Technology Trends Presentation For Power Symposium

Transcription

1 Technology Trends Presentation For Power Symposium Darryl Solie, Distinguished Engineer, Chief System Architect IBM Systems & Technology Group From Ingenuity to Impact Copyright IBM Corporation 2005

2 Agenda What s driving technology today? Why Cell BE today? Emerging System Strategy Scale Out & Acceleration Intel s direction IBM Engineering & Technology Services 2005 IBM Corporation 2

3 3 When Moore Is Less, Watts Happen IBM Engineering & Technology Services 2002 IBM Corporation

4 4 A Second Observation: Where have all the Gigahertz gone? IBM Engineering & Technology Services 2002 IBM Corporation

5 Technology Scaling We ve hit the wall Relative Device Performance Conventional Bulk CMOS SOI (silicon-on-insulator) High mobility Double-Gate Year? IBM Engineering & Technology Services 2005 IBM Corporation 5

6 What s causing the problem? nm 10S Tox=11A Gate Stack Gate dielectric approaching a fundamental limit (a few atomic layers) Power Density (W/cm 2 ) Active Power Passive Power Gate Length (microns) Gate Length (microns) 0.01 IBM Engineering & Technology Services 2005 IBM Corporation 6

7 Has This Ever Happened Before? Steam Iron 5W/cm2? Opportunity IBM Engineering & Technology Services 2005 IBM Corporation 7

8 Engineering & Technology Services Cell Processor Chip Overview 3 GHz 64 Bit PowerPC Processor 8 SPU s (VMX-like accelerators) 25 GBytes/sec memory bandwidth Mem. Contr. 64b Power Processor Synergistic Processor Up to 75 GBytes/sec I/O bandwidth GByte High Speed Memory Flexible IO... Synergistic Processor ~ 95 3 GHz Page 8 IBM Corporation 2005

9 Engineering & Technology Services Cell BE Processor Overview Heterogeneous multi-core system architecture - Power Processor Element for control tasks - Synergistic Processor Elements for data-intensive processing Synergistic Processor Element (SPE) consists of - Synergistic Processor Unit (SPU) - Synergistic Memory Flow Control (SMF) Data movement and synchronization Interface to highperformance Element Interconnect Bus SPE SPU SXU 16B/cycle LS SMF SPU SXU PPE LS SMF L2 SPU SXU LS SMF 16B/cycle PPU L1 SPU SXU LS SMF 32B/cycle 16B/cycle EIB (up to 96B/cycle) PXU SPU SXU LS SMF SPU SXU LS SMF 16B/cycle MIC Dual XDR TM SPU SXU LS SMF SPU SXU BIC LS SMF FlexIO TM 16B/cycle (2x) 64-bit Power Architecture with VMX Page 9 IBM Corporation 2005

10 Engineering & Technology Services General Purpose Cores vs Synergistic Processor Elements Optimized acceleration can provide significant advantages Page 10 IBM Corporation 2005

11 Engineering and Technology Services Theoretical Peak Operations FP (SP) FP (DP) Int (16 bit) Int (32 bit) 250 Billion Ops / sec Freescale MPC8641D 1.5 GHz AMD Athlon 64 X2 2.4 GHz Intel Pentium D 3.2 GHz PowerPC 970MP 2.5 GHz Cell Broadband Engine TM 3.2 GHz IBM Corporation

12 Cell BE Performance BE s performance is about an order of magnitude better than traditional GPPs for media and other applications that can take advantage of its SIMD capability BE can outperform a P4/SSE2 at same clock rate by 3 to 18x (assuming linear scaling) in various types of application workloads Type Algorithm 3 GHz GPP 3 GHz BE BE Perf Advantage HPC Matrix Multiplication (S.P.) 25 Gflops 190 GFlops (8SPEs) 8x Linpack (S.P.) 18 GFlops (IA32) 150 GFlops (BE) 8x Linpack (D.P.) 6 GFlops (IA32) 12 GFLops (BE) 2x bioinformatic smith-waterman 570 Mcups (IA32) 420 Mcups (per SPE) 6x graphics transform-light 160 MVPS (G5/VMX) 240 MVPS (per SPE) 12x TRE 1.6 fps (G5/VMX) 24 fps (BE) 15x security AES 1.1 Gbps (IA32) 2Gbps (per SPE) 14x TDES 0.12 Gbps (IA32) 0.16 Gbps (per SPE) 10x MD Gbps (IA32) 2.3 Gbps (per SPE) 6x SHA Gbps (IA32) 1.98 Gbps (per SPE) 18x communication EEMBC 501 Telemark (1.4GHz mpc7447) 770 Telemark (per SPE) 12x video processing mpeg2 decoder (sdtv) 200 fps (IA32) 290 fps (per SPE) 12x IBM Systems & Technology Group 12

13 IBM Server Strategy Large SMPs Clusters and Virtualization Scale Up / SMP Computing High Density Racks/Blades Scale Out / Distributed Computing IBM Engineering & Technology Services 2005 IBM Corporation 13

14 Engineering & Technology Services IBM BladeCenter Page 14 IBM Corporation 2005

15 Blue Gene/L Lawrence Livermore System Processors / Floating Point Units 360 Teraflops / 16 Terabytes of Memory 10X Performance / 28X Less Power / 10X smaller IBM Engineering & Technology Services 2005 IBM Corporation 15

16 Blue Gene/L Compute SoC 2 PPC 440 Processors 4 DP Floating Point Units 4 MB EDRAM Full Mesh Toroid Interconnect Integrated Memory Control/Ethernet ~ Watts/Chip PLB (4:1) 32k/32k L1 440 CPU Double FPU 32k/32k L1 440 CPU I/O proc Double FPU 128 L2 snoop 128 L Multiported Shared SRAM Buffer 256 Shared L3 directory for EDRAM Includes ECC ECC 4MB EDRAM L3 Cache or Memory l 128 Ethernet Gbit JTAG Access Torus Tree Global Interrupt DDR Control with ECC Gbit Ethernet JTAG 6 out and 6 in, each at 1.4 Gbit/s link 3 out and 3 in, each at 2.8 Gbit/s link 144 bit wide DDR 256MB IBM Engineering & Technology Services 2005 IBM Corporation 16

17 Intel EMEA Academic Forum 5/05 IBM Systems & Technology Group 17

18 Intel EMEA Academic Forum 5/05 IBM Systems & Technology Group 18

19 So..Where do we go next? - (More) Application Specific Acceleration! IBM Engineering & Technology Services 2005 IBM Corporation 19