Digital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification Part II

Transcription

1 Digital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification Part II Ahmed Abu-Hajar, Ph.D. abuhajar@digitavid.net Digitavid, Inc San Jose, CA

2 VHDL Lexical Description Code must be written in ASCII text format Lexical Elements: a sequence of elements that makes up a fundamental elements such as: Delimiter: is a character that is used to separates lexical elements such as: & ( ) * +, - / : ; < = > Compound delimiter: A sequence of two or more delimiters such as: => ** := /= >= <> -- Identifier: Is a reserved word that has special meaning in the language User defined identifiers: words defined by users to name variables, blocks, constants, entities, ect. Must start with a letter and may include numbers, digits, isolated underline character. All identifiers be distinct and user defined identifiers should be distinct from the reserved identifiers Comments: comments starts after -- until the end of line. Signal A : std_logic; -- comments until end of line -- every thing after -- will be ignored by the compiler Character Literal: a character between two apostrophes A d 1 used to define scalar values for initializing scalar objects String Literal: A sequence of characters placed in between two quotation marks The sequence of these characters is string a -- with length 1 -- with length 0 How are you -- with length 11 if the string longer than one line, must use the concatenation operator &. This string is long for one line. Then we & use the concatenation operator

3 VHDL Lexical Description Bit String Literal: Is a string of digits enclosed by quotation marks. The base of the bits is indicated by placing a letter in front of the bit string. B B means Binary (0-1) O O means Octal (0-7) X A8F9 -- X means Hexadecimal (0-F) No letter means Binary Separating the digits for easier readability using underline char _ is allowed only if the base is specified. B 1111_ allowed 1111_ Not allowed Abstract Literal: Has numerical values which are integer or real. VHDL divide them into to types Decimal Literal: Use E letter to give the exponent part, and may use under line char for readability 6, 67_345, 2.680E-8,.

4 VHDL Data Types Data Types Scalar FILE Access COMPOSIT Enumeration Numeric Physical Record Array Real Integer

5 Scalar Data types Enumeration data type: Their value is assigned in their listed order. Predefined build in in the VHDL standard libraries: Type Boolean is (FALSE, TRUE); Type Bit is ( 0, 1 ); Type STD_ULOGIC( U, X, 0, 1, Z, W, L, H, - ); Type character is uses ASCII 128 charters. Severity Level associated with the assert statement. User defined Enumeration types Type state is (S0, S1, S2); Type color is ( RED, BLUE, GREEN, YELLOW);

6 Scalar Data types We can define subtypes of predefined and user defined types. Predefined subtype is std_logic defined in the EEE_std_logic_std_1164 package as a sub type from std_ulogic. Subtype std_logic is std_ulogic ( X, 0, 1, Z, W, L, H, - ); Numeric data type: Real and Integer The range is bounded over [ , ] The type can be in descending or ascending order. Examples type index range 0 to 7; -- ascending type down_counter range 15 downto 0; -- descending type temp range 0.0 to 100.0; -- ascending

7 Scalar Data types Physical data type: is a scalar numeric type associated with a system of units or physical measurements. Time is the only predefined physical type Other physical data types may be user defined type time is range 0 to 1E20; units fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 ns; s = 1000 ms; min = 60 s; hr = 60 min; end units;

8 Composite Data types Composite Date Type Array is composed of several data elements where all has the same type. Predefined Arrays String is an array of character types Bit_vector is array of bit types Std_logic_vector is an array of std_logic Syntax for defining Array Type string is array (positive range <>) of char; Type bit_vector is array (natural range <> ) of bit; Type std_logic_vector is array (natural range <>) of std_logic

9 Scalar Data types Notes: 1- The rang of the array s indexes is place between parentheses 2- positive is type positive does not include 0 3- natural is type natural which includes 0 4- <> means the range is unconstrained User Defined Array: Very useful for register level designs, Why? Examples: Type register_16_bit is array (15 downto 0) of std_logic; Type counter_32_bit is array(0 to 31) of bit; Range may be in ascending or descending order Array of an Array Type register_16_bit is array (15 downto 0) of std_logic; Type ROM is array (natural range <>) of register_16_bit; 2-D array Type 2_D_array is array (natural range <>, natural range<> ) of bit;

10 Data type Attributes Attributes are functions that return value, type or range associated with various types of codes Attributes May be predefined or user defined User define attribute do not affect the simulation Enumeration and Scalar attributes pos attribute indicates the position of the data in the list. Example: For the lets define color as Type COLOR is ( RED, BLUE, GREEN, YELLOW);, COLOR pos(green) reads as color tick pos of green which returns the position of the green color which is 2. COLOR val(2) return GREEN -- returns the color at index (2) COLOR left returns RED, and COLOR right return YELLOW high and low returns most high and most low data. leftof and rightof returns the data the next left or next right symbol COLOR leftof (GREEN) = BLUE COLOR rightof(green) = YELLOW pred and succ gives the preceded and the succeeded values

11 Data type Attributes Enumeration and Scalar attributes Example: For the lets define color as Type COLOR is ( RED, BLUE, GREEN, YELLOW);, COLOR pos(green) reads as color tick pos of green which returns the position of the green color which is 2. COLOR val(2) returns GREEN -- returns the color at index (2) COLOR left returns RED, and COLOR right return YELLOW high and low returns most high and most low data. leftof and rightof returns the data the next left or next right symbol COLOR leftof (GREEN) = BLUE COLOR rightof(green) = YELLOW pred and succ gives the preceded and the succeeded values Attributes for Array: Example: lets define a 32 bit word as an array Type word is array (range 31 downto 0) of bit; word range returns range 31 downto 0 word length returns 32 word left returns 31 word right returns 0 word high returns 15 word low returns 0

12 VHDL Data Objects 1- Constants assigned value do not change 2- Variables are used for indexes 3- Signals carry voltage 0 or 1 volts Constants The value of a constant is specified when it is declared. The data type of constants must be defined before declaration A Constant value is specified using := delimiter Examples: Constants PI : real := Constant A : bit := L ; Constant Next_state : state :=s0;

13 VHDL Data Objects Variables Variables must be declared before they have been used Variables are only declared within a process or a subprogram Must specify data type when variables are declared Initializing variable to a value at declaration is optional If a variable is not initialized, its default value is the most left element of the data type declared Examples: variable a,b,c : std_logic; variable index : integer range 0 to 100; variable a : std_logic_vector (7 downto 0); variable X : real :=1.2;

14 VHDL Data Objects Signals Signals are declared as: Ports in the entity declaration section Intermediate nodes in the signal declaration section of the Architecture. Before the begin statement Signals are nodes that carry voltage which may change with time. Only port signals my be exposed to other entities Input ports may not be assigned values Signal declaration has the same rules as variables signal x1, x2, x3 : bit; signal Reg1 :std_logic_vector(16 downto 0); signal a, b : std_logic := 0 ;

15 VHDL Data Objects More on Signals Signals are assigned using the <= delimiter Signals may carry future data using after a <= b, 1 after 10ns, 0 after 20ns, c after 40ns; f <= c OR d; If a signal is assigned to value without any delays, then simulation will apply the change after δ seconds. Where δ is the simulation sub-interval. Transaction: If a signal is scheduled a value but the actual value may or may not change. Event: when the signal s value change Use <= for signal assignment and := for variable assignment.

16 VHDL Data Objects Signal Attributes X event: Returns TRUE if the value of X changed during the current simulation time δ, else it returns fales X stable(n): Returns TRUE if X did not have an event during the past n seconds, else it returns FALSE. X active: Returns TRUE is the signal is has transaction during the current simulation time δ, else it returns False X quiet(n): Retuen TRUE when X has no transaction during the past n seconds, else it returns FALSE. X last_active: Returns the amount of time elapsed since the last Transaction. X last_event: Returns the amount of time elapsed since the last event. X last_value: Returns the value of X just before the last Change. X delayed(n): Delays the signal X for n seconds;

17 Example: 16-bit Ripple Adder 16-bit Full Adder ( ripple carry full adder) Open new source in Project Navigator and define an entity called my_16_bit Full_adder The entity has 2 16-bit, inputs, one cin input, one 16-bit output and one cout output Cout a b 16-bit Full Adder Sum Cin

18 Example 16-bit Ripple Adder Entity my_16_bit_adder is Port ( a,b : in STD_LOGIC_VECTOR (15 downto 0); Cin : in STD_LOGIC; Cout : out STD_LOGIC; sum : out STD_LOGIC_VECTOR (15 downto 0)); end my_16_bit_adder; a b Cout 16-bit Full Adder Cin Sum

19 Example: 16-bit Ripple Adder Open new source for simulation Name it TB_my_16_bit_adder ENTITY TB_My_16_bit_adder_vhd IS END TB_My_16_bit_adder_vhd; ARCHITECTURE behavior OF TB_My_16_bit_adder_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT my_16_bit_adder PORT(a : IN std_logic_vector(15 downto 0); b : IN std_logic_vector(15 downto 0); Cin : IN std_logic; Cout : OUT std_logic; sum : OUT std_logic_vector(15 downto 0) ); END COMPONENT;

20 Example: 16-bit Ripple Adder ARCHITECTURE behavior OF TB_My_16_bit_adder_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT my_16_bit_adder END COMPONENT; --Inputs SIGNAL Cin, Cout : std_logic := '0'; SIGNAL a, b, sum : std_logic_vector(15 downto 0) := (others=>'0'); BEGIN -- Instantiate the Unit Under Test (UUT) uut: my_16_bit_adder PORT MAP( a => a, b => b, Cin => Cin, Cout => Cout, sum => sum ); a <= X"000F", X"0fff" after 20ns; b <= X"000F", X"0fff" after 30ns; cin <= '0'; END;