[1] Douglas L. Perry, VHDL, third edition, ISBN , McRaw- Hill Series on Computer Engineering.
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1 Lecture 12 1 Reference list [1] Douglas L. Perry, VHDL, third edition, ISBN , McRaw- Hill Series on Computer Engineering. [2] Kevin Skahil, VHDL for programmable logic, ISBN Addison-Wesley. [3] David Pellerin, Douglas Taylor, VHDL Made Easy, ISBN Prentice Hall. [4] Ben Cohen, VHDL Answers to Frequently Asked Question, 2nd edition, ISBN , Kluwer Academic Publishers. [5] Sudhakar Yalamanchili, Introductory VHDL Simulation to Synthesis, ISBN , Prentice Hall. [6] Digital design with Hardware Description Languages, Mark Davidson, Jyrki Alamaunu, Tommi Zetterman, Autum [7] Peter J Ashenden, The Student s Guide to VHDL, ISBN Morgan Kaufmann Publishers, Inc, San Francisco California, [8] DIGITAL INTEGRATED CIRCUITS a design perspective, second ed., Jan M. Rabaey, Anantha Chandrakasan, Borivoje Niklic', Prentice Hall, ISBN [9] Digital Design, Prinsiples and Practices, fourth ed., John F. Wakerly ISBN
2 Operators Adding Operators Operators can be used to describe arithmetic functions or, in the case of arrays types, concatenation operations. Operator Description Operand types Result type + addition any numeric type same type - subtraction any numeric type same type & concatenation any numeric type same type & concatenation any array or element type same array type [3]p.94 3 Operators Multiplying Operators Operators can be used to describe mathematical function on numeric types. Operator Description Operand types Result type * multiplication Left: any integer or same type floating point type Right: same type * multiplication Left: any physical type same type Right: integer or real type * multiplication Left: any integer or real same as right Right: any physical type [3]p.94 4
3 Operators Dividing Operators Operator Description Operand types Result type / division any integer or same type floating point type / division Left: any physical type same as left Right: any integer or real type / division Left: any physical type integer Right: same type [3]p.95 5 Operators Sing Operators Operators can be used to specify the sign of a numeric object or literal. Operator Description Operand types Result type + identity any numeric type same type - negation any numeric type same type [3]p.95 6
4 Operators Miscellaneous Operators Operator Description Operand types Result type ** exponentiation Left: any integer type same as left Right: integer type ** exponentiation Left: any floating point same as left type Right: integer type abs absolute value any numeric type same numeric type not logical negation any bit or Boolean type same type [3]p.96 7 Operators Shift Operators ( only) Operator Description Operand types Result type sll shift left logical Left: any one-dimensional same as left array type whose element operand type type is bit or Boolean Right: Integer type srl shift right logical same as above same as above sla shift left arithmetic same as above same as above sra shift right arithmetic same as above same as above rol rotate left logical same as above same as above ror rotate right logical same as above same as above [3]p.96 8
5 IEEE Standard 1164 An object of type bit has only two possible values, 0 and 1. Simulation and synthesis require other values Problem with type bit Nine state system defined and agreed by IEEE (Standard 1164). [6], [3]p IEEE Standard 1164 These nine values make it possible to accurately model the behavior of digital circuit during simulation. Does the circuit behave in an unexpected manner with unknown input value? For synthesis users, the standard has additional benefits for describing circuits involve output enable. [3]p
6 IEEE Standard 1164 To use IEEE 1164 standard logic data types, you will need to add at least two statements to your VHDL source files. Load the ieee 1164 standard library library ieee ; use ieee.std_logic_1164.all ; Its contents made visible [3]p IEEE Standard 1164 If your source file includes more than one design units, you need to repeat use statement just prior to each design unit. library ieee ; use ieee.std_ulogic_1164.all ; package my_package is. end my_package ; use ieee.std_ulogic_1164.all ; entity first_one is. end first_one ; architecture structure of first_one is. end first_one ; use ieee.std_ulogic_1164.all ; entity second_one is. end second_one ; [3]p
7 IEEE Standard 1164 Package std_logic_1164 Two fundamental data types: std_ulogic std_logic Enumerated types are defined with nine symbolic values (single character). [3]p IEEE Standard 1164 std_ulogic -- logic state system (unresolved) TYPE std_ulogic IS ('U', --Uninitialized 'X', --Forcing unknown '0', --Forcing 0 '1', --Forcing 1 'Z', --High impedance 'W', --Weak unknown 'L', --Weak 0 'H', --Weak 1 '-', --Don t care ) ; See package std_logic_1164 [4]p.355 [4]p.355, [3]p
8 IEEE Standard 1164 std_ulogic Data type is unresolved type. It is illegal for two values to be simultaneously driven onto a signal signal of type std_ulogic. ( such as '0' and '1' or '1' and 'Z') The use of unresolved types will ensure automatic detection of multiple drivers by a compiler. [4]p.95, [3]p IEEE Standard 1164 std_logic Data type is resolved type based on std_ulogic. Resolved types are declared with resolution functions. Resolution functions define the resulting behavior when an object is driven with multiple values simultaneously. You can drive simultaneously different values onto a signal of type std_logic. [3]p
9 IEEE Standard 1164 std_logic_vector, std_ulogic_vector Both are defined in the std_logic_1164 package as unbounded arrays unconstrained array of std_ulogic for use with the resolution function TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic ; unconstrained array of std_logic for use in declaring signal arrays TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_logic ; [4]p.356, [3]p IEEE Standard 1164 std_logic_vector, std_ulogic_vector std_ulogic_vector is unresolved std_logic_vector is resolved IEEE recommends using the resolved types : std_logic std_logic_vector We may have difficulties to catch erroneous multiple drivers of signals. [6] 18
10 Attributes Attributes allow you to extract additional information about an object that may not be directly related to the value that object carries. Predefined attributes Also user can define attributes [6], [3]p Attributes Predefined attributes Some predefined attributes for scalar types, constrained array types and any objects declared to be of array types: Predefined attributes are always applied to a prefix. X'high X'low X'left X'right returns the upper bound of a given scalar type or subtype returns the lower bound of a given scalar type or subtype returns the left-most bound of a given type or subtype returns the right-most bound of a given type or subtype For constrained array types only. X'range returns the range value for a constrained array X'length returns the number of elements of an array [6], [3]p
11 Attributes Examples Predefined attributes type bit_array is array (1 to 5) of bit ; variable L : integer := bit_array'left ; --L has value of 1 variable R : integer := bit_array right ; --R has value of 5 type bit_array is array (-15 to +15) of bit ; variable H : integer := bit_array'high ; --H has value 15 type bit_array is array (15 downto 0) of bit ; variable L : integer := bit_array'low ; --L has value of 0 type bit_array is array (0 to 31) of bit ; variable LEN : integer := bit_array'length ; --LEN has value of 32 [3]p Attributes Predefined attributes X event X active X last_event X last_active X last_value returns true value when signal X changes its value. returns true value when signal X assigned to. returns the time elapsed since the previous event occur- ring on this signal X. returns the time elapsed since the last transaction (scheduled event) of the signal X. returns the value of signal X prior to the last event. These attributes are predefined for any signal X. [6], [3]p
12 Attributes Examples Predefined attributes if Clk = '1' and Clk'event then --Look for clock edge if Clk'event and Clk = '1' then --Look for clock edge process variable T : time ; begin Q <= D after 5ns ; wait 10ns ; T := Q'last_event ; --T gets a value 5ns. end process ; [3]p Attributes Custom attributes Custom attributes are those attributes that are not defined in the IEEE specifications, but you (or your simulation or synthesis tool vendor) define for your own use. Example: Attribute enum_encoding is provided by a number of synthesis tool vendors (most notably Synopsys). attribute enum_encoding : string ; Attribute declaration type statevalue is ( INIT, IDLE, READ, WRITE, ERROR); attribute enum_encoding of statevalue : type is " " ; [3]p
13 Attributes Example Custom attributes library SYNOPSYS; use SYNOPSYS.attributes.all; entity dtkfsm is port (dr: in STD_LOGIC; kello: in STD_LOGIC; reset: in STD_LOGIC; dtk: out STD_LOGIC); end; architecture dtkfsm_arch of dtkfsm is -- BINARY ENCODED state machine: Sreg0 type Sreg0_type is (S1, S2, S3, S4); attribute enum_encoding of Sreg0_type: type is "00 " & -- S1 "01 " & -- S2 "10 " & -- S3 "11"; -- S4 signal Sreg0: Sreg0_type;. Attribute enum_encoding is declared in library SYNOPSYS 25 Modeling Now we know something about entity, ports, data objects, types, variables and attributes, etc.. Next we learn basics of the describing of the architecture. VHDL allows both concurrent and sequential statements to be entered. 26
14 Modeling Concurrent statements All statement in concurrent area are "executed at the same time". Begin There is no significance to the order in which the statements are entered. Statement Statement Statement End [3]p Modeling Sequential statements Sequential statements are executed one after in the order that they appear. Begin Statement Statement Note! Writing a description of a circuit using sequential programming features of VHDL does not necessarily mean that circuit being described is sequential in its operation. (Combinational/FSM) Statement End [3]p
15 Modeling Sequential statements Concurrent Sequential statements Sequential statements Sequential statements While the statements in the body of the process are executed sequentially, the body of the process is treated by VHDL as all other concurrent statements in the simulation. [3]p Modeling Sequential statements If statement Case statement Null statement Loop statement Assertion and Report statement [7]p
16 Modeling Signal assignment statement a <= b ; Statement will be executed whenever signal b changes value. Sensitivity list of signal assignment statement (signal b) Whenever a signal in the sensitivity list changes value, the signal assignment statement is executed. [1]p Modeling Syntax for the signal assignment statement Signal assignment statement VHDL87 target <= [transport] waveform ; waveform_element {, waveform_element } unaffected value_expression [ after time_expression ] null [ after time_expression ] [4]p.349,
17 Modeling Syntax for the signal assignment statement Signal assignment statement VHDL93 [label : ] target <= [delay_mechanism] waveform ; transport [reject time_expression] inertial [4]p. 349, Modeling Examples: Signal assignment statement time ns clock_a <= '0', '1' after 10 ns, '0' after 20 ns, '1' after 40 ns ; [5]p
18 Modeling Examples: Signal assignment statement c <= a and b after 5 ns ; y1 <= not ( a and b ) after 7 ns ; y2 <= not ( a and b ) transport after 7 ns ; y1 <= reject 3 ns not ( a and b ) after 7 ns ; [3]p. 158, Modeling Inertial delay If no delay type is specified, then inertial delay is used. Inertial delay is default in VHDL. Inertia value is equal to the delay through the device. A B B delay = 20 ns B < = A after 20 ns ; A [1]p
19 Modeling Transport delay Transport delay works like propagation delay on a wire. Transport delay must be specified, because delay type is not default. A delay = 20 ns B B A [1]p The End 38
[1] Douglas L. Perry, VHDL, third edition, ISBN , McRaw- Hill Series on Computer Engineering.
![[1] Douglas L. Perry, VHDL, third edition, ISBN , McRaw- Hill Series on Computer Engineering.](/thumbs/83/87451311.jpg "[1] Douglas L. Perry, VHDL, third edition, ISBN , McRaw- Hill Series on Computer Engineering.")
Lecture 10 1 Reference list [1] Douglas L. Perry, VHDL, third edition, ISBN 0-07-049436-3, McRaw- Hill Series on Computer Engineering. [2] Kevin Skahil, VHDL for programmable logic, ISBN 0-201-89586-2
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