Digital Systems Design
|
|
- Ambrose Fisher
- 5 years ago
- Views:
Transcription
1 IAY 0600 Digital Systems Design VHDL discussion Dataflow Style Combinational Design Tallinn University of Technology Combinational systems Combinational systems have no memory. A combinational system's outputs are a function of only its present input values. No latches/ffs or closed feedback loop Combinational system description can be in dataflow, behavioral, or structioral styles. Concurrent signal assignment signal is basic for dataflow style combinational design. We consider three kinds of concurrent signal assignment: Concurrent signal assignment statement using a Boolean expression Selected signal assignment statement Conditional signal assignment statement 2 4-to-1 multiplexer using a Bool. expression Selected signal assignment statement library ieee; use ieee.std_logic_1164.all entity mux4to1 is port (c3, c2, c1, co: in std_logic; g_bar, b, a: in std_logic; y: out std_logic); end mux4to1; architecture dataflow of mux4to1 is y <= not g_bar and ( (not b and a and c0) or (not b and a and c1) or (b and not a and c2) or (b and a and c3)); end dataflow; Simplified syntax: with select_expression select signal_name <= value_expr_1 when choice_1, value_expr_2 when choice_2, value_expr_3 when choice_3,... value_expr_n when choice_n; The value of one and only one choice must equal the value of the select expression. 3 4 Notation used in syntax definitions Syntax refers to the patern or structure of the word order in a prase. Definitions are simplified for instructional purposes. Selected signal assignment statement (ex.) library ieee; use ieee.std_logic_1164.all entity mux4to1 is port (c3, c2, c1, c0: in std_logic; g_bar, b, a: in std_logic; y: out std_logic); end mux4to1; architecture selected of mux4to1 is with std_logic_vector' (g_bar, b, a) select y <= c0 when "000", c1 when "001", c2 when "010", c3 when "011" '0' when others; -- default end selected; Here we use an aggregate (g_bar, b, a) in a select expression 5 6
2 Type qualification. Choices completeness We must explicitly specify the aggregat's (g_bar, b, a) type. This is accomplished using a type qualification ('): std_logic_vector' (g_bar, b, a) To describe combinational logic, the choices listed in a selected signal assignment must be all inclusive. That is, they must include every possible value of the select expression. y <= c0 when "000", The last clause (default assignment) uses the keyword c1 when "001", others to assign the value of 0 c2 when "010", to y for the 725 values of the c3 when "011" select expression not explicitly listed. '0' when others; 9**3=729, 729-4=725 7 Conditional signal assignment statement The result from evaluating a condition is type boolean. type boolean is (false, true) ; The leftmost literal in an enumeration listing is in position 0. Each enumeration type definition defines an ascending range of position numbers. Example: type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-') ; ' Z ' (with position number 4) iz greater than ' 1 ' (with position number 3 8 Conditional signal assignment statement Avoiding implied latches library ieee ; use ieee.std_logic_1164.all ; entity mux4to1 is port (c3, c2, c1, co: in std_logic; g_bar, b, a: in std_logic; y: out std_logic); end mux4to1; architecture conditional of mux4to1 is signal tmp : std_logic_vector (2 downto o); tmp <= (g_bar, b, a); y <= c0 when tmp = "000" else c1 when tmp = "001" else c2 when tmp = "010" else c3 when tmp = "011" else '0' ; -- default assignment end conditional; 9 The last value_expression must not have an associated when condition clause (default assignment). For example, let s take previous description. If the conditional signal is written as: y <= c0 when tmp = "000" else c1 when tmp = "001" else c2 when tmp = "010" else c3 when tmp = "011" ; the VHDL interpretation of this construct is that, for the 4 specified values of tmp, a new value should be assigned to y. This implies that for all other values of tmp the y should retain its previous value. As a result, the synthesizer generates a latch at the output of the combinational logic to store the value of y. 10 Synthesised mux logic with undesired latch Nondesirable feedback loop Signal assignment statement with a closed feedback loop: a signal appears in both sides of a concurrent assignment statement For example, q <= ((not q) and (not en)) or (d and en); Syntactically correct Form a closed feedback loop Should be avoided 11 12
3 Behavioral style features Behavioral Style Combinational Design (non-)synthesizing Loops (paryty detector example) Tallinn University of Technology A behavioral style architecture uses algorithms in the form of sequential programs. These sequential programs are called processes. The statement part of a behavioral style architecture consists of one or more processes. Each process statement is, in its entirety, a concurrent statement. Process communicate with each other, and with other concurrent statements, using signals. Statements inside a process are sequential statements. They are executed in sequence and their order is critical to their effect. Sequential control statements select between alternative statement execution paths. 14 Dataflow style half-adder description library ieee; use ieee.std_logic_1164. all; entity half_adder is port (a, b : in std_logic; sum, carry_out : out std_logic); end half_adder; architecture data_flow of half_adder is sum <= a xor b ; carry_out <= a and b ; end data_flow; -- concurrent signal assignment -- concurrent signal assignment Signal assignment statement placed in the statement part of an architecture is a concurrent statement. 15 Behavioral style half-adder description entity half_adder is port (a, b : in std_logic; sum, carry: out std_logic); end half_adder; architecture behavior of half_adder is ha: process (a, b) if a = 1 then sum <= not b ; carry <= b ; --sequential signal assignments else sum <= b ; carry <= 0 ; end if; end process ha ; end behavior ; 16 Process statement Process st-ment and combinational logic A process statement is a concurrent statement that itself is comprised of sequential statements. No signals can be declared in a process. A process with a sensitivity list must not contain any wait statements. A process without a sensitivity list must contain at least one wait statement, or its simulation will never end. A process can be viewed as an infinite loop whose execution is repeatedly suspended and resumed. 17 Processes statements can be used to describe combinational or sequential systems. Two requirements for a process to synthesize to a combinational system are: The process s sensitivity list must contain all signals read in the process. A signal or variable assigned a value in a process must be assigned a value in all possible executions of the process. 18
4 Process communication In this example, three processes are communicating, using signals (s1, s2, s3), to implement a full adder. Process communication using signals is similar to the way components in a structural description communicate (are connected). 19 Full adder representation library ieee; use ieee.std_logic_1164. all; entity full_adder is port (a, b, carry_in : in std_logic; sum, carry_out : out std_logic); end full_adder; architecture processes of full_adder is signal s1, s2, s3 : std_logic; -- Signals to interconnect -- Each process is a concurrent statement ha1: process (a, b) -- ha1 process if a = ' 1 ' then s1 <= not b ; s2 <= b ; else s1 <= b ; s2 <= 0 ; end if; end process ha1; 20 Full adder representation (cont.) ha2: process (s1, carry_in) -- ha2 process if s1 = ' 1 ' then sum <= not carry_in ; s3 <= carry_in ; else sum <= carry_in ; s3 <= ' 0 ' ; end if; end process ha2 ; or1: process (s3, s2) -- or1 process if ( s3 = ' 1 ' ) or ( s2 = ' 1 ' ) then carry_out = ' 1 ' ; else carry_out = ' 0 ' ; end if; end process or1 ; end processes 21 PARYTY DETECTOR EXAMPLE (NON-)SYNTHESIZING LOOPS 22 Dataflow description of parity detector Output oddp is asserted when the number of 1s in the input vector is odd, otherwise it is unasserted. library ieee; use ieee.std_logic_1164. all ; entity parity is port (din : in std_ logic _ vector (3 downto 0) ); oddp : out std_logic -- aserted for odd parity) ; end parity ; architecture dataflow of parity is oddp <= din (3) xor din (2) xor din (1) xor din (0) ; end dataflow ; Simulation of dataflow style parity detrector The testbench sequences through all possible binary input combinations. Input vector din is diplayed as both a composite signal, whose value is expressed in hexadecimal, and in terms of its separate elements
5 Behavioral parity detector (failed)description Simulation of parity detector Architecture for parity detector written using a loop and a signal: architecture bihav_sig of parity is signal odd : std_logic ; po : pocess (din) odd <= ' 0 ' ; for index in 3 downto 0 loop odd <= odd xor din (index) ; end loop ; end process ; oddp <= odd ; end behav_sig ; 25 Waveforms from simulation of parity detector written using a loop and a signal. The simulation resulted in oddp always having the value U. Why??? 26 How a RTL synthesizer synthesizes a loop The synthesizer unrolls the loop to create the sequence of statements that corresponds to the complete execution of the loop. One copy of the sequence of statements inside the loop is created for each loop iteration. In each copy, the loop parameter is replaced by its value for that loop iteration. The loop is replaced by the statements created by unrolling the loop (behavior is not changing). odd <= '0' ; for index in 3 downto 0 loop odd <= odd xor din (index) ; end loop ; odd <= '0' ; odd <= odd xor din (3) ; odd <= odd xor din (2) ; odd <= odd xor din (1) ; odd <= odd xor din (0) ; How a RTL synthesizer synthesizes a loop Since odd is a signal, the assignment of a value to it does not take affect until the process suspends. As a result, only the last assignment to odd before the process suspends is meaningful. odd <= odd xor din (0) ; Accordingly, the synthesizer synthesizes next logic: Explanation of simulation result XOR function in STD logic From last assignment statement < odd <= odd xor din (0); > it is clear why the simulation resulted in oddp always having the value U. At initialization, odd is given the value U. After the process suspends odd is assigned U xor din (0), which evaluates to U (look the next slide). Thus the process always computes the value U for odd (that is assigned than to oddp) truth table for "xor" function CONSTANT xor_table : stdlogic_table := ( U X 0 1 Z W L H ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- U ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- X ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- 0 ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- 1 ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- Z ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- W ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- L ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- H ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- - ); 30
6 Solution of the problem We need each assignment to odd to take immediately. Thus, we need to use variable to store the value of odd. Look the next slide: the design description is modified by replacing the signal declaration for in the declarative part of the architecture body with a variable declaration for odd in the declarative part of the process. The Sequence of sequential assignments made to variable odd: odd := ' 0 ' ; odd := odd xor din (3) ; odd.= odd xor din (2) ; odd := odd xor din (1) ; odd := odd xor din (0) ; Since assignments take effect immediately, the algorithm work as desired 31 Using variables Architecture for parity detctor written using a loop and variable: architecture bihav_var of parity is po : pocess (din) variable odd : std_logic; -- declare a variable default value odd := ' 0 ' ; for index in 3 downto 0 loop odd := odd xor din (index) ; end loop ; oddp <= odd ; end process ; end behav_var ; 32 Synthesis of processes Logic resulting from synthesis using the architecture written with a loop and variable odd := ' 0 ' ; odd := xor din (3) ; odd.= xor din (2) ; odd := xor din (1) ; odd := xor din (0) ; 33 Loops that cannot be synthesized To synthesize a loop, a RTL synthesizer must unroll the loop. This requires that the number of loop iterations be known during synthesis. Thus a for loop with constant bounds can be synthesized. If a variable were used in specifying the loops range bounds (nonconstant bounds), the synthesizer could not statically determine the number of loop iterations. Also a synthesizer cannot statically determine the number of loop iterations of a while loop, since completion of a while loop is dependent on data generated during the loop s execution. 34 Avoiding latches To ensure that the logic synthesized from a process is combinational, all signals and vatiables assigned a value in the process must be assigned a value each time the process executes. If this requirement is not met, latches may be inferred. To insure this requirement is met it might be helpful to assign a default value at the ning of the process to each signal or variable that is assigned values later in the process. 35
Digital Systems Design
IAY 0600 Example: HalfAdder Behavior Structure Digital Systems Design a b Sum Carry 0 0 0 0 0 1 1 0 a b HalfAdder Sum Carry 1 0 1 0 VHDL discussion Dataflow Style Combinational Design 1 1 0 1 a Sum Sum
More information2/14/2016. Hardware Synthesis. Midia Reshadi. CE Department. Entities, Architectures, and Coding.
Hardware Synthesis MidiaReshadi CE Department Science and research branch of Islamic Azad University Email: ce.srbiau@gmail.com Midia Reshadi 1 Chapter 2 Entities, Architectures, and Coding Styles Midia
More informationECE 545 Lecture 5. Data Flow Modeling in VHDL. George Mason University
ECE 545 Lecture 5 Data Flow Modeling in VHDL George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 4, Concurrent Signal Assignment Statements of VHDL 2 Types of VHDL Description
More informationOutline. Concurrent Signal Assignment Statements. 2. Simple signal assignment statement. 1. Combinational vs. sequential circuit
Outline Concurrent Signal Assignment Statements 1. Combinational versus sequential circuit 2. Simple signal assignment statement 3. Conditional signal assignment statement 4. Selected signal assignment
More informationDigital Systems Design
Digital Systems Design Review of Combinatorial Circuit Building Blocks: VHDL for Combinational Circuits Dr. D. J. Jackson Lecture 2-1 Introduction to VHDL Designer writes a logic circuit description in
More informationDigitaalsüsteemide disain
IAY 0600 Digitaalsüsteemide disain VHDL discussion Verification: Testbenches Design verification We want to verify that our design is correct before the target PLD is programmed. The process performed
More informationConcurrent Signal Assignment Statements (CSAs)
Concurrent Signal Assignment Statements (CSAs) Digital systems operate with concurrent signals Signals are assigned values at a specific point in time. VHDL uses signal assignment statements Specify value
More informationVHDL for FPGA Design. by : Mohamed Samy
VHDL for FPGA Design by : Mohamed Samy VHDL Vhdl is Case insensitive myvar = myvar = MYVAR IF = if = if Comments start with -- Comments can exist anywhere in the line Semi colon indicates the end of statements
More informationNanosistemų programavimo kalbos 4 paskaita. Nuosekliai vykdomi sakiniai
Nanosistemų programavimo kalbos 4 paskaita Nuosekliai vykdomi sakiniai Sequential Statements This slide set covers the sequential statements and the VHDL process (do NOT con- fuse with sequential circuits)
More informationMulti-valued Logic. Standard Logic IEEE 1164 Type std_ulogic is ( U, uninitialized
Multi-valued Logic Standard Logic IEEE 1164 Type std_ulogic is ( U, uninitialized X, unknown 0, logic 0 1, logic 1 Z, high impedance W, unknown L, logic 0 weak H, logic 1 weak - ); don t care Standard
More informationVHDL. Chapter 7. Behavioral Modeling. Outline. Behavioral Modeling. Process Statement
Chapter 7 VHDL VHDL - Flaxer Eli Ch 7-1 Process Statement Outline Signal Assignment Statement Variable Assignment Statement Wait Statement If-Then-Else Statement Case Statement Null Statement Loop Statement
More informationLecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language)
Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits Hardware Description Language) 1 Standard ICs PLD: Programmable Logic Device CPLD: Complex PLD FPGA: Field Programmable
More informationIntroduction to VHDL #3
ECE 322 Digital Design with VHDL Introduction to VHDL #3 Lecture 7 & 8 VHDL Modeling Styles VHDL Modeling Styles Dataflow Concurrent statements Structural Components and interconnects Behavioral (sequential)
More informationBasic Language Concepts
Basic Language Concepts Sudhakar Yalamanchili, Georgia Institute of Technology ECE 4170 (1) Describing Design Entities a sum b carry Primary programming abstraction is a design entity Register, logic block,
More informationECOM 4311 Digital System Design using VHDL. Chapter 7
ECOM 4311 Digital System Design using VHDL Chapter 7 Introduction A design s functionality should be verified before its description is synthesized. A testbench is a program used to verify a design s functionality
More informationHardware Description Language VHDL (1) Introduction
Hardware Description Language VHDL (1) Introduction Digital Radiation Measurement and Spectroscopy NE/RHP 537 Introduction Hardware description language (HDL) Intended to describe circuits textually, for
More informationCCE 3202 Advanced Digital System Design
CCE 3202 Advanced Digital System Design Lab Exercise #2 Introduction You will use Xilinx Webpack v9.1 to allow the synthesis and creation of VHDLbased designs. This lab will outline the steps necessary
More informationChapter 6 Combinational-Circuit Building Blocks
Chapter 6 Combinational-Circuit Building Blocks Commonly used combinational building blocks in design of large circuits: Multiplexers Decoders Encoders Comparators Arithmetic circuits Multiplexers A multiplexer
More informationExperiment 8 Introduction to VHDL
Experiment 8 Introduction to VHDL Objectives: Upon completion of this laboratory exercise, you should be able to: Enter a simple combinational logic circuit in VHDL using the Quartus II Text Editor. Assign
More informationSequential Statements
Sequential Statements Chapter 5 1 Outline 1. VHDL process 2. Sequential signal assignment statement 3. Variable assignment statement 4. If statement 5. Case statement 6. Simple for loop statement Chapter
More informationUNIT I Introduction to VHDL VHDL: - V -VHSIC, H - Hardware, D - Description, L Language Fundamental section of a basic VHDL code Library :
UNIT I Introduction to VHDL VHDL stands for very high-speed integrated circuit hardware description language. Which is one of the programming languages used to model a digital system by dataflow, behavioral
More informationChapter 2 Basic Logic Circuits and VHDL Description
Chapter 2 Basic Logic Circuits and VHDL Description We cannot solve our problems with the same thinking we used when we created them. ----- Albert Einstein Like a C or C++ programmer don t apply the logic.
More informationHardware Description Languages. Modeling Complex Systems
Hardware Description Languages Modeling Complex Systems 1 Outline (Raising the Abstraction Level) The Process Statement if-then, if-then-else, if-then-elsif, case, while, for Sensitivity list Signals vs.
More informationWhat Is VHDL? VHSIC (Very High Speed Integrated Circuit) Hardware Description Language IEEE 1076 standard (1987, 1993)
What Is VHDL? VHSIC (Very High Speed Integrated Circuit) Hardware Description Language IEEE 1076 standard (1987, 1993) Only possible to synthesize logic from a subset of VHDL Subset varies according to
More informationAdvanced Training Course on FPGA Design and VHDL for Hardware Simulation and Synthesis. 26 October - 20 November, 2009
2065-15 Advanced Training Course on FPGA Design and VHDL for Hardware Simulation and Synthesis 26 October - 20 November, 2009 FPGA Architectures & VHDL Introduction to Synthesis Nizar Abdallah ACTEL Corp.2061
More informationEECE-4740/5740 Advanced VHDL and FPGA Design. Lecture 3 Concurrent and sequential statements
EECE-4740/5740 Advanced VHDL and FPGA Design Lecture 3 Concurrent and sequential statements Cristinel Ababei Marquette University Department of Electrical and Computer Engineering Overview Components hierarchy
More informationAbi Farsoni, Department of Nuclear Engineering and Radiation Health Physics, Oregon State University
Hardware description language (HDL) Intended to describe circuits textually, for a computer to read Evolved starting in the 1970s and 1980s Popular languages today include: VHDL Defined in 1980s by U.S.
More information310/ ICTP-INFN Advanced Tranining Course on FPGA and VHDL for Hardware Simulation and Synthesis 27 November - 22 December 2006
310/1780-10 ICTP-INFN Advanced Tranining Course on FPGA and VHDL for Hardware Simulation and Synthesis 27 November - 22 December 2006 VHDL & FPGA - Session 2 Nizar ABDALLH ACTEL Corp. 2061 Stierlin Court
More informationSequential VHDL. Katarzyna Radecka. DSD COEN 313
Sequential VHDL Katarzyna Radecka DSD COEN 313 kasiar@ece.concordia.ca Overview Process Sensitivity List Wait Statements If Statements Case Statements Loop Statements Three Styles of VHDL Behavioral Structural
More informationDesign units can NOT be split across different files
Skeleton of a Basic VHDL Program This slide set covers the components to a basic VHDL program, including lexical elements, program format, data types and operators A VHDL program consists of a collection
More informationCSCI Lab 3. VHDL Syntax. Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\
CSCI 250 - Lab 3 VHDL Syntax Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\ Objectives 1. Learn VHDL Valid Names 2. Learn the presentation of Assignment and Comments 3. Learn Modes, Types, Array,
More informationIntroduction to VHDL. Main language concepts
Introduction to VHDL VHSIC (Very High Speed Integrated Circuit) Hardware Description Language Current standard is IEEE 1076-1993 (VHDL-93). Some tools still only support VHDL-87. Tools used in the lab
More informationOutline. CPE/EE 422/522 Advanced Logic Design L05. Review: General Model of Moore Sequential Machine. Review: Mealy Sequential Networks.
Outline CPE/EE 422/522 Advanced Logic Design L05 Electrical and Computer Engineering University of Alabama in Huntsville What we know Combinational Networks Sequential Networks: Basic Building Blocks,
More informationPart 4: VHDL for sequential circuits. Introduction to Modeling and Verification of Digital Systems. Memory elements. Sequential circuits
M1 Informatique / MOSIG Introduction to Modeling and erification of Digital Systems Part 4: HDL for sequential circuits Laurence PIERRE http://users-tima.imag.fr/amfors/lpierre/m1arc 2017/2018 81 Sequential
More informationLecture 1: VHDL Quick Start. Digital Systems Design. Fall 10, Dec 17 Lecture 1 1
Lecture 1: VHDL Quick Start Digital Systems Design Fall 10, Dec 17 Lecture 1 1 Objective Quick introduction to VHDL basic language concepts basic design methodology Use The Student s Guide to VHDL or The
More informationENGIN 241 Digital Systems with Lab
ENGIN 241 Digital Systems with Lab (4) Dr. Honggang Zhang Engineering Department University of Massachusetts Boston 1 Introduction Hardware description language (HDL): Specifies logic function only Computer-aided
More informationRTL Implementation. Introduction to Structured VLSI Design. Concurrent Statements and Processes. Combinational and Sequential Logic.
RTL Implementation 32 Introduction to Structured VLSI Design Recap on Processes, Signals, and Variables A Y Y=A*B+C B C 48 Joachim Rodrigues We have complete control (active chioice) over the registers:
More informationComputer-Aided Digital System Design VHDL
بس م اهلل الر حم ن الر حی م Iran University of Science and Technology Department of Computer Engineering Computer-Aided Digital System Design VHDL Ramin Rajaei ramin_rajaei@ee.sharif.edu Modeling Styles
More informationReview. LIBRARY list of library names; USE library.package.object; ENTITY entity_name IS generic declarations PORT ( signal_name(s): mode signal_type;
LIBRARY list of library names; USE library.package.object; Review ENTITY entity_name IS generic declarations PORT ( signal_name(s): mode signal_type; signal_name(s) : mode signal_type); END ENTITY entity_name;
More informationECE U530 Digital Hardware Synthesis. Course Accounts and Tools
ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser mel@coe.neu.edu Sept 13, 2006 Lecture 3: Basic VHDL constructs Signals, Variables, Constants VHDL Simulator and Test benches Types Reading: Ashenden
More informationECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic
ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 3, RT-level
More informationThe process. Sensitivity lists
The process process itself is a concurrent statement but the code inside the process is executed sequentially Process label (optional) Process declarative region Process body entity Test is, : in bit;
More informationECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic
ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 3, RT-level
More informationVHDL Examples Mohamed Zaky
VHDL Examples By Mohamed Zaky (mz_rasmy@yahoo.co.uk) 1 Half Adder The Half Adder simply adds 2 input bits, to produce a sum & carry output. Here we want to add A + B to produce Sum (S) and carry (C). A
More informationInthis lecture we will cover the following material:
Lecture #8 Inthis lecture we will cover the following material: The standard package, The std_logic_1164 Concordia Objects & data Types (Signals, Variables, Constants, Literals, Character) Types and Subtypes
More information5. VHDL - Introduction - 5. VHDL - Design flow - 5. VHDL - Entities and Architectures (1) - 5. VHDL - Entities and Architectures (2) -
Sistemas Digitais I LESI - 2º ano Lesson 5 - VHDL Prof. João Miguel Fernandes (miguel@di.uminho.pt) Dept. Informática - Introduction - VHDL was developed, in the mid-1980s, by DoD and IEEE. VHDL stands
More informationEmbedded Systems CS - ES
Embedded Systems - 1 - REVIEW Hardware/System description languages VDHL VHDL-AMS SystemC TLM - 2 - VHDL REVIEW Main goal was modeling of digital circuits Modelling at various levels of abstraction Technology-independent
More informationVHDL 2 Combinational Logic Circuits. Reference: Roth/John Text: Chapter 2
VHDL 2 Combinational Logic Circuits Reference: Roth/John Text: Chapter 2 Combinational logic -- Behavior can be specified as concurrent signal assignments -- These model concurrent operation of hardware
More informationArithmetic Circuits. Nurul Hazlina Adder 2. Multiplier 3. Arithmetic Logic Unit (ALU) 4. HDL for Arithmetic Circuit
Nurul Hazlina 1 1. Adder 2. Multiplier 3. Arithmetic Logic Unit (ALU) 4. HDL for Arithmetic Circuit Nurul Hazlina 2 Introduction 1. Digital circuits are frequently used for arithmetic operations 2. Fundamental
More informationBasic Language Constructs of VHDL
Basic Language Constructs of VHDL Chapter 3 1 Outline 1. Basic VHDL program 2. Lexical elements and program format 3. Objects 4. Data type and operators Chapter 3 2 1. Basic VHDL program Chapter 3 3 Design
More informationLecture 12 VHDL Synthesis
CPE 487: Digital System Design Spring 2018 Lecture 12 VHDL Synthesis Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 What is Synthesis?
More informationCOE 405 Design Methodology Based on VHDL
COE 405 Design Methodology Based on VHDL Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Outline Elements of VHDL Top-Down Design Top-Down Design with
More informationHardware Modeling. VHDL Basics. ECS Group, TU Wien
Hardware Modeling VHDL Basics ECS Group, TU Wien VHDL Basics 2 Parts of a Design Unit Entity Architecture Configuration Package Package Package Body Library How to create a Design Unit? Interface to environment
More informationLecture 4. VHDL Fundamentals. George Mason University
Lecture 4 VHDL Fundamentals George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 3, Basic Language Constructs of VHDL 2 Design Entity ECE 448 FPGA and ASIC Design with
More informationHardware Synthesis. References
Hardware Synthesis MidiaReshadi CE Department Science and research branch of Islamic Azad University Email: ce.srbiau@gmail.com 1 References 2 1 Chapter 1 Digital Design Using VHDL and PLDs 3 Some Definitions
More informationLecture 3 Introduction to VHDL
CPE 487: Digital System Design Spring 2018 Lecture 3 Introduction to VHDL Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 Managing Design
More informationEE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 4 Introduction to VHDL
EE 459/500 HDL Based Digital Design with Programmable Logic Lecture 4 Introduction to VHDL Read before class: Chapter 2 from textbook (first part) Outline VHDL Overview VHDL Characteristics and Concepts
More informationControl and Datapath 8
Control and Datapath 8 Engineering attempts to develop design methods that break a problem up into separate steps to simplify the design and increase the likelihood of a correct solution. Digital system
More informationIE1204 Digital Design L7: Combinational circuits, Introduction to VHDL
IE24 Digital Design L7: Combinational circuits, Introduction to VHDL Elena Dubrova KTH / ICT / ES dubrova@kth.se This lecture BV 38-339, 6-65, 28-29,34-365 IE24 Digital Design, HT 24 2 The multiplexer
More informationVHDL. ELEC 418 Advanced Digital Systems Dr. Ron Hayne. Images Courtesy of Cengage Learning
VHDL ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Cengage Learning Design Flow 418_02 2 VHDL Modules 418_02 3 VHDL Libraries library IEEE; use IEEE.std_logic_1164.all; std_logic Single-bit
More informationEE261: Intro to Digital Design
2014 EE261: Intro to Digital Design Project 3: Four Bit Full Adder Abstract: This report serves to teach us, the students, about modeling logic and gives a chance to apply concepts from the course to a
More informationDigital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification Part II
Digital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification Part II Ahmed Abu-Hajar, Ph.D. abuhajar@digitavid.net Digitavid, Inc San Jose, CA VHDL Lexical Description Code
More informationEEL 4783: Hardware/Software Co-design with FPGAs
EEL 4783: Hardware/Software Co-design with FPGAs Lecture 9: Short Introduction to VHDL* Prof. Mingjie Lin * Beased on notes of Turfts lecture 1 What does HDL stand for? HDL is short for Hardware Description
More informationMridula Allani Fall Fall
Mridula Allani Fall 2010 Fall 2010 1 Model and document digital systems Hierarchical models System, RTL (Register Transfer Level), gates Different levels of abstraction Behavior, structure Verify circuit/system
More informationA bird s eye view on VHDL!
Advanced Topics on Heterogeneous System Architectures A bird s eye view on VHDL Politecnico di Milano Conference Room, Bld 20 19 November, 2015 Antonio R. Miele Marco D. Santambrogio Politecnico di Milano
More informationModeling Complex Behavior
Modeling Complex Behavior Sudhakar Yalamanchili, Georgia Institute of Technology, 2006 (1) Outline Abstraction and the Process Statement Concurrent processes and CSAs Process event behavior and signals
More informationECE 3401 Lecture 10. More on VHDL
ECE 3401 Lecture 10 More on VHDL Outline More on VHDL Some VHDL Basics Data Types Operators Delay Models VHDL for Simulation VHDL for Synthesis 1 Data Types Every signal has a type, type specifies possible
More informationLattice VHDL Training
Lattice Part I February 2000 1 VHDL Basic Modeling Structure February 2000 2 VHDL Design Description VHDL language describes a digital system as a set of modular blocks. Each modular block is described
More informationACS College of Engineering. Department of Biomedical Engineering. Logic Design Lab pre lab questions ( ) Cycle-1
ACS College of Engineering Department of Biomedical Engineering Logic Design Lab pre lab questions (2015-2016) Cycle-1 1. What is a combinational circuit? 2. What are the various methods of simplifying
More informationVHDL: A Crash Course
VHDL: A Crash Course Dr. Manuel Jiménez With contributions by: Irvin Ortiz Flores Electrical and Computer Engineering Department University of Puerto Rico - Mayaguez Outline Background Program Structure
More informationIntroduction to VHDL
Introduction to VHDL Agenda Introduce VHDL Basic VHDL constructs Implementing circuit functions Logic, Muxes Clocked Circuits Counters, Shifters State Machines FPGA design and implementation issues FPGA
More informationContents. Appendix D VHDL Summary Page 1 of 23
Appendix D VHDL Summary Page 1 of 23 Contents Appendix D VHDL Summary...2 D.1 Basic Language Elements...2 D.1.1 Comments...2 D.1.2 Identifiers...2 D.1.3 Data Objects...2 D.1.4 Data Types...2 D.1.5 Data
More informationTwo HDLs used today VHDL. Why VHDL? Introduction to Structured VLSI Design
Two HDLs used today Introduction to Structured VLSI Design VHDL I VHDL and Verilog Syntax and ``appearance'' of the two languages are very different Capabilities and scopes are quite similar Both are industrial
More informationVHDL Part 2. What is on the agenda? Basic VHDL Constructs. Examples. Data types Objects Packages and libraries Attributes Predefined operators
VHDL Part 2 Some of the slides are taken from http://www.ece.uah.edu/~milenka/cpe428-02s/ What is on the agenda? Basic VHDL Constructs Data types Objects Packages and libraries Attributes Predefined operators
More informationLecture 5: State Machines, Arrays, Loops. EE 3610 Digital Systems
EE 3610: Digital Systems 1 Lecture 5: State Machines, Arrays, Loops BCD to Excess-3 (XS 3 ) Code Converter Example: Fig. 2-53 2 Easier to use one type of code (e.g. XS 3 ) over the other type (e.g. BCD)
More informationOverview. Ram vs Register. Register File. Introduction to Structured VLSI Design. Recap Operator Sharing FSMD Counters.
Overview Introduction to Structured VLSI Design VHDL V Recap Operator Sharing FSMD Counters Joachim Rodrigues Ram vs Register Register File RAM characteristics RAM cell designed at transistor level Cell
More informationLecture 4. VHDL Fundamentals. Required reading. Example: NAND Gate. Design Entity. Example VHDL Code. Design Entity
Required reading Lecture 4 VHDL Fundamentals P. Chu, RTL Hardware Design using VHDL Chapter 3, Basic Language Constructs of VHDL George Mason University 2 Example: NAND Gate Design Entity a b z a b z 0
More information1. Defining and capturing the design of a system. 2. Cost Limitations (low profit margin must sell millions)
What is an Embedded System? A type of computer system ECEN 4856: Embedded System Design Lecture 2: Embedded System Standards Traditional Definitions Limited in hardware and software vs the PC Designed
More information1 ST SUMMER SCHOOL: VHDL BOOTCAMP PISA, JULY 2013
MARIE CURIE IAPP: FAST TRACKER FOR HADRON COLLIDER EXPERIMENTS 1 ST SUMMER SCHOOL: VHDL BOOTCAMP PISA, JULY 2013 Introduction to VHDL Calliope-Louisa Sotiropoulou PhD Candidate/Researcher Aristotle University
More informationECE 545 Lecture 8. Data Flow Description of Combinational-Circuit Building Blocks. George Mason University
ECE 545 Lecture 8 Data Flow Description of Combinational-Circuit Building Blocks George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 7, Combinational Circuit Design:
More informationVHDL simulation and synthesis
VHDL simulation and synthesis How we treat VHDL in this course You will not become an expert in VHDL after taking this course The goal is that you should learn how VHDL can be used for simulation and synthesis
More informationBASIC VHDL LANGUAGE ELEMENTS AND SEMANTICS. Lecture 7 & 8 Dr. Tayab Din Memon
BASIC VHDL LANGUAGE ELEMENTS AND SEMANTICS Lecture 7 & 8 Dr. Tayab Din Memon Outline Data Objects Data Types Operators Attributes VHDL Data Types VHDL Data Objects Signal Constant Variable File VHDL Data
More informationECE 545 Lecture 6. Behavioral Modeling of Sequential-Circuit Building Blocks. George Mason University
ECE 545 Lecture 6 Behavioral Modeling of Sequential-Circuit Building Blocks George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 5.1, VHDL Process Chapter 8, Sequential
More informationDOD, VHSIC ~1986, IEEE stnd 1987 Widely used (competition Verilog) Commercial VHDL Simulators, Synthesizers, Analyzers,etc Student texts with CDROMs
DOD, VHSIC ~1986, IEEE stnd 1987 Widely used (competition Verilog) Commercial VHDL Simulators, Synthesizers, Analyzers,etc Student texts with CDROMs Entity Architecture Blocks CAE Symbol CAE Schematic
More informationEITF35: Introduction to Structured VLSI Design
EITF35: Introduction to Structured VLSI Design Part 1.2.2: VHDL-1 Liang Liu liang.liu@eit.lth.se 1 Outline VHDL Background Basic VHDL Component An example FSM Design with VHDL Simulation & TestBench 2
More informationECE 448 Lecture 4. Sequential-Circuit Building Blocks. Mixing Description Styles
ECE 448 Lecture 4 Sequential-Circuit Building Blocks Mixing Description Styles George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 4, Regular Sequential Circuit Recommended
More informationVHDL. VHDL History. Why VHDL? Introduction to Structured VLSI Design. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language
VHDL Introduction to Structured VLSI Design VHDL I Very High Speed Integrated Circuit (VHSIC) Hardware Description Language Joachim Rodrigues A Technology Independent, Standard Hardware description Language
More informationDIGITAL SYSTEM DESIGN & DIGITAL IC APPLICATIONS UNIT-I DIGITAL DESIGN USING HDL
DIGITAL SYSTEM DESIGN & DIGITAL IC APPLICATIONS UNIT-I DIGITAL DESIGN USING HDL 1) What are the Basic steps involved in the Designing of Digital System? Ans) Basic steps involved in the Designing of Digital
More informationECE 545 Lecture 4. Simple Testbenches. George Mason University
ECE 545 Lecture 4 Simple Testbenches George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 2.2.4, Testbenches 2 Testbenches ECE 448 FPGA and ASIC Design with VHDL 3 Testbench
More informationThe block diagram representation is given below: The output equation of a 2x1 multiplexer is given below:
Experiment-3: Write VHDL programs for the following circuits, check the wave forms and the hardware generated a. multiplexer b. De-Multiplexer Objective: i. To learn the VHDL coding for Multiplexer and
More informationFPGA BASED SYSTEM DESIGN. Dr. Tayab Din Memon Lecture 9 & 10 : Combinational and Sequential Logic
FPGA BASED SYSTEM DESIGN Dr. Tayab Din Memon tayabuddin.memon@faculty.muet.edu.pk Lecture 9 & 10 : Combinational and Sequential Logic Combinational vs Sequential Logic Combinational logic output depends
More informationSRI SUKHMANI INSTITUTE OF ENGINEERING AND TECHNOLOGY, DERA BASSI (MOHALI)
SRI SUKHMANI INSTITUTE OF ENGINEERING AND TECHNOLOGY, DERA BASSI (MOHALI) VLSI LAB MANUAL ECE DEPARTMENT Introduction to VHDL It is a hardware description language that can be used to model a digital system
More informationCprE 583 Reconfigurable Computing
Recap Moore FSM Example CprE / ComS 583 Reconfigurable Computing Moore FSM that recognizes sequence 10 0 1 0 1 S0 / 0 S1 / 0 1 S2 / 1 Prof. Joseph Zambreno Department of Electrical and Computer Engineering
More informationSynthesis from VHDL. Krzysztof Kuchcinski Department of Computer Science Lund Institute of Technology Sweden
Synthesis from VHDL Krzysztof Kuchcinski Krzysztof.Kuchcinski@cs.lth.se Department of Computer Science Lund Institute of Technology Sweden March 23, 2006 Kris Kuchcinski (LTH) Synthesis from VHDL March
More informationField Programmable Gate Array
Field Programmable Gate Array System Arch 27 (Fire Tom Wada) What is FPGA? System Arch 27 (Fire Tom Wada) 2 FPGA Programmable (= reconfigurable) Digital System Component Basic components Combinational
More informationstructure syntax different levels of abstraction
This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital
More informationHere is a list of lecture objectives. They are provided for you to reflect on what you are supposed to learn, rather than an introduction to this
This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital
More informationEE 595. Part II Design Units in VHDL. EE 595 EDA / ASIC Design Lab
EE 595 Part II Design Units in VHDL Design Units There are five type of design units in VHDL: Entities Architectures Packages Package Bodies Configurations Entities and architectures are the only two design
More informationLab 1 Modular Design and Testbench Simulation ENGIN 341 Advanced Digital Design University of Massachusetts Boston
Lab 1 Modular Design and Testbench Simulation ENGIN 341 Advanced Digital Design University of Massachusetts Boston Introduction This lab introduces the concept of modular design by guiding you through
More informationVHDL: skaitmeninių įtaisų projektavimo kalba. 2 paskaita Pradmenys
VHDL: skaitmeninių įtaisų projektavimo kalba 2 paskaita Pradmenys Skeleton of a Basic VHDL Program This slide set covers the components to a basic VHDL program, including lexical elements, program format,
More information