VHDL Packages for Synthesis Base Types Standard bit types may be used Typically IEEE 1164 Std. types are used. CPE 528: Session #9

Transcription

1 CPE 528: Session #9 Department of Electrical and Computer Engineering University of Alabama in Huntsville VHDL Packages for Synthesis Base Types Standard bit types may be used Typically IEEE 1164 Std. types are used std_ulogic type USE USE IEEE.std_logic_1164.ALL; Values U, X, W, and - are called metalogical values for synthesis TYPE std_ulogic IS IS ( 'U', -- Uninitialized 'X', -- --Forcing Unknown '0', -- --Forcing 0 '1', -- --Forcing 1 'Z', -- --High Impedance 'W', -- --Weak Unknown 'L', -- --Weak 0 'H', -- --Weak 1 '-' '-' -- --Don't care ); ); std_logic type - resolved std_ulogic type Outline Review: VHDL Packages for Synthesis Review: VHDL for Combinational Logic Synthesis VHDL for Sequential Logic Synthesis VHDL for RTL Level Synthesis Structural VHDL Implementation Technology Considerations Summary VHDL Packages for Synthesis Base Types (cont.) The std_logic_1164 package also contains: Vectors of std_ulogic and std_logic Subtypes of std_logic - X01, X01Z, UX01, UX10Z Logic functions with various arguments - std_ulogic, std_logic, std_logic_vector FUNCTION and (l,r : std_ulogic;) RETURN UX01; FUNCTION nand (l,r : std_ulogic;) RETURN UX01; FUNCTION or (l,r : std_ulogic;) RETURN UX01; FUNCTION nor (l,r : std_ulogic;) RETURN UX01; FUNCTION xor (l,r : std_ulogic;) RETURN UX01; FUNCTION xnor (l,r : std_ulogic;) return ux01; FUNCTION "not" (l,r : std_ulogic) RETURN UX01; Conversion functions FUNCTION To_bit(s:std_ulogic) RETURN bit; FUNCTION To_bitvector(s:std_ulogic_vector) RETURN bit_vector; FUNCTION To_StdULogic(b:bit) RETURN std_ulogic; 1

2 VHDL Packages for Synthesis Base Types (cont.) Clock edge functions FUNCTION rising_edge (SIGNAL s:std_ulogic) RETURN boolean; FUNCTION falling_edge (SIGNAL s:std_ulogic) RETURN boolean; Unknown functions FUNCTION Is_X (s:std_ulogic_vector) RETURN boolean; FUNCTION Is_X (s:std_logic_vector) RETURN boolean; FUNCTION Is_X (s:std_ulogic) RETURN boolean; IEEE Std Packages Numeric_Bit Type declarations for signed and unsigned numbers USE USE IEEE.numeric_bit.ALL; TYPE unsigned IS IS ARRAY (natural RANGE <> <> ) OF OF bit; TYPE signed IS IS ARRAY (natural RANGE <> <> ) OF OF bit; Arithmetic operators - various combinations of signed and unsigned arguments FUNCTION abs (arg:unsigned) RETURN unsigned; FUNCTION - - (arg:unsigned) RETURN unsigned; FUNCTION + + (l,r:unsigned) RETURN unsigned; FUNCTION - - (l,r:unsigned) RETURN unsigned; FUNCTION * * (l,r:unsigned) RETURN unsigned; FUNCTION / / (l,r:unsigned) RETURN unsigned; FUNCTION rem (l,r:unsigned) RETURN unsigned; FUNCTION mod (l,r:unsigned) RETURN unsigned; 04/02/2003 UAH-CPE528 7 VHDL Packages for Synthesis Arithmetic Packages All synthesis tools support some type of arithmetic packages Synopsis developed packages based on std_logic_1164 package - supported by many other synthesis tools std_logic_arith std_logic_signed std_logic_unsigned Actel synthesis tools support their own package asyl.arith IEEE has developed standard packages for synthesis IEEE Std Numeric_Bit Numeric_Std IEEE Std Packages Numeric_Bit Comparison operators - various combinations of signed and unsigned arguments FUNCTION > > (l,r:unsigned) RETURN boolean; FUNCTION < < (l,r:unsigned) RETURN boolean; FUNCTION <= (l,r:unsigned) RETURN boolean; FUNCTION >= (l,r:unsigned) RETURN boolean; FUNCTION = = (l,r:unsigned) RETURN boolean; FUNCTION /= (l,r:unsigned) RETURN boolean; Shift and rotate functions FUNCTION shift_left (arg:unsigned; count:natural) RETURN unsigned; FUNCTION shift_right (arg:unsigned; count:natural) RETURN unsigned; FUNCTION rotate_left (arg:unsigned; count:natural) RETURN unsigned; FUNCTION rotate_right (arg:unsigned; count:natural) RETURN unsigned; FUNCTION sll sll (arg:unsigned; count:natural) RETURN unsigned; FUNCTION slr slr (arg:unsigned; count:natural) RETURN unsigned; FUNCTION rol rol (arg:unsigned; count:natural) RETURN unsigned; FUNCTION ror ror (arg:unsigned; count:natural) RETURN unsigned; 04/02/2003 UAH-CPE /02/2003 UAH-CPE

3 IEEE Std Packages Numeric_Bit Resize functions FUNCTION resize (arg:unsigned;new_size:natural) RETURN unsigned; FUNCTION resize (arg:signed;new_size:natural) RETURN signed; Conversion functions FUNCTION to_integer (arg:unsigned) RETURN natural; FUNCTION to_unsigned (arg,size:natural) RETURN unsigned; Logical operators FUNCTION not (l:unsigned) RETURN unsigned; FUNCTION and (l,r:unsigned) RETURN unsigned; FUNCTION or (l,r:unsigned) RETURN unsigned; FUNCTION nand (l,r:unsigned) RETURN unsigned; FUNCTION nor (l,r:unsigned) RETURN unsigned; FUNCTION xnor (l,r:unsigned) RETURN unsigned; Edge detection functions FUNCTION rising_edge(signal s:bit) RETURN boolean; FUNCTION falling_edge(signal s:bit) RETURN boolean; 04/02/2003 UAH-CPE528 9 Outline VHDL Packages for Synthesis VHDL for Combinational Logic Synthesis Types Attributes Concurrent signal assignment statements Operators Processes If statements Case statements Loops Procedures and functions Tri state logic Use of don t cares After clauses Inferring latches Problems to avoid VHDL for Sequential Logic Synthesis VHDL for RTL Level Synthesis IEEE Std Packages Numeric_Std Similar to Numeric_Bit package using std_logic_1164 types Signed and unsigned type declarations Aritmetic operators Comparison operators Shift and rotate functions Resize functions Conversion functions Logical operators Match functions FUNCTION std_match (l,r:std_ulogic) RETURN boolean; FUNCTION std_match (l,r:unsigned) RETURN boolean; Translation functions USE USE IEEE.numeric_std.ALL; FUNCTION to_01 (s:unsigned; xmap:std_logic := := 0 ) RETURN unsigned; 04/02/2003 UAH-CPE Types Scalar types Enumeration types are supported Bit, Boolean, and Std_Ulogic map to single bits Mapping of other types will be made by the tool unless the ENUM_ENCODING attribute is used Character type is suppored Severity_level type is ignored Integer type, Natural, and Positive are supported A subtype with a descrete range should be used or the default 32 bit length will be synthesized Physical types (e.g., time) are ignored Floating point type is ignored - references to floating point objects can occur only within ignored constructs, e.g., After clauses, etc. 04/02/2003 UAH-CPE

4 Types (cont.) Array types are supported Bounds must be specified directly or indirectly as static values of an integer type Element subtype must denote a scalar type or a one dimensional vector of an enumerated type that denotes single bits TYPE TYPE integer_array IS IS ARRAY(natural RANGE RANGE 7 DOWNTO 0) 0) OF OF integer; TYPE TYPE boolean_array IS IS ARRAY(integer RANGE RANGE <>) <>) OF OF boolean; SIGNAL bool_sig : boolean_array(-1 to to 1); 1); Record types are supported Access types are ignored File types are ignored File objects and file operations are not supported Concurrent Signal Assignment Statements Simple concurrent signal assignment statements are supported ENTITY csa csais is END END csa; csa; ARCHITECTURE behavior OF OF csais y <= <= a NOR NOR b; b; ENTITY aoi_csa is is END END aoi_csa; ARCHITECTURE behavior OF OF aoi_csais SIGNAL sig1,sig2 : std_logic; sig1 sig1 <= <= a AND AND b; b; sig2 sig2 <= <= c OR OR sig1; sig1; y <= <= NOT NOT sig2; sig2; 04/02/2003 UAH-CPE /02/2003 UAH-CPE Attributes The following predefined attributes for types are supported: t BASE t LEFT t RIGHT t HIGH t LOW The following predefined attributes for array objects are supported: a LEFT a RIGHT a HIGH a LOW a RANGE a REVERSE_RANGE a LENGTH The following predefined attributes for signals are supported s STABLE s EVENT User defined attributes other than ENUM_ENCODING are NOT supported Conditional Signal Assignment Statements Concurrent conditional signal assignment statements are supported - must end in else library clause IEEE; IEEE; ENTITY mux2 mux2 is is sel sel : IN IN std_logic; END END mux2; mux2; ARCHITECTURE behavior OF OF mux2 mux2 IS IS y <= <= a WHEN WHEN (sel (sel = '0') '0') ELSE ELSE b WHEN WHEN (sel (sel = '1') '1') ELSE ELSE 'X'; 'X'; 04/02/2003 UAH-CPE /02/2003 UAH-CPE

5 Selected Signal Assignment Statements Concurrent selected signal assignment statements are supported ENTITY mux4 mux4 is is d : IN IN std_logic; sel sel : IN IN std_logic_vector(1 DOWNTO 0); 0); END END mux4; mux4; ARCHITECTURE behavior OF OF mux4 mux4 IS IS WITH WITH sel selselect y <= <= a WHEN WHEN "00", "00", b WHEN WHEN "01", "01", c WHEN WHEN "10", "10", d WHEN WHEN "11", "11", 'X' 'X' WHEN WHEN OTHERS; 04/02/2003 UAH-CPE Operators (cont.) Comparison operators - >, <, <=, >=, =, /= use use IEEE.numeric_std.all; ENTITY compare is is PORT(a : IN IN unsigned(3 DOWNTO 0); 0); b : IN IN unsigned(3 DOWNTO 0); 0); aleb aleb : OUT OUT boolean); END END compare; ARCHITECTURE behavior OF OF compare IS IS aleb aleb <= <= (a (a <= <= b); b); 04/02/2003 UAH-CPE Operators Generally, if the numeric_bit and numeric_std packages are supported, the operators within them are supported Arithmetic operators - abs, +, -, *, /, rem, mod use use IEEE.numeric_std.all; ENTITY divider is is PORT(divisor : IN IN unsigned(1 DOWNTO 0); 0); dividend : IN IN unsigned(1 DOWNTO 0); 0); quotient : OUT OUT unsigned(1 DOWNTO 0)); 0)); END END divider; ARCHITECTURE behavior OF OF divider IS IS quotient <= <= dividend / divisor; Operators (cont.) Shift and conversion operators - shift_left, shift_right, rotate_left, rotate_right, resize, to_integer, library to_unsigned IEEE; library IEEE; use use IEEE.numeric_std.all; ENTITY shift_4 is is PORT(a : IN IN unsigned(3 DOWNTO 0); 0); b : IN IN unsigned(1 DOWNTO 0); 0); y : OUT OUT unsigned(3 DOWNTO 0)); 0)); END END shift_4; ARCHITECTURE behavior OF OF shift_4 IS IS y <= <= shift_left(a,to_integer(b)); 04/02/2003 UAH-CPE /02/2003 UAH-CPE

6 Process Statements Process statements are supported Postponed processes (or postponed concurrent signal assignment statements) are NOT supported Process statement can have either a sensitivity list or a WAIT statement Sensitivity list is ignored for synthesis (by most tools) - thus, to avoid simulation mismatches, all signals which appear on the RHS should be in the sensitivity list Only one WAIT statement per process is allowed and it must be the first statement in the process after BEGIN Only the WAIT UNTIL syntax of the WAIT statement is supported WAIT UNTIL input1 = 1 ; WAIT UNTIL clock EVENT and and clock = 1 ; 04/02/2003 UAH-CPE Process Statements Incomplete Sensitivity List ENTITY aoi_process is is END END aoi_process; ARCHITECTURE behavior OF OF aoi_process IS IS SIGNAL sig1 sig1 : std_logic; comb comb : PROCESS(a,b,c) c sig1 0 sig1 sig1 <= <= a AND AND b; y U b; y <= <= not(sig1 or or c); c); /02/2003 UAH-CPE a b Process Statements Example ENTITY aoi_process is is END END aoi_process; ARCHITECTURE behavior OF OF aoi_process IS IS SIGNAL sig1 sig1 : std_logic; comb comb : PROCESS(a,b,c,sig1) sig1 sig1 <= <= a AND AND b; b; y <= <= not(sig1 or or c); c); Sequential Signal Assignment Statements Various types of signal assignment statements inside a process statement (sequential signal assignment statements) are supported IF statements Case statements Loop statement Only For loops supported Bounds must be specified as static values of an integer type Exit and Next statements supported (without lables) 04/02/2003 UAH-CPE /02/2003 UAH-CPE

7 Sequential IF Statements IF statements are supported ENTITY xor_process is is END END xor_process; ARCHITECTURE behavior OF OF xor_process IS IS comb comb : PROCESS(a,b) IF((a IF((a = '1' '1' and and b = '0') '0') OR OR (a (a = '0' '0' and and b = '1')) '1')) THEN THEN y <= <= '1'; '1'; ELSE ELSE y <= <= '0'; '0'; 04/02/2003 UAH-CPE Sequential Loop Statements Only For loops with integer range are library supported IEEE; library IEEE; IEEE.std_logic_1164.all; ENTITY shift4 is ENTITY shift4 is PORT(mode : IN std_logic; PORT(mode IN std_logic; shift_in : IN std_logic; shift_in IN std_logic; a : IN std_logic_vector(4 DOWNTO 1); IN std_logic_vector(4 DOWNTO ARCHITECTURE 1); behavior OF shift4 IS DOWNTO ARCHITECTURE 1); behavior OF shift4 IS y : OUT std_logic_vector(4 DOWNTO SIGNAL 1); in_temp : std_logic_vector(5 OUT std_logic_vector(4 DOWNTO 0); shift_out : OUT std_logic); SIGNAL in_temp std_logic_vector(5 DOWNTO 0); shift_out OUT std_logic); SIGNAL out_temp : std_logic_vector(5 DOWNTO 1); END shift4; SIGNAL out_temp std_logic_vector(5 DOWNTO 1); END shift4; in_temp(0) <= shift_in; in_temp(0) <= shift_in; in_temp(4 DOWNTO 1) <= a; in_temp(4 DOWNTO 1) <= a; in_temp(5) <= '0'; in_temp(5) <= '0'; comb : PROCESS(mode,in_temp,a) comb PROCESS(mode,in_temp,a) FOR i IN 1 TO 5 LOOP FOR IN TO LOOP IF(mode = '0') THEN IF(mode '0') THEN out_temp(i) <= in_temp(i-1); out_temp(i) <= in_temp(i-1); ELSE ELSE out_temp(i) <= in_temp(i); out_temp(i) <= in_temp(i); END IF; END IF; END LOOP; END LOOP; END PROCESS comb; END PROCESS comb; y <= out_temp(4 DOWNTO 1); <= out_temp(4 DOWNTO 1); shift_out <= out_temp(5); shift_out <= out_temp(5); END behavior; END behavior; 04/02/2003 UAH-CPE Sequential Case Statements ENTITY mux4_process is is d : IN IN std_logic; sel sel : IN IN std_logic_vector(1 DOWNTO 0); 0); END END mux4_process; ARCHITECTURE behavior OF OF mux4_process IS IS Case statements are supported Choices which include metalogical values are never taken comb comb : PROCESS(a,b,c,d,sel) CASE CASE sel selis IS WHEN WHEN "00" "00" => => y <= <= a; a; WHEN WHEN "01" "01" => => y <= <= b; b; WHEN WHEN "10" "10" => => y <= <= c; c; WHEN WHEN "11" "11" => => y <= <= d; d; WHEN WHEN OTHERS => => y <= <= 'X'; 'X'; END END CASE; CASE; 04/02/2003 UAH-CPE Procedures and Functions Procedures and Functions are supported - with limitations to allowed statement types Procedures and functions may be in a package or in the declarative part of the architecture LIBRARY ieee; ieee; USE USE ieee.std_logic_1164.all; USE USE ieee.numeric_std.all; PACKAGE logic_package IS IS FUNCTION majority(in1, in2, in2, in3 in3 : std_logic) RETURN std_logic; PROCEDURE decode(signal input input : IN IN std_logic_vector(1 DOWNTO 0); 0); SIGNAL output : OUT OUT std_logic_vector(3 DOWNTO 0)); 0)); END END logic_package; 04/02/2003 UAH-CPE

8 Procedures and Functions (cont.) Using Procedures and Functions PACKAGE BODY BODY logic_package IS IS FUNCTION majority(in1, in2, in2, in3 in3 : std_logic) RETURN std_logic IS IS VARIABLE result : std_logic; IF((in1 = '1' '1' and and in2 in2 = '1') '1') or or (in2 (in2 = '1' '1' and and in3 in3 = '1') '1') or or (in1 (in1 = '1' '1' and and in3 in3 = '1')) '1')) THEN THEN result := :='1'; ELSIF((in1 = '0' '0' and and in2 in2 = '0') '0') or or (in2 (in2 = '0' '0' and and in3 in3 = '0') '0') or or (in1 (in1 = '0' '0' and and in3 in3 = '0')) '0')) THEN THEN result := :='0'; ELSE ELSE result := :='X'; RETURN result; END END majority; LIBRARY ieee; ieee; USE USE ieee.std_logic_1164.all; USE USE ieee.numeric_std.all; USE USE work.logic_package.all; ENTITY voter voter IS IS END END voter; ARCHITECTURE maj majof OF voter voter IS IS y <= <= majority(a,b,c); END END maj; maj; 04/02/2003 UAH-CPE /02/2003 UAH-CPE Procedures and Functions (cont.) Using Procedures and Functions (cont.) PROCEDURE decode(signal input input : IN IN std_logic_vector(1 DOWNTO 0); 0); SIGNAL output : OUT OUT std_logic_vector(3 DOWNTO 0)) 0)) IS IS CASE CASE input input IS IS WHEN WHEN "00" "00" => => output <= <= "0001"; WHEN WHEN "01" "01" => => output <= <= "0010"; WHEN WHEN "10" "10" => => output <= <= "0100"; WHEN WHEN "11" "11" => => output <= <= "1000"; WHEN WHEN OTHERS => => output <= <= "XXXX"; END END CASE; CASE; END END decode; END END logic_package; LIBRARY ieee; ieee; USE USE ieee.std_logic_1164.all; USE USE ieee.numeric_std.all; USE USE work.logic_package.all; ENTITY decoder IS IS PORT(y : IN IN std_logic_vector(1 DOWNTO 0); 0); g : OUT OUT std_logic_vector(3 DOWNTO 0)); 0)); END END decoder; ARCHITECTURE dec decof OF decoder IS IS comb comb : PROCESS(y) decode(y,g); END END dec; dec; 04/02/2003 UAH-CPE /02/2003 UAH-CPE

9 Tri-State Logic Tri-state logic is infered when an object is assigned an IEEE Std value Z ENTITY tri_state4 is is PORT(enable : IN IN std_logic; a : IN IN std_logic_vector(3 DOWNTO 0); 0); y : OUT OUT std_logic_vector(3 DOWNTO 0)); 0)); END END tri_state4; ARCHITECTURE behavior OF OF tri_state4 IS IS y <= <= a WHEN WHEN (enable = '1') '1') ELSE ELSE "ZZZZ"; 04/02/2003 UAH-CPE After Clauses Although not defined by the language, most simulator s waveform windows do not show VHDL delta cycles adequately, if at all Debugging large behavioral simulations before synthesis can be difficult if no delays are used - everything appears to happen simultaneously List windows typically show delta cycles, but can be difficult to interpret The solution is to put dummy delays in the behavioral descriptions using After clauses to spread out the events After clauses are ignored for synhtesis CONSTANT delay : TIME := := 5 ns; ns; output <= <= input + 1 AFTER delay; 04/02/2003 UAH-CPE Use of Don t Cares ( X s) IEEE Std values of X or - can be used to specify don t care conditions ENTITY not_xor is is END END not_xor; ARCHITECTURE behavior OF OF not_xor IS IS comb comb : PROCESS(a,b) IF((a IF((a = '1' '1' and and b = '0') '0') OR OR (a (a = '0' '0' and and b = '1')) '1')) THEN THEN y <= <= '1'; '1'; ELSE ELSE y <= <= 'X'; 'X';-- --could also also be be /02/2003 UAH-CPE Inferring Latches If signals or variables are not assigned values in some conditional expressions of IF or Case statements, level-sensitive sequential logic might result ARCHITECTURE behavior OF OF mux3_seq IS IS comb comb : PROCESS(a,b,c,sel) ENTITY mux3_seq is is CASE CASE sel selis IS WHEN WHEN "00" "00" => => y <= <= a; a; WHEN WHEN "01" "01" => => y <= <= b; b; WHEN WHEN "10" "10" => => y <= <= c; c; sel sel : IN IN std_logic_vector(1 DOWNTO 0); 0); WHEN WHEN OTHERS => => --empty END END CASE; CASE; END END mux3_seq; 04/02/2003 UAH-CPE

10 Avioding Latches ENTITY mux3 mux3 is is sel sel : IN IN std_logic_vector(1 DOWNTO 0); 0); END END mux3; mux3; ARCHITECTURE behavior OF OF mux3 mux3 IS IS comb comb : PROCESS(a,b,c,sel) CASE CASE sel selis IS WHEN WHEN "00" "00" => => y <= <= a; a; WHEN WHEN "01" "01" => => y <= <= b; b; WHEN WHEN "10" "10" => => y <= <= c; c; WHEN WHEN OTHERS => => y <= <= 'X'; 'X'; END END CASE; CASE; Assigning values of don t care ( X or - ) in these cases can avoid this 04/02/2003 UAH-CPE Problems to Avoid Synthesizing Asynchronous State Machines! ARCHITECTURE rtlof pc_comb2 IS IS SIGNAL pc pc : unsigned(3 DOWNTO 0); 0); use use IEEE.numeric_std.all; one one : PROCESS(data_in, cntrl, pc) pc) ENTITY pc_comb2 is is PORT(dat_in : IN IN unsigned(3 DOWNTO 0); 0); CASE CASE cntrl cntrlis IS cntrl cntrl : IN IN std_logic; WHEN data_out : OUT OUT unsigned(3 DOWNTO 0)); WHEN '1' '1' => => pc pc <= <= (pc (pc + "0001"); 0)); WHEN WHEN '0' '0' => => pc pc <= <= data_in; END END pc_comb2; WHEN WHEN OTHERS => => pc pc <= <= "XXXX"; END END CASE; CASE; END END PROCESS one; one; dat_out <= <= pc; pc; END END rtl; rtl; 04/02/2003 UAH-CPE Problems to Avoid Inferring Latches in Complex Behaviors ARCHITECTURE rtl rtlof OF pc_comb IS IS use use IEEE.std_logic_1164.ALL; SIGNAL pc pc : unsigned(3 DOWNTO 0); 0); use use IEEE.numeric_std.ALL; one one : PROCESS(dat_in, cntrl, pc) pc) ENTITY pc_comb IS IS PORT(data_in : IN IN unsigned(3 DOWNTO 0); 0); CASE CASE cntrl cntrlis IS cntrl cntrl : IN IN unsigned(1 DOWNTO 0); 0); WHEN WHEN "01" "01" => => pc pc <= <= (pc (pc + "0001"); data_out : OUT OUT unsigned(3 DOWNTO 0)); 0)); WHEN WHEN "10" "10" => => pc pc <= <= pc; pc; END END pc_comb; WHEN WHEN OTHERS => => pc pc <= <= data_in; END END CASE; CASE; END END PROCESS one; one; DATA_OUT <= <= PC; PC; END END rtl; rtl; Level Sensitive D Latch Use IF statement without Else clause ENTITY d_latch is is PORT(d : IN IN std_logic; clk clk : IN IN std_logic; q : INOUT INOUT std_logic; qn qn : OUT OUT std_logic); END END d_latch; ARCHITECTURE behavior OF OF d_latch IS IS seq seq : PROCESS(d,clk) IF(clk = '1') '1') THEN THEN q <= <= d; d; END END PROCESS seq; seq; qn qn <= <= not not q; q; 04/02/2003 UAH-CPE /02/2003 UAH-CPE

11 Master-Slave D Latch (D Flip-Flop) ENTITY ms_latch is is PORT(d : IN IN std_logic; clk clk : IN IN std_logic; q : INOUT INOUT std_logic; qn qn : OUT OUT std_logic); END END ms_latch; ARCHITECTURE behavior OF OF ms_latch IS IS SIGNAL q_int q_int : std_logic; seq1 seq1 : PROCESS(d,clk) Optimize IF(clk = '1') '1') THEN THEN q_int q_int <= <= d; d; END END PROCESS seq1; seq1; seq2 seq2 : PROCESS(q_int,clk) IF(clk = '0') '0') THEN THEN q <= <= q_int; END END PROCESS seq2; seq2; qn qn <= <= not not q; q; 04/02/2003 UAH-CPE Edge Sensitive D Flip-Flop (cont.) Wait statement can be used ARCHITECTURE behavior OF OF d_ff_w IS IS seq ENTITY d_ff_w is seq : PROCESS is PORT(d : IN IN std_logic; WAIT WAIT UNTIL UNTIL clk clk = 1 ; 1 ; clk clk : IN IN std_logic; q <= <= d; d; q : INOUT INOUT std_logic; END qn qn : OUT OUT std_logic); END PROCESS seq; seq; qn END END d_ff_w; qn <= <= not not q; q; ARCHITECTURE behavior OF OF d_ff_w IS IS seq seq : PROCESS WAIT WAIT UNTIL UNTIL rising_edge(clk); q <= <= d; d; END END PROCESS seq; seq; qn qn <= <= not not q; q; 04/02/2003 UAH-CPE Edge Sensitive D Flip-Flop Clocks must be of BIT or STD_LOGIC type - metalogic values not allowed Rising_edge() and Falling_edge() functions can be used to specify clock edge ENTITY d_ff d_ff is is PORT(d : IN IN std_logic; clk clk : IN IN std_logic; q : INOUT INOUT std_logic; qn qn : OUT OUT std_logic); END END d_ff; d_ff; ARCHITECTURE behavior OF OF d_ff d_ff IS IS seq seq : PROCESS(clk) IF(rising_edge(clk)) THEN THEN q <= <= d; d; END END PROCESS seq; seq; qn qn <= <= not not q; q; 04/02/2003 UAH-CPE Edge Sensitive Flip-Flops ENTITY d_ff_pc is is PORT(d : IN IN std_logic; clk clk : IN IN std_logic; pre pre : IN IN std_logic; clr clr : IN IN std_logic; q : INOUT INOUT std_logic; qn qn : OUT OUT std_logic); END END d_ff_pc; Preset and clear functions can be added Asynchronous with respect to the clock ARCHITECTURE behavior OF OF d_ff_pc IS IS seq seq : PROCESS(clk,pre,clr) IF(pre = '0') '0') THEN THEN q <= <= '1'; '1'; ELSIF(clr = '0') '0') THEN THEN q <= <= '0'; '0'; ELSIF(rising_edge(clk)) THEN THEN q <= <= d; d; END END PROCESS seq; seq; qn qn <= <= not not q; q; 04/02/2003 UAH-CPE

12 Edge Sensitive Flip-Flops ENTITY d_ff_spc is is PORT(d : IN IN std_logic; clk clk : IN IN std_logic; pre pre : IN IN std_logic; clr clr : IN IN std_logic; q : INOUT INOUT std_logic; qn qn : OUT OUT std_logic); END END d_ff_spc; Preset and clear functions can be added Synchronous with respect to the clock ARCHITECTURE behavior OF OF d_ff_spc IS IS seq seq : PROCESS(clk) IF(rising_edge(clk)) THEN THEN IF(pre = '0') '0') THEN THEN q <= <= '1'; '1'; ELSIF(clr = '0') '0') THEN THEN q <= <= '0'; '0'; ELSE ELSE q <= <= d; d; END END PROCESS seq; seq; qn qn <= <= not not q; q; 04/02/2003 UAH-CPE Mealy and Moore State Machine Models A state machine has three basic parts Next State Logic Output Logic Memory The most straight-forward way to code a synthesizable state machine is to use one process per function Primary Inputs Present State Mealy Machine Model Output Combinational Logic Next State Combinational Logic Memory Primary Outputs Next State Primary Inputs Present State Moore Machine Model Output Combinational Logic Next State Combinational Logic 04/02/2003 UAH-CPE Memory Primary Outputs Next State Finite State Machine Synthesis State machines can be modeled as a combinational portion and a sequential portion Both Mealy and Moore type state machines can be described Most synthesis tools employ special algorithms to minimize state machines - thus standard procedures must be used to enable the tool to recognize the state machine Huffman FSM Model Primary Inputs Combinational Logic Primary Outputs Present State Memory Next State 04/02/2003 UAH-CPE