Implementation of Double Precision Floating Point Adder with Residue for High Accuracy Using FPGA

Transcription

1 1008 Implementation of Double Precision Floating Point Adder with Residue for High Accuracy Using FPGA P.V.V.S. Narayana 1, N.V.N. Prasanna Kumar 2 1 (M.Tech Student, Department of ECE, Sri Vasavi Engineering College, Pedatadepalli 2 (Asst. Professor, Department of ECE, Sri Vasavi Engineering College, Pedatadepalli ABSTRACT A computation with real number in many scientific and engineering applications is compulsory. To characterize these numbers fixed point representation is in use. However, in several cases the range of this representation is not sufficient to get the correct values. Therefore to obtain the dynamic range as well as the correct answer for all applications floating point representation is used instead of fixed point representation. FP number representation system may be a common selection for scientific, engineering and numerical computations. This project is intended using modified single path floating point addition technique. A separate residue unit is designed in parallel with this floating point adder to know the error term which is nothing but residue. This project is implemented in seven pipelined stages and it address parallelism as well as accuracy by put together that computes a correctly rounded result for basic summation. The proposed design has taken less area than previous work In this paper, the field Programmable Gate Array based double precision floating point adder with residue feature is forced using VHDL and was, consecutively, verified on Xilinx9.2 ISE simulator. Keywords: Floating point adder (FPadder) with Residue, FPGA, Leading one detector, Left Shifter, Rounding. 1. INTRODUCTION Lot of research has been done to get the accurate answers from the past two decades in many numerical computations. This work is dedicated to get a maximum of accuracy which is developed on FPGA. Of course many numerical applications utilized double precision format. Several research works are already done in floating point operations. The highest precision is to be taken for better accuracy and precision, but even then in the double precision format also will show the error. So maintaining the accuracy is difficult in floating point arithmetic operations in previous adders. Many serial components like left shifter or right shifter and the floating point addition (FPA) have been taken a longer latency. The Floating point (FP) adder required to have to be speedy in order to match with the increasing clock rate demand. In general the conventional floating point adders perform the computation in a single clock cycle. For that cause clock rates would be lower and lower. Thus in order to perform a sequential summations or sequential computations the conventional adder is incompetent. So pipeling is the technique is necessary to overcome this limitation on clock frequency. Pipelining means the instructions are executed sequentially, finally, the last output will come one by one. The speed of the operation will achieve by increasing the pipelines. The Pipelining techniques are applied in FPA in order to speed up the numerical arithmetic operation and to increase the through put. Now- a -days everybody try to increase the clock speed this means that according to, Moore's Law feature size scaling is increasing exponentially in transistor per integrated chip. Increasing the pipeling and clock speed setting boundary to there is surely have a limit in the clock scaling, if it really happens definitely there may be a short channel effects occurs, this causes the transistor never goes to the OFF state, so it runs as an ON state. So the industry is now might be reaches that end point, the focus is now transfer to enhances with parallelism in computations more willingly than clock speed. Each IEEE-754 standard floating-point number system has a specific precision like single precision or double precision and quadruple precision which is comprises of sign bit, exponent and significant or fractional bits. But the bits will vary depending on the precision. In single precision one sign bit, 8-exponent bits, 23-significand bits with implied one. In case of double precision, one sign bit, 11-exponent bits, 53- significand bits including one hidden bit by the standard. Exponent must be greater than zero and less than 1023.In this paper, we focus on the problem of summing two double-precision FP values, but when we rearrange the order of numbers sum would produce a miscellaneous result. This is an alternative to be deprived of parallelism in order to increase the clock speed. The sequential summation operation [1] will always give the similar result, but it may still be an erroneous one in case of shuffled order. In this case parallelizations and accuracy may get failed. When we know the error we have a freedom to correct the answer. In this paper, we made an effort based on for FP addition using pipelining technique still guaranteeing an ideal result and of course acceptably rounded deterministic

2 1009 result. To speed up the computations for many scientific applications the design of the accurate floating point unit or FPA unit is thus of interest in this domain. In residue preserving addition most of the algorithms such as [5] [7] rely on the similar basic building block that is studied in detail by Kornerup et al. [8], a floating-point adder with residue (FPAR), which computes sum and residue (error term) Sum = IEEE-754 Round(x + y) --- (1) Residue = (x + y) sum (2) The sum of two FP numbers is the same as like normal standard floating point addition; here the extra term is introduced as error or residue. The FPAR building block can be implemented on a standard IEEE-754 Floating point unit. Kornerup shows that the algorithm introduced by Knuth is negligible. The similar work has been carried out in HDL implementation and analysis of a residual register [4] for parallelism, accuracy and consumes lesser area. 2. IEEE DOUBLE PRECISION FLOATING POINT ADDER WITHOUT RESIDUE The above floating point adder is divided into seven pipelined stages to improve the speed of operations. The below circuit diagram or figure 1 shows that the general organization which is nothing but improved single path floating point adder. Adding two floating point numbers like x and y in standard FP algorithm [9] for Floating Point Addition of is as follows. Fig.1.Floating Point Adder Stage1: Take two binary floating point numbers. The MSB bits of two numbers given to XOR gate as inputs. To decide the type of addition operation use the XOR output terminal is connected to adder in stage3.next exponent subtraction which is designed for difference of two numbers (D),sign bit either 0 or 1 as (Sn) and larger exponent (LE).Sn will connect to swap circuit multiplexers. So the Swap circuit gives the outputs as larger mantissa and smaller mantissa which is decided by Sn.At the same time some of special cases will connect from sign, exponent, mantissa bits. To special case unit. But some other special cases will come by direct computations without intervention of special case unit. Stage2: From the swap circuit larger mantissa will come in one side and smaller mantissa will come in other side. To get align the smaller significand and bigger significand, the exponent difference is connected to smaller significand via right shifter. In this right shifting process shifted bits will be considered as residue bits which are used for rounding. Stage3: After align the both significands, add the both mantissa bits using 53 bit ripple carry adder. But Ripple carry adder will give the large delay. So to get better trade off we may use other adders also. In this project we tried here 2 s complement adder to save the area and time. Stage4: During the addition operation sometimes will generate carry out. This carry will connect to 1-bit right shifter in stage 4.If the addition is 53 bits then the output of addition is connected to leading one detector. The leading one detector output is connected to multiplexer in stage5.at the same time rounding performed using the residue bits Stage5: While during the addition operation, if nonzero entry comes then normalization is needed particularly in subtraction. In the result of the mantissa must be shifted until it reaches the front with one using the Leading one priority detector (LOPD) & left shifter. So it can easily achieved, but error may be occurs. After completing the one bit right shift this result will be added with rounding value in add rounding & 1- bit shift unit and given this output is as one of the input to multiplexer. Other input is connected from left shifter output and the LOPD output is connected to multiplexer as selection line. Stage6: The multiplexer output which is sometimes has normal, or subnormal s or special case numbers which are connected via multiplexer by choosing as the one of the input. The normal sum will be connected to other input terminal in same multiplexer (MUX). Stage7: Some of the special cases, output as SET will connect to final multiplexer of selection line and Concatenate the final result includes sign of bigger number, normalized exponent and mantissa. Which is connected to another multiplexer as other input. Other input is from special cases which are obtained directly during the normal operations. So final result may obtain depending on the selection line.

3 PROPOSED IEEE DOUBLE PRECISION SINGLE PATH FLOATING POINT ADDER WITH RESIDUE The block diagram for performing the floating point accumulation with residue for improving accuracy and parallelism is as shown below: doing the addition operation getting a carry as 54 th bit. If 54th bit comes then this 54 th bit is to be connected to one bit right shifter to set the next bit as leading one position. Using the residue bits, calculate the round value and this round value will be added to the 1-bit right shifted number, so we get an accurate answer. If rounding is performed without 1-bit right shift, there may be getting an error. Step5: First determine the LSB bit (L) which is nothing but ready to discarded bit from adder, determine Guard (G), Round (R) and Sticky bits from residue unit. Sticky bit (T) is attained by OR ing the bits of range 16 down to 0.Then the rounded residue bits are concatenated with the mantissa sum in step 5. A. Algorithm Fig 2.Floating Point Adder with Residue Step1: Number X=S x, Exponent X,, Mantissa X. Number Y=S Y, Exponent Y, Mantissa Y. Number X & Number Y is connected to special case unit which are having Denormals, Zero mantissa, Infinity etc., are connected via special case unit. Step2: In this unit here two possible cases are faced for exponent subtraction. Case1: If exponent X is greater than exponent Y then larger exponent is equals to exponent X, smaller exponent is exponent Y and larger mantissa is mantissa X., smaller mantissa is equals to mantissa Y. Case2: If exponent is smaller than exponent number Y then the larger exponent is equals to exponent Y,smaller exponent is exponent x and larger mantissa is mantissa Y., smaller mantissa is equals to mantissa X. Step3: The exponent difference (Diff) will be calculated using the exponent subtractor circuit and Right shift the smaller mantissa bits by Diff bits using seventy three bit right shifter. During the right shifting process the discarded bits are treated as residue bits. After shifting, the bits form a code word of mantissa in concatenation of bits (72 downto 0) in which 19 down to 0 bits are residue bits. Step4: Perform addition operation to both significands after aligning the smaller and larger mantissas.while Step6: After finding the residue bits perform the add rounding. Then the output of Add-Round block is connected to the 73- bit leading one detector which is meant for residue and then it is connected to 73-bit left shifter to get normalize the result. At the same time the output of mantissa addition is connected to leading one detector which belongs to Floating point adder (FPA) & the output of LOD is connected to 53-bit left shifter to get the normalized value. Step7: The output of FPA leading one detector draws closer or moves via multiplexer by selecting the selection line either 0 or 1. Step8: The exponent is increased one more than the larger exponent in case of one bit right shifting done. During the left shifting operation the exponent value is subtracted from larger exponent. Step9: The MSB bits of two floating point (FP)- numbers are given to XOR gate as inputs. The output of XOR gate is connected to MSB bit of resulted FP number. Step10: Finally, concatenate the output of XOR output (sign out), incremented or subtracted exponent means that final exponent and mantissa bits. Finally the output of SUM is s= IEEE754Round (X+Y), Residue R= (X+Y)-SUM; 4. IMPLEMENTATION Single path double precision floating point adder (FPA) [3] consists of different modules which are discussed here briefly. In this connection first one is swap circuit, then Exponent Subtractor, Right shifter/left shifter, leading one priority detector etc., will briefly explained here. Both the designs are implemented on a Virtex 5 and target device is xc4vlx15-12sf363

4 1011 FPGA and find that the FPAR occupies only 37 of area which is very less than previous work [2]. A.SWAP CIRCUIT Mantissa X, Mantiss Y, Sn are the inputs. Smaller mantissa and larger mantissa are the outputs. The simple algorithm for this swap circuit is if sign (Sn) = 0 then Mantissa X is larger significand and M Y is smaller significand.in case Sn= 1 then Mantiss Y is larger significand and M X is smaller significand. The larger significand is connected to the adder as one of the input. The smaller significand is connected to right shifter by the value of exponent difference (D) B.EXPONENT SUBTRACTOR In this exponent subtractor, EA, EB are inputs which are connected to exponent field of corresponding FP numbers. Outputs are larger exponent (LE), difference (D), and sign (Sn). The operation of the exponent subtractor is given here. Case1: If we subtract smaller number (EB) from larger number (EA), then the borrow is 0 then larger exponent is EA come by mux1. Case2: If we subtract larger number (EA) from smaller one (EB), then borrow will come as 1 then larger exponent is EB come by mux1.the output of difference (D) will depend on the selection line which is connected to borrow. If borrow may be either 0 or 1 that means selection line is either 0 or 1 of mux2. If the borrow is 1 then the difference will come after the 2 s complement addition or else if borrow is 0 then the circuit will get the absolute difference without performing 2 s complement addition. The larger exponent (LE) is connected to readjust the final exponent. Sign (Sn) will be used to compare the mantissa bits. Difference (D) is used to right shift the smaller significand. C.SPECIAL CASES S1 S2 S_CASE SCO SET Fig 3.Special Case Unit The maximum time and resources will be saved when we use the special case unit. Both number S1 and number S2 are set up as inputs to special case unit as shown in the above fig.3 and SCO is the special case output. SET signal enables or disables the S _CASE block if it is needed or not. A few combinations have a direct result; like zero and a normal number are bringing in the output will be the normal number in straight away. D.RIGHT SHIFTER WITH RESIDUE BITS The right shifter has one input which is of 53 bits. Using the exponent difference the shifted amount will be done. Output will be taken 73 bits. In our design discarded bits (20 additional bits) are used to get the accuracy. Three extra bits (GRS) are really necessary to preserve the accuracy of shifted floating point number The last bit is sticky bit is obtained by OR ing all the bits shifted out.in the result is 72 bits which consists of discarded bits from 19 down to 0. E.SIGNIFICAND ADDER XOR output in stage1 is considered as sign-out, which is used to determine the addition or subtraction. Here sign-out is connected to sub. If sub is equals to 0 means the circuit performs normal integer addition. In case of subtraction the sub bit is 1. This signal is used to invert one of the operands before addition in case of subtraction.ofcourse, we may use the ripple carry or carry look ahead adder etc., for better trade off the delay. F.ROUNDING When compared to all remaining techniques round to nearest even (RNE) [3] gives the almost less error. So we get the two different equations to get the round (rnd).if G=1 and R and T are not both zero, rnd=g(r+t).if G=1 and R and T are both zero, rnd=g(r+t) 1 L.Where L is least significand bit of significand adder output. G.LEADING ONE PRIORITY DETECTOR (LOPD) FOR FPA & FPAR There are number of ways to design the leading one detector, After addition is over then the next operation is normalization, during the normalization we need to know how many of the bits have to shift from LSB to MSB bit [10]. In this project leading one priority detector is used. Here my design requires two leading one circuits one for FPA and other one for Residue unit for normalizing the 64-bit floating point binary addition result. The result mantissa is priority encoded (to detect the position of the leading one) and left shifted so that the leading one becomes the MSB using this technique H. LEFT SHIFTERS The two basic varieties are the arithmetic left shift and therefore the arithmetic right shift. for binary numbers it's a bitwise operation that shifts all of the bits of its quantity; equally within the operand is simply moved a given number of bit positions, and therefore the vacant bit-positions are stuffed in. rather than being full of all 0s.After the obtain the results from the LOD, we left-shift the result from the adder to normalize to get the first bit as 1. The shifter can be implemented using sll in VHDL operator, or it can be explained behaviorally or data flow model also.

5 1012 During the normalization or shifting operations the exponent will be updated. The exponent updating is nothing but subtract the shifted amount or value from larger exponent. Our design requires two left shifters one is for FPA unit and other one is for Residue unit. Here my design requires two leading one circuits. For a double precision -precision FPA, the maximum required amount of left shift is 53.At the same time we need 73 bit left shifter to get normalize the residual error in this normalization process. D.MANTISSA ADDER Adder result is shown here in the figure7 for Floating Point Adder with Residue unit. 5. EXPERIMENTAL RESULTS A.FINAL RESULT The final result is shown here in the figure 4 for Floating Point Adder with Residue Fig 7. Significand Adder E.LEADING ONE DETECTOR LOD result is shown here in the figure 8 for Floating Point Adder with Residue unit. Fig 4. Floating Point Adder with Residue B. EXPONENT DIFFERENCE The Exponent Difference result is shown here in the figure 5 for Floating Point Adder with Residue unit Fig 8. Leading one detector F.LEFT SHIFTER (53 bit) Normalization result is shown here in the figure 9 for Floating Point Adder with Residue unit. Fig bit Exponent Subtractor C.RIGHT SHIFTER The Right Shifter result is shown here in the figure 6 for Floating Point Adder with Residue unit. Fig 9. Left shifter G.LEFT SHIFTER (73-BIT) Normalization result is shown here in the figure 10 for Floating Point Adder with Residue unit. Fig 6. Right Shifter Fig 10. Left shifter

6 1013 H.RTL SCHEMATIC for ADDER RTL Schematic of floating point adder with residue is shown here in figure.11 adder/subtractor increases the precision and accuracy and reduced the area overhead. In ALU design and for iterative or in sequential summation networks where the error will increase during computations, our design is really helpful in floating point computer arithmetic applications. REFERENCES Fig 11. RTL Schematic of floating point adder with residue I.SPECIAL CASES Some of the cases has been shown here in figure.12 Fig 12. Special Cases 6. COMPARISIONS&DEVICE-UTILIZATION Previous work[2] LU Ts Slices FP A FPA R Area Over Head 48 Proposed work LUT Slice s s Area Over Head 31 [1]. M. V. Manoukian and G. A. Constantinides, Accurate Floating point arithmetic through hardware error-free transformations, in Proc. Intl. Conf. on Reconf. Comp. Springer-Verlag, 2011, pp [2].Accumulation of Accurate Parallel Floating-Point. < arith2013.html> [3]. M. Ercegovac and T. Lang, Digital Arithmetic, ser. The Morgan Kaufmann Series in Computer Architecture and Design. Morgan Kaufmann, [4]. HDL implementation and analysis of a residual register for a floating-point arithmetic unit. [5]. I. J. Anderson, A distillation algorithm for floatingpoint summation, SIAM J. Sci. Comput, vol. 20, pp , [6] Y.-K. Zhu and W. B. Hayes, Correct rounding and a hybrid approach to exact floating-point summation, SIAM J. Sci.Comput., vol. 31, no. 4, pp , July [7] S. M. Rump, Ultimately fast accurate summation, SIAM J.Sci. Comput., vol. 31, no. 5, pp , September [8]. P. Kornerup, V. Lef`evre, N. Louvet, and J.-M. Muller, On the computation of correctly rounded sums, IEEE Trans.Comput., vol. 61, no. 3, pp , March [9]. A. Malik and S. -B. Ko, A Study on the Floating- Point Adder in FPGAs, in Canadian Conference on Electrical and Computer Engineering (CCECE-06), (2006) May, pp Table 1: Floating Point Adder with Residue 7. CONCLUSION This project presents the implementation of double precision floating point adder with residue unit. The whole design was captured in VHDL, tested in simulation using Model Tech s modelsim, placed and routed on a Vertex 5 FPGA from Xilinx. The proposed VLSI implementation of the Double Precision