I/O Functions. Register Names and Purpose. Outline MIPS Assembly Language Programming. MIPS ALP, OISC and X86 ALP. SPIM: Hello World ALP 3/18/2015

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1 MIPS ALP, OISC and X86 ALP A. Sahu CSE, IIT Guwahati Outline MIPS Assembly Language Programming Stack, Call/Return Recursive Call : Factorial Example OISC : One Instruction Set Computer X86 : CISC ALP, NASM Simulator Please be updated with MIPS Assembly Language Program Register Names and Purpose Name Register number Usage $zero 0 the constant value 0 $v0-$v1 2-3 values for results $a0-$a3 4-7 arguments $t0-$t temporaries $s0-$s saved $t8-$t more temporaries $gp 28 global pointer $sp 29 stack pointer $fp 30 frame pointer $ra 31 return address I/O Functions $v0 Function Parameter 1 print_int $a0 is int 4 print_string $a0 is address of string 5 read_int returned in $v0 8 read_string $a0 is address of buffer, $a1 is length SPIM: Hello World ALP.data msg:.asciiz "Hello World" You set $v0 to indicate.text the operation. Parameters in $a0, $a1.globl main main: li $v0, 4 # syscall 4 (print_str) la $a0, msg # argument: string syscall # print the string jr $ra # retrun to caller 1

2 Procedural Abstraction What is required? P(){} Q(){} Main P(); Q(); proc P proc Q Control flow (call and return) Data flow (parameter passing) Local and global storage allocation Take care of nesting Take care of recursion Control flow call Control flow return p = &A[0]; q = p + 99; la $t1, A addi $s2, $t1, 396 void xchg( ) { if (*p<*r) goto Z; xchg: lw $t3, 0($t1) X: r = p + 1; Y: xchg( ); r++; if (r q) goto Y; p++; if (p<q) goto X; X: addi $t2, $t1, 4 Y: jal xchg # $ra gets PC+4 addi $t2, $t2, 4 ble $t2, $s2, Y addi $t1, $t1, 4 blt $t1, $s2, X *p *r; Z: return; } lw $t4, 0($t2) blt $t3, $t4, Z sw $t3, 0($t2) sw $t4, 0($t1) Z: jr $ra # PC gets $ra Parameter passing thro registers p = &A[0]; q = p + 99; X: r = p + 1; Y: xchg(p, r); r++; if (r q) goto Y; p++; if (p<q) goto X; convention la $a0, A addi $s2, $a0, 396 X: addi $a1, $a0, 4 Y: jal xchg # $ra gets PC+4 addi $a1, $a1, 4 ble $a1, $s2, Y addi $a0, $a0, 4 blt $a0, $s2, X Passing many parameters Convention: Input to procedure $a0, $a1, $a2, $a3 Output from procedure $v0, $v1 Additional parameters: Use memory 2

3 Local storage allocation main P Q data code Nested calls P( ); void P( ) { void Q( ) { Q( );... return} return} jal P P:.. Q:.. jal Q... jr $ra jr $ra save and restore $ra Stack and push/pop operations MIPS ALP: Factorial Example $sp is the stack pointer push $ra addi $sp, $sp, 44 sw $ra, 0($sp) pop $ra lw $ra, 0($sp) addi $sp, $sp, 4 $sp int } factorial (int n){ if (n < 2) return 1; return (n factorial (n 1)); MIPS ALP: Factorial Example factorial: bgtz $a0, doit li $v0, 1 # base 0! = 1 jr $ra doit: sub $sp,8 # stack frame sw $s0,($sp) # for arg n sw $ra,4($sp) # ret addr move $s0, $a0 # save argument sub $a0, 1 # n 1 jal factorial # v0 = (n 1)! mul $v0,$s0,$v0 # n*(n 1)! # restore reg frm stack lw $s0,($sp) lw $ra,4($sp) add $sp,8 jr $ra Recursive calls data flow Stack is used for passing parameters when registers are not sufficient Stack is used for allocating local variables 3

4 Sharing registers Registers which are shared between caller and callee should be saved at the time of call and restored at the time of return Who does this? Conventions for saving registers $s0 to $s7 are called saved temporary these are preserved across calls saved by callee, if necessary $t0 to $t9 are called temporary these are not preserved across calls saved by caller, if necessary OISC OISC One instruction set computer (OISC), Sometimes called an ultimate reduced instruction set computer (URISC), Is an abstract machine that uses only one instruction Obviating the need for a machine language opcode. With a judicious choice for the single instruction and given infinite resources, Capable of being a universal computer Same manner as traditional computers that have multiple instructions Three Type of OISC Transport Triggered Architecture (TTA) Bit Manipulating Machine Arithmetic Based Turing complete Transport Triggered Architecture (TTA) TTA is a design in which computation is a side effect of data transport. Usually some memory registers (triggering ports) within common address space, perform anassigned assigned operation whenthe instruction references them. For example Using a single memory to memory copy instruction, this is done by triggering ports that perform arithmetic and instruction pointer jumps when written to. 4

5 Bit Manipulating Machines Bit Manipulating Machines are the simplest class. Copies one bit in memory and passes the execution unconditionally to the address specified by one of the operands of the instruction. This process turns out to be capable of universal computation because copying bits can conditionally modify the code that will be subsequently executed Arithmetic Based Turing complete Machines ABTCM use an arithmetic operation and a conditional jump. The instruction operates on integers which may also be addresses in memory. Currently there are several known OISCs of this class, based on different arithmetic operations Example OISC Subtract and branch if less than or equal to zero subleq a, b, c ; Mem[b] = Mem[b] Mem[a] ; if (Mem[b] 0) goto c Same using Accumulator subleq2 a, b ; Mem[a] = Mem[a] ACCUM ; ACCUM = Mem[a] ; if (Mem[a] 0) goto b Instruction Synthesis : SBLEQ JMP c == ADD a, b == MOV a, b == subleq Z, Z, c subleq a, Z subleq Z, b subleq Z, Z subleq b, b subleq a, Z subleq Z, b subleq Z, Z Instruction Synthesis : SBLEQ BEQ b, c == subleq b, Z, L1 subleq Z, Z, OUT L1: subleq Z, Z subleq Z, b, c OUT:... Instruction Synthesis : SBLEQ NOT a == subleq2 tmp ; tmp = 0 (tmp reg) subleq2 tmp subleq2 minus_one ; acc = 1 subleq2 a ; a' = a + 1 subleq2 Z ; Z = a 1 subleq2 tmp ; tmp = a + 1 subleq2 a ; a' = 0 subleq2 tmp ; load tmp into acc subleq2 a ; a' = a 1 ( = ~a ) subleq2 Z ; set Z back to 0 5

6 X86 (8086) Assembly Language Program Int GA=500; int fung(){ int FA=200; FA=FA+GA; } int main(){ int LA=100; LA=LA+GA; return 0; } C Example $gcc S test.c.file "test.c".globl GA.data.align 4.type GA, 4 GA:.long 500.text.globl fung.type X86 Assembly code.lfb0: ;; Local Fun Begin 0.cfi_startproc pushl %ebp ;; Push current FP.cfi_def_cfa_offset 8.cfi_offset 5, 8 movl %esp, %ebp.cfi_def_cfa_register 5 subl $16, %esp movl $200, 4(%ebp) ;; Local FA movl GA, %eax addl %eax, 4(%ebp) leave ; do the pop operation.cfi_restore 5.cfi_def_cfa 4, 4 ret.cfi_endproc.lfe0: ret ;;Local Fun End 0.size fung,. fung.globl main.type main:.lfb1: ;; local Fun Begin 1.cfi_startproc pushl %ebp.cfi_def_cfa_offset 8.cfi_offset 5, 8 movl %esp, %ebp.cfi_def_cfa_register 5 subl $16, %esp movl $100, 4(%ebp) movl GA, %eax addl %eax, 4(%ebp) X86 Assembly code movl $0, %eax leave.cfi_restore 5.cfi_def_cfa 4, 4 ret.cfi_endproc. LFE1 L lf E d1.size main,. main.ident "GCC: (GNU) (Red Hat )".section.note.GNUstack,"",@progbits cfi offset 5 8.LFE1: ;;Local Fun End 1 16 bit Microprocessor All internal registers as well as internal and external data buses were 16 bits wide 4 Main Register, 4 Index Register, 4 Segment Register, Status Reg, Instr Ptr. Not compatible with 8085, but with successors Two Unit works in parallel: Bus Interface Unit (BIU) Execution Unit (EI) AX accumulator reg BX base address reg CX count reg DX data reg SI source index reg DI dest index reg BP base pointer. SP stack pointer EAX AH AL EBX BH BL ECX CH CL EDX DH DL ESI EDI SI (Source Idx ) DI (Dest. Idx) EBP BP (Base Ptr ) ESP SP (Stack Ptr) EZ ECS EDS EES ESS EIP Z (Flag Reg) CS (Code Seg Reg) DS (Data Seg Reg ) ES (Extra Seg Reg ) SS (Stack Seg Reg) IP (Intr Ptr) 6

7 X86 Compatibility 8085 (8 bit) == > 8086 (16 bit) == > i386 (32 bit) or ia32== > x86 64 (64 bit) or ia64 AX (AH+AL) : 16 bit EAX 32 bit RAX 64 bit Register General registers EAX, EBX, ECX, EDX Acc, Base Ptr for Memory, Ctr and Interrupt, Data Segment registers CS, DS, ES FS GS, SS Code, Data, Extra (far,near,videomem), Stack Index and pointers ESI EDI EBP EIP ESP Indicator EFLAGS Index and Ptr Register ES:EDI EDI DI : Destination index register Used for string, memory array copying and setting and for far pointer addressing with ES DS:ESI, EDI SI : Source index register Used for string and memory array copying SS:EBP EBP BP : Stack kbase pointer register Holds the base address of the stack SS:ESP ESP SP : Stack pointer register Holds the top address of the stack CS:EIP EIP IP : Index Pointer Holds the offset of the next instruction, It can only be read Memory Model: Segment Definition.model small Most widely used memory model. The code must fit in 64k. The data must fit in 64k..model medium The code can exceed 64k. The data must fit in 64k..model compact The code must fit in 64k. The data can exceed 64k..medium and.compact are opposites. hellodat SEGMENT BYTE 'DATA' ;Define the data segment dos_pr EQU 9 ;define a constant via EQU strng DB 'Hello World',13,10,'$ ; Define char string hellodat ENDS hellodat SEGMENT ;define a segment dos_print EQU 9 ;define a constant strng DB 'Hello World',13,10,'$' ;Define char string hellodat ENDS.data dos_print EQU 9 ;define a constant strng DB 'Hello World',13,10,'$' ;Define char string Data Allocation Directives db : define byte dw: def. word (2 bytes) dd: def double word (4) dq : def quad word (8) equ : equate assign numeric expr to a name.data db A 100 dup (?) ; define 100 bytes, with no initial values for bytes db Hello ; define 5 bytes, ASCII equivalent of Hello. dd PtrArray 4 dup (?) ;array[0..3] of dword maxint equ ; define maxint=32767 count equ 10 * 20 ; calculate a value (200) 7

8 Assemby code: Loop Loop simply decreases CX and checks if CX!= 0, if so, a Jump to the specified memory location MOV CX,100 _LABEL: INC AX LOOP _LABEL LOOPNZ : LOOPs when the zero flag is not set MOV CX,10 _CMPLOOP:DEC AX CMP AX,3 LOOPNE CMPLOOP Assemby code: Nested Loop: One CX register mov cx, 8 Loop1: push cx mov cx, 4 Loop2: stmts loop Loop2 pop cx stmts loop Loop1 Arithmetic ADD, SUB, MUL, DIV ADD AX, 5 AX = 0003 AX = 0008 Logic AND, OR, XOR, NOT AND CH, DL CH = DL = CH= Bit manipulation SHL/SHR SHL AL, 1 AL= ;(SHL by 1) Comparisons and jumps JMP, CMP, Jxx, CALL, RET 8