The University of Michigan - Department of EECS EECS 370 Introduction to Computer Architecture Midterm Exam 1 February 17, 2011

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1 The University of Michigan - Department of EECS EECS 370 Introduction to Computer Architecture Midterm Exam 1 February 17, 2011 Name: KEY_(Answers in red) University of Michigan uniqname: (NOT your student ID number!) Open book, open notes. No laptops, PDAs, cell phones, etc. (calculators are ok). Questions vary in difficulty; it is strongly recommended that you do not spend too much time on any one question. For questions where a box is provided, please put your final answer in the box. The rules of the Honor Code of the University of Michigan - College of Engineering apply for this exam. Honor code pledge: I have neither given nor received aid on this examination, nor have I concealed any violations of the Honor Code. Signature: (Exams without a signed pledge will not be graded) Question Score/Point Value Short answer questions /10 1. Memory alignment /10 2. Assembler/Linker /12 3. C to MIPS /10 4. LC2k assembly /10 5. Caller/Callee assignment /12 6. Finite state machines /7 7. Digital design /5 8. New ISA /12 9. Single cycle datapath /12 TOTAL /100 Page 1 of 14

2 Short Answer Questions [2 pts. each] S1. Which is not typically stored on a function stack frame? a) Function parameters b) Local variables c) String constants d) Caller-save registers e) Callee-save registers S2. Which program would execute fastest on the LC2k single-cycle datapath? a) A program consisting of 100 lw instructions b) A program consisting of 100 add instructions. c) A program consisting of 100 not-taken beq instructions. d) All of these programs take the same amount of time. S3. Why is LC2k considered a RISC architecture? Select the best answer. a) It only has 8 opcodes b) All instructions are 32-bits in length c) There are no opcodes to load bytes and halfwords like MIPS. d) It uses PC-relative addressing for BEQ. e) Add and nand have three operands rather than two. S4. Is it possible for a function to have an empty relocation table? Briefly explain why or why not. Yes, a function that contains no function calls (i.e., a leaf function) and no references to global variables would contain no instructions that require relocating by the linker, and hence it s relocation table would be empty. S5. Select the correct bitwise carry out function for the fourth carry out of a carry lookahead adder with a group of size of four. Note that we are starting with a subscript of 1 for the lowestorder bit in the group. a) G 4 + P 4 (G 3 + P 3 (G 2 + P 2 )) b) P 4 G 4 + P 4 G 3 + P 4 P 3 G 2 + P 4 P 3 P 2 G 1 c) P 4 G 4 d) G 4 + P 4 G 3 + P 4 P 3 G 2 + P 4 P 3 P 2 G 1 Page 2 of 14

3 Longer Questions [Varying points] 1. Memory Alignment [10 pts.] Consider a 32-bit architecture requiring strict alignment. struct { double a; char b; int *c; struct { char d; double e; } f; char *g[10]; short h; } fred; a) [7 pts.] Indicate, in the following table, the address ranges spanned by the variables in the struct. Addresses start at 128. Start Address and End Address are inclusive, so for example, a Start Address of 4 and End Address of 5 would be two bytes. Variable Start Address End Address Total Size a b c d e f g h b) [3 pts.] How many bytes does struct fred use in total? Start addressing from where a s address begins and consider any padding that might be needed to ensure proper alignment for variables that may follow the struct in memory. 80 bytes Page 3 of 14

4 2. Assembler/Linker [12 pts.] Given the following C code, please answer the questions that follow. You should assume variables declared static are not entered into the symbol table by the linker. 0 char a; 1 int foo(int p) { 2 static int b = 0; 3 int *d; 4 b++; 5 d = malloc( 10 * sizeof(int) ); 6 printf( %d, b); 7 d[5] = 6; 8 a = 6 ; 9 return b; 10 } a. [4 pts.] List whether a given variable is located on the stack, static, or heap by circling the answer below: a Stack Static Heap b Stack Static Heap d Stack Static Heap d[5] Stack Static Heap *d Stack Static Heap b. [4 pts.] Please circle the items that are placed in the symbol table: foo malloc printf d %d b p a sizeof 6 c. [4 pts.] Indicate the line numbers associated with all relocation table entries for this program. Line Numbers: 2, 4, 5, 6, 8, 9 (no points are lost if lines 4 and 9 are not listed) Page 4 of 14

5 3. MIPS/C Conversion [10 pts] Jonathon has the following C code excerpt that he wishes to convert into MIPS Assembly: while ( ((x >> 1) & 0x1)!= 0 ) { x = x >> 1; count++; } Jonathon has started, but unsure how to finish the conversion to MIPS. Please help him convert the piece of C code to MIPS Assembly by filling in the blanks below. Assume that x is stored in $1 and count is stored in $2, both integer values. (Note: srl is the MIPS shift right logical instruction). addi $3, $0, _1_ loop: srl $4, $1, _1 (or $3 is fine) and $5, _$4_, $3 beq $5, _$0_, done add $1, _$4_, $0 addi $2, _$2_, _1_ beq _$0_, $0, _loop_ done: Page 5 of 14

6 4. LC2K Assembly [10 pts.] Given the following LC2K assembly program, answer the questions that follow. 0 lw 0 1 num 1 lw 0 2 b 2 lw 0 3 check 3 lw 0 4 negone 4 lw 0 5 five 5 nand nand beq 0 3 other 8 add beq 0 0 done 10 other add done sw 0 2 b 12 halt 13 num.fill b.fill 0 15 check.fill 1 16 negone.fill five.fill 5 a) [2 pts.] Which one MIPS assembly instruction corresponds to what lines 5 and 6 are executing? (no points lost if just and instruction is listed without registers) (can also have and $3, $3, $1) and $3, $1, $3 b) [4 pts.] What is the final value stored in address 14 when this program finishes executing? c) [4 pts.] In one or two sentences, describe what this program does. If num is even, b gets set to 5. If num is odd, b gets set to -1-1 Page 6 of 14

7 5. Caller/Callee [12 pts.] You are given the following two C functions: int rick(void) { int n=0, e=1, v=2, r=3, g; n = n + e + v + r; r = r + abs(n); for(g=0; g < 7; g += 2){ e = roll(g,e); e += v; } if(r > 5) return r; if(e == 1) return e+1; return -1; } int roll(int v, int y) { int i=v, e=y, o, u=-1; u = rand(); u++; printf( u was rolled: %d, u); for (o = 0; o < 5; o++) { i = i * e + u; printf( Astley: %d, i); } return i; } a.) [8 points] To answer this question, fill the tables below. You must show your work on the copy of the code above to receive any credit. Assume that the function rick is called only once. How many store/load operations are executed for each variable in rick and roll? Consider the number of saves and restores occurring in only the function being analyzed (i.e., rick() and roll()), not functions called by them or calling them. Do the analysis assuming for each variable both a caller-saved and a callee-saved mapping, and consider the single call to rick and the total of all the resulting call(s) to roll. Assume that parameters v and y are stored in special input parameter registers. rick() Callersaved Calleesaved roll() Callersaved Calleesaved # sw # lw # sw # lw # sw # lw # sw # lw n i e e v o r u g Page 7 of 14

8 Problem 5 continued b.) [4 points] If you have 3 caller-saved and 2 callee-saved registers available, what is the best mapping of registers to variables to minimize the total number of load/store operations? (circle your selection below) rick() n caller callee roll() i caller callee e caller callee e caller callee v caller callee o caller callee r caller callee u caller callee g caller callee Page 8 of 14

9 6. Finite State Machines [7 pts.] Consider the synchronous finite state machine specified in the following table. Current State Input Next State Output A 0 A 0 A 1 B 0 B 0 B 0 B 1 C 0 C 0 B 1 C 1 C 1 1. [5 pts.] Draw the state diagram (a graph composed of nodes and edges) for the finite state machine described by the state table. Label the states and transitions, and indicate output values. It would also be fine to have used a Mealy-style diagram, with output values appearing on arcs (in addition to input values). 2. [2 pts.] Is this a Mealy or Moore machine? Moore. Although the table format makes it look like a Mealy machine, the output values depend only on the current state, not the current state and current input. Page 9 of 14

10 7. Digital Design [5 pts.] For the circuit below consisting of a NAND gate, a D flip-flop (rising/positive edge triggered), and an AND gate, sketch the outputs Y and Z on the provided timing diagram. Neglect propagation delays. Answer: Page 10 of 14

11 8. New ISA [12 pts.] Below is the description of a new, stack-based ISA that only contains one register, REG. The ISA is byte addressable. R-type instructions Bits Bits 12-0 Opcode Unused Instruction Opcode Action Push 000 STACK[top] = REG Pop 001 REG = STACK[top] Flip 010 Flip the stack (the top value is on the bottom and the bottom value is on the top and all values in the middle are reversed) Halt 011 Halts the machine. I-type instructions Immediate is a 13 bit 2 s complement number Bits Bits 12-0 Opcode Immediate Instruction Opcode Action Load 100 REG = MEM[immediate + STACK[top]] Store 101 MEM[immediate + STACK[top] = REG Bne 110 If (REG!= STACK[top]) PC = PC offset else PC = PC + 2; U-type instructions Bits Bits 12-2 Bits 1-0 Opcode Unused Math code Instruction Opcode Math Math code Action ALU.<Math> 111 Add 00 REG = REG + STACK[top] Sub 01 REG = REG - STACK[top] Xor 10 REG = REG xor STACK[top] Page 11 of 14

12 Problem 8 continued a.) [4 pts.] What type of memory addressing modes does this architecture use? Circle all that apply. Direct Addressing Indirect Addressing Base + Displacement b.) [4 pts.] Translate the following instructions into machine code. (Write your answers in HEX) Instruction Flip Bne -5 ALU.xor Machine Code 0x4000 0xDFFB 0xE002 c.) [4 pts.] You ran a compiler on the following C code to generate machine code for the new ISA. However, due to a compiler bug, the instructions were mixed up! Reorganize the instructions below to execute the C code. You may not need all the instructions and you may not need to fill all the lines. Note: ambiguity in this problem resulted in its elimination from the exam. If you assume a value from the stack is NOT popped when used, the solution is below. a += b; a is located at memory location 100, and b is located at memory location 104. REG initially contains the value 0 and the stack is initially empty. Mixed up instructions Push Push Load 104 Load 100 Store 104 Halt Store 100 Flip ALU.add Load variables from memory Perform addition Write to memory and end Push Load 104 Push Load 100 ALU.add Flip Store 100 Halt Page 12 of 14

13 9. LC-2K Single Cycle Datapath [12 pts.] You have been asked by your manager to implement a dedicated hardware stack in the LC-2K s datapath. The ISA engineers have given you three new instructions, described as follows, to use as your basis for redesigning the LC-2K (SP = stack pointer): push rega Effect: STACK[$SP] = rega, $SP = $SP + 1 pushi imm Effect: STACK[$SP] = signed_offset, $SP = $SP + 1 pop rega Effect: rega = STACK[$SP], $SP = $SP 1 a) [4 pts.] Assuming all eight original LC-2K instructions are still usable, how many instruction bits have been added to accommodate these new instructions? Before there were 3 bits to represent 8 instructions, we now have 11 instructions, so we need one additional opcode bit. b) [8 pts.] Add all necessary hardware to one of the attached LC-2K datapath diagrams to support the new stack instructions. The Stack Memory (depicted as Stack ) behaves similarly to the data memory. It has two inputs one for data input, and one for an address input. It has two control signal inputs, EN (to enable an operation on Stack Memory), and R/W (to select whether you are reading or writing to the stack). It has a single data output which will return the result of a read operation on this memory. You may add wires and MUXes as needed, but you must add a SP register. Connect the STACK memory to the rest of the datapath so that the three new instructions are fully supported. You may not add ALUs/Adders you must use the existing ALUs/Adders to accomplish this part of the question. In addition to adding MUXes, you may also need to modify existing MUXes. Extend the control ROM s size and outputs as needed. Try to keep your work neat and mark the diagram you wanted graded with GRADE ME. One solution is presented on the next page. There are other solutions, i.e. it is possible to use the adder that calculates PC+1+Offset if you properly connect its inputs and outputs to/from the SP register. It is possible, but much more difficult, to add the SP register to the register file. You must not forget that the pop instruction writes to rega, so you must add instruction bits to the register destination selection MUX. The output of the Stack must go to the MUX that selects what gets written to the destination register (rega for pops). You should not use the PC+1 adder to increment/decrement the SP register. If you do so, your single cycle datapath will fail to update the PC to move on and execute the next instruction. Page 13 of 14

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