Understanding Signal to Noise Ratio and Noise Spectral Density in high speed data converters

Transcription

1 Understanding Signal to Noise Ratio and Noise Spectral Density in high speed data converters TIPL 4703 Presented by Ken Chan Prepared by Ken Chan 1

2 Table o Contents What is SNR Deinition o SNR Components o SNR Thermal, Quantization, Jitter Calculation o SNR Jitter Dominated What is NSD Deinition o NSD How is NSD dierent rom SNR Components o NSD Same as SNR, just speciication is dierent Using NSD in typical application In band Perormance estimate using close in phase noise Out o band emissions estimate based on out o band phase noise 2

3 What is SNR - Signal-to-Noise Ratio Basics SNR is the ratio o the signal power to the noise power that corrupts the signal. This parameter does not include harmonic distortion. In the time domain: Amplitude (db) Noise Signal Noisy Signal In the requency domain: Signal SNR SNR P NOISE log P, dbm SIGNAL P P, dbm log SIGNAL NOISE P P NOISE NOISE, dbm, dbm / Hz log BW Hz Noise Level FREQUENCY (Hz) 3

4 Maximizing the SNR in an ADC SNR P SIGNAL, dbm P NOISE, dbm Quantization Thermal Aperture Jitter SNR can be increased in the ollowing ways: Increase signal power Full Scale Range (FSR) Decrease noise power Quantization Noise Clock Jitter ADC Aperture Jitter Thermal Noise Clock Jitter 4

5 SNR by Individual Noise Contributors Total SNR can be calculated by the sum o the individual noise sources: SNR total Design Choice ADC Selection Sampling Clock Selection Sampling Rate log SNR QUANT SNR JITTER SNR THERM SNR QUANT = SNR due to quantization SNR JITTER = SNR due to clock and aperture jitter SNR THERM = SNR due to thermal and transistor noise 1 Eect on Noise N-bits aects quantization noise, aperture jitter and thermal noise by design Clock jitter Bandwidth over which noise is distributed 5

6 Quantization Noise and SNR SNR due to quantization error, assuming a sine wave input: SNR QUANT 6.02 N db Example: 14-bit converter where N=14: SNR QUANT db How to determine the required ADC resolution? An N-bit ADC determines the maximum possible SNR or the system Practically, an ADC s SNR is limited by other actors: Sampling clock jitter ADC jitter and thermal noise Other system noise sources Over-sampling rate and application channel bandwidth 6

7 Transistor and Thermal Noise and SNR Noise Mechanism α Spectral Proile Source Cause Shot I DC white pn-junctions DC bias current is not constant Flicker 1/ 1/ Active devices Carriers are trapped and released in a semiconductor Thermal T white resistors Thermal excitation o carriers in a conductor Noise in an ADC: Track-and-hold is dominant source Capacitors source no noise Resistor results in kt/c noise v 2 no ( ( 4 ktr kt C ) v 2 R ( ) * * 2 1 ) * ( ) * ( 2 2 RC o ) 7

8 Clock Jitter and SNR Clock jitter is the random variation o the clock edge compared to its ideal point in time Theoretical limit o SNR due to jitter: SNR where : in j j dbc input clock 20 log( requency jitter 2 in j ) Total jitter is the rms sum o the individual jitter contributions For ADCs, this is generally the external clock jitter and aperture jitter T external 2 aperture 2 8

9 More on Clock Jitter Clock jitter causes imprecise sampling intervals which results in incorrect sampling instances and thereore errors in the sampled signal Clock jitter has an increased eect at higher input requencies or higher maximum input slew rates 9

10 Sources o Clock Jitter The total clock jitter or an ADC is rom the aperture jitter and the external sampling clock jitter. Clock jitter is the jitter contribution rom the external clock source and can be measured by using a phase noise analyzer Aperture jitter (a.k.a. aperture uncertainty) is the jitter contribution rom the ADC, due to the internal clock buers. This cannot be measured directly using a phase noise analyzer. Example: aperture jitter or the ADS4249 The total clock jitter is determined by rms sum o all individual contributions: TOTAL 2 EXTERNAL 2 APERTURE

11 Example Phase Noise Plot 11 Noise Spectral Density (dbc/hz) Frequency (MHz)

12 Calculating Jitter rom Clock Phase Noise Jitter is a result o noise on the sampling clock. Assuming the wideband clock noise is relatively low, then the clock jitter is calculated by integrating the clock phase noise over a speciied BW then converting to seconds. j 2 2 clk N Where: N = Phase Noise Power (dbc) 0, 1 = requency limits o integration j = clock jitter Example rom previous slide s phase noise plot: N = dbc/hz (rom khz to MHz oset) F clk = MHz 2 j MHz dbc / Hz s 12

13 A DIFFERENT WAY TO LOOK AT CLOCK JITTER/NOISE 13

14 Limitation o the Traditional SNR Calculation Due to Jitter The traditional SNR due to jitter equation gives the SNR over the entire Nyquist band, with the jitter measured over a wide clock oset requency The equation is a unction o the analog input requency and jitter perormance SNR where in j j dbc : input clock 20 log( requency jitter I the ADC clock is already ine tuned to the best jitter perormance, would the only option let to meet stringent SNR perormance is to adjust the input requency? I so, what is the point o over-sampling ADCs? 2 in ) j 14

15 General Equation or ADC SNR It turns out the SNR equation is also a unction o clock requency as well. Recall the jitter equation: clk I we substitute the jitter equation into the SNR equation, we would get the ollowing: SNR j dbc 20 log( 2 20 log( 20 log( 20 log( j in The irst term is the inherent integrated noise due to clock noise. The second term is a correction term. This is important to help us understand the perormance o over-sampling. I over-sampling is used, the SNR can be improved 2 2 N N N 2 clk N in clk ) ) ) 20 log( ) 20 log( N in clk clk in ) ) 15

16 Why is the general equation important? The general equation is important because the traditional equation oten simpliies the ADC clock noise loor as an uniorm white noise. In reality, the ADC clock usually has better noise behavior as the oset requency increases, and also, the clock is oten well iltered. Simpliied integrated clock noise Actual phase noise 16

17 System Requirement Implication Most importantly, some o the stringent system requirements oten are bandwidth speciic. I.e. noise spec over a speciic bandwidth. For instance, when given a certain blocker signal, the traditional SNR calculation may overestimate the noise over the bandwidth o the wanted signal. This may make jitter speciication o the clock impossible to achieve. 17

18 Experiment Result Clocking the ADC with a 250MHz tone + MHz noise ranging rom 240MHz to 250MHz ADS4149 at 250MSPS Two inputs shown and overlaid: MHz and 0MHz (DAC5681 output) 18

19 ADC Test Result 20log(250/) = 28dBc 20log(250/0) = 8dBc 19

20 DAC NSD VS SNR 20

21 SNR Jitter estimate is the same or DACs The total SNR is the vector sum o all individual SNR contributions SNR total log SNR QUANT SNR CLK SNR THERM 1 SNR QUANT = SNR due to quantization SNR CLK = SNR due to clock and aperture jitter SNR THERM = SNR due to thermal and transistor noise Similar treatment o clock jitter (integrated phase noise) or SNR limit o DAC sampled system SNR where : i j j dbc 20 log( output requency clock jitter 2 i j ) 21

22 NSD or SNR? For DACs, generally the noise spectral density (NSD) is more important than overall SNR The shape o the NSD around the carrier must meet mask requirements When SNR is required, customer s oten limit the bandwidth o the transmitted signal by a bandpass or lowpass ilter For this reason, newer datasheets report NSD rather than SNR s = 1GSPS out = 20MHz Signal Noise DAC output noise is comprised o Quantization noise Thermal noise Jitter noise Data dependent noise 22

23 Why NSD over SNR? In real systems, there is oten tight iltering around the band o interest, where all the noise outside o that band is iltered out. Rather than showing the SNR o the signal in the irst Nyquist zone, it is more convenient to show the noise power so that the total noise power in the uniltered band can be readily calculated For example, consider a DAC3484 running at MSPS with a band o interest o 0 MHz and the ollowing ilters: A MHz low-pass ilter (passing ull irst Nyquist zone): A 0-MHz low-pass ilter: 160 dbc / Hz log MHz 72. dbfs SNR dbfs 0 dbfs dbc / Hz log 0 MHz dbfs SNR dbfs 0 dbfs 80 23

24 Converting NSD to SNR The SNR o the DAC can be calculated rom the NSD spec The SNR was traditionally deined as the ratio o the power o the undamental to the power o the noise integrated over the irst Nyquist zone. SNR It can also be calculated directly in dbfs rom the NSD in dbc/hz SNR dbc dbfs P dbm Example: DAC3484 running at 1.25 GSPS with MHz output SNR, undamenta l NSD dbm / Hz log S 0 dbfs NSD dbc / Hz log F 2 S 1.25 GHz 160 dbc / Hz log 72. dbfs dbfs dbfs 04 F

25 NSD to SNR tradeos Jitter/Phase noise SNR estimates based on Jitter are good estimates or SNR or the entire Nyquist band may be too pessimistic or BW limited applications. SNR estimates based on NSD (typically measured at some MHz oset) do not account or close-in phase noise which could aect inband EVM Useul or out o band estimates like ACPR Also useul or transmit mask requirements Using the clock NSD curve and BW limited noise calculations would be the ideal solution or in-band and out-o-band measurements.

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