AVR Logical and Bitwise Instructions

Transcription

1 AVR Logical and Bitwise Instructions Assembly Language Programming SDSMT Dr. Randy C. Hoover

2 Boolean Logic An algebraic system for Boolean data Set: {false, true) Operations: and, or, not The operations obey certain axioms such as associativity, commutativity, identity Named after George Boole ( ) Implemented via digital logic circuits fundamental to the function of a computer 2/5/18 2

3 Recall: SREG How do logical operations effect the SREG? Status Register Bits indicating status of processor Located in I/O space I T H S V N Z C Global Interrupt Enable Bit Copy Storage Half- Carry Flag Sign Bit Two's Complement Over-flow Flag Negative Flag Zero Flag Carry Flag 2/5/18 3

4 Carry and Zero Flags Carry This generally indicates a carry out of the most significant bit during the addition of two bytes Zero This indicates when a result is zero Z=0 when result IS NOT zero Z=1 when result IS zero 2/5/18 4

5 Negative and overflow Flags Negative This is a copy of bit 7 of the result For signed data, it indicates the result is negative Two's complement overflow Set (to 1) when an arithmetic operation gives an out-of-range result assuming two's complement (signed) data 2/5/18 5

6 Half Carry and Sign Flags Half Carry This usually represents the carry out of the first nybble of an addition operation Sign Indicates the expected sign of a two's complement arithmetic operation This is always N^V (exclusive-or) 2/5/18 6

7 Global Interrupt and Bit Copy Global Interrupt enable This bit is 1 when interrupts are enabled Interrupt signals are ignored while this bit is 0 BiT copy Except the reset interrupt Used as a temporary storage location for a single bit when using the AVR bit load and bit store instruction 2/5/18 7

8 AVR's NOT The AVR processor's COM instruction applies the Boolean NOT to every bit in a register com Rd Also called the one's complement Affects the status register flags H S V N Z C - N^V 0 R 7 zero? 1 2/5/18 8

9 AVR's And Or The AVR processor's AND and OR instructions apply the Boolean operation to each column of a pair of registers and Rd, Rr or Rd, Rr These affect the status register flags H S V N Z C - N^V 0 R 7 zero? - 2/5/18 9

10 AVR's Exclusive Or The AVR processor's EOR instruction applies the Boolean operation to each column of a pair of registers eor Rd, Rr This affects the status register flags in the same way as the AND and OR instructions H S V N Z C - N^V 0 R 7 zero? - 2/5/18 10

11 Immediate Mode Immediate mode versions of AND and OR are available for registers R16 through R31 only andi Rd, k ori Rd, k Rd = Rd AND krd = Rd OR k The second operand is any expression which is assumed to be a byte value The byte is coded as part of the instruction 2/5/18 11

12 Using AND Common application Clear one or more bits in a byte Mask A byte with 0's in positions to be cleared, 1's elsewhere Example andi R16, $0F ;clear high nybble andi R16, ~((1<<7) (1<<5)) ;clear bits 7 and 5 2/5/18 12

13 Using AND Common application Test if one or more bits are set in a byte Mask A byte with 0's in positions to be ignored, 1's in positions to be tested Example andi R16, $0F ;test low nybble breq allzero ;branch if low nybble all zeros 2/5/18 13

14 Using OR Common application Set one or more bits in a byte Mask A byte with 1's in positions to be set, 0's elsewhere Example ori R16, 0b ;set bits 6 and 5 ori R16, (3<<5) ;same as above 2/5/18 14

15 Using OR Common application Combining bit fields into one byte Preprocessing Use ANDI to be sure other bits in the byte are cleared Example andi R16, $0F ;isolate low nybble andi R17, $F0 ;isolate high nybble or R16, R17 ;combine low and high nybbles 2/5/18 15

16 Using EOR Common application Flip one or more bits in a byte Mask A byte with 1's in positions to be flipped, 0's elsewhere Example ldi R16, 1<<6 ;mask to flip bit 6 eor R20, R16 ;eor has no immediate mode 2/5/18 16

17 Application: Letter Case Convert characters to upper case The only difference between ASCII codes for the upper and lower case characters is bit 5 Uppercase characters: bit 5 = 0 Lowercase characters: bit 5 = 1 OR can be used to convert to lower case AND can be used to convert to upper case EOR can be used to toggle case 2/5/18 17

18 Application: ASCII - BCD The ASCII codes for the digits have the digits' BCD value in the lower nybble. All digits have upper nybble 0b0011 Use AND to convert ASCII to BCD Use OR to convert BCD to ASCII 2/5/18 18

19 Packed BCD If two BCD digits are to be packed into one byte Swap one to the high nybble The AVR instruction set has a swap instruction exactly for this purpose Use OR to combine them into one byte 2/5/18 19

20 Other BIT Manipulations Set/Clear bits in register sbr Rd, k cbr Rd, k Only registers k is a byte with 1's in positions to be set or cleared set means make the selected bit 1, clear means make it 0 You can also do this with ORI or ANDI! These are aliases for: ori Rd, k andi Rd, ~k 2/5/18 20

21 Other BIT Manipulations Set/Clear bit in I/O register sbi A, b cbi A, b Only I/O registers 0-31 (0x00 0x1F) are accessible with this instruction The bit number must be 0 through 7 Note that these instructions affect only 1 bit in the register No flags are affected by these instructions 2/5/18 21

22 TST The TeST instruction affects status flags, but does not change any registers tst Rd This instruction is identical to (an alias for) AND Rd, Rd Commonly used to see if a register is zero, or contains a negative/non-negative value. 2/5/18 22

23 CLR/SER These instructions clear or set all of the bits in a register clr Rd (alias for eor Rd, Rd) This is really the eor instruction which does affect status flags ser Rd (alias for ldi Rd, $FF) Only available for registers The load instructions do not affect flags 2/5/18 23

24 SWAP This swaps the two nybbles in a register swap Rd Does not affect any flags This instruction is commonly used in preparation for combining two nybble values into a single byte 2/5/18 24

25 Shift Shift instructions move bits to adjacent positions in a register All bits move at the same time and in the same direction, left or right Left shift or right shift What value is used to fill in the vacated spot on one end of the register? What happens to the bit that falls out of the other end of the register? 2/5/18 25

26 LSR, LSL These are the logical shifts lsr Rd lsl Rd The bit brought in is 0 The bit falling out is copied into the carry flag Flags H S V N Z C LSR: - N^V N^C 0 zero? Rd 0 LSL: Rd 3 N^V N^C R 7 Zero? Rd 7 2/5/18 26

27 ASR This is an arithmetic shift asr Rd The sign bit is preserved (R 7 = Rd 7 ) The lsl instruction is used for an arithmetic left shift Flags H S V N Z C - N^V N^C R 7 zero? Rd 0 2/5/18 27

28 ROL/ROR The rotate instructions use the carry flag to determine the bit value in the vacated position rol Rd (R 0 = C)/ror Rd (R 7 = C) Flags H S V N Z C ROL: Rd 3 N^V N^C R 7 Zero? Rd 7 ROR: - N^V N^C R 7 zero? Rd 0 2/5/18 28

29 Arithmetic Application lsl Rd calculates Rd *= 2 Overflow may occur Check C for unsigned data Check V for signed data lsr Rd calculates Rd /= 2 (unsigned) asr Rd calculates Rd /= 2 (signed) Rounding is to the left on the number line -5 shifted right gives -3 (not -2) 2/5/18 29

30 Additional Bit Manipulations Because the AVR processor is designed for embedded applications with limited memory, bit-based data and operations are quite common As a result, many specialized bit operations are present We have already looked at sbr, cbr, sbi, cbi, and swap 2/5/18 30

31 BST/BLD The bit store and bit load instructions allow transfers between a single bit of any register and the T flag in SREG bst Rd, b T = Rd(b) Note that Rd is not the destination register, but it does appear as the first operand of this instruction bld Rd, b Rd(b) = T 2/5/18 31

32 BCLR/BSET These instructions clear or set a bit in the status register (by its position) bclr s SREG(s) = 0 bset s SREG(s) = 1 s is a position You will never need these instructions - All have a special alias so you do not need to lookup the bit number of each flag 2/5/18 32