SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces
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1 SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces Arash Saifhashemi 1 Peter A. Beerel 1,2 1 Ming Hsieh Dept. of Electrical Engineering, University of Southern California 2 Fulcrum Microsystems, Calabasas CA, CPA 2011 University of Limerick, Ireland
2 Outline Introduction Why asynchronous circuit design? Hardware description languages SystemVerilog Abstract Communication Basic Features Channels - Send, Receive Channel status and mixed-level simulation SystemVerilog Abstract Communication Extended Features Peek and Probe Split and synchronized communication One-to-many and one-to-any channels Results and Conclusion
3 Why Asynchronous Circuit Design? Systems on chip: chips are becoming distributed systems Communication-dominated No globally synchronous clock Asynchronous alternative Local handshaking: CSP-like communication Benefits Higher speed Shorter globally critical paths Lower power consumption Remove power-hungry global clock Modules active only when necessary Robustness to variations Process, voltage, and temperature 60 IP blocks 350 RAMs: Communication Bottleneck Pictures: [Benini 06]
4 Asynchronous Circuit Design - Today Applications Ethernet Switches (Fulcrum Microsystems) Ultra high-speed FPGAs (Achronix) Multi-core network on Chip Ultra low-power chip design Basic challenges Lack of CAD tools to automate designs Proteus design flow (USC) CAD Tools Commercially Available Leverage off of available synchronous CAD tools Starting at a high-level specification written in SystemVerilogCSP Proprietary CSP inspired SystemVerilog language Standard Synthesis Asynchronization and Optimization Standard Physical Design Final Layout
5 Hardware Description Languages Desirable features of an HDL Concurrency Timing e.g.: A=B (C=D ; E=F) e.g.: A=B after 5ns Support for various levels of abstraction Support by commercial CAD tools Support for both synchronous & asynchronous Communication abstraction Ease of design Design usability: protocols evolve and change Architecture evaluation before implementation Ease of adoption by synchronous designers CSP as a basis for a hardware description language Suitable for modeling abstract communication Lacks some desirable features Synthesis High level (Behavioral) Gate level (Netlist) Transistor level (Netlist) Simulation/ Verification
6 Previous Work New Language inspired by CSP Have limited CAD tool support - LARD [Edwards et al], Tangram [Berkel et al], CHP [Martin] Software languages No inherent support for timing, limited CAD tool support - JCSP [Welch et. al] VHDL Fine grained concurrency is cumbersome [Frankild et al, Renaudin et al, Myers et al] VerilogCSP Verilog Programming Language Interface: very slow; cannot handle multichannel modules [Saifhashemi et al] Verilog macros are cumbersome and do not support extensions SystemVerilog (Superset of Verilog) Initial implementations promising but do not address extensions [Tiempo]
7 CSP Communication Channels Abstract communication between processes s:sender mid (CSP Channel) r:receiver ( ) ( ) SENDER = mid!v! SENDER RECEIVER = mid? x! RECEIVER No notion of hardware implementation details Semantics based on events on channels between independent processes [Hoare 04]
8 Outline Introduction Why asynchronous circuit design? Hardware description languages SystemVerilog Abstract Communication Basic Features Channels - Send, Receive Channel status and mixed-level simulation SystemVerilog Abstract Communication- Advanced Features Peek and Probe Split and synchronized communication One-to-many and one-to-any channels Results and Conclusion
9 Abstract SystemVerilog Channels Our approach Use SystemVerilog interface to abstract channel wires as well as Send/Receive tasks Abstract communication s:sender mid (SystemVerilog Interface) r:receiver module Sender (interface R);! parameter WIDTH = 8;! logic [WIDTH-1:0] v;! always! begin! v={$random()}%2**(width-1);! R.Send(v);! #10ns;! end! endmodule! module Receiver (interface L);! parameter WIDTH = 8;! logic [WIDTH-1:0] x;! always! begin! L.Receive(x);! #15ns;! end! endmodule!
10 Behind The Scenes: Channel Interface Channel details encapsulated within an Interface Implementation details (below) hidden from user Greatly simplifies debugging and evaluation of the design typedef enum {idle, r_pend, s_pend}!channelstatus;! typedef enum {P2PhaseBD, P4PhaseBD}!ChannelProtocol;!! interface Channel;!!parameter WIDTH = 8;!!parameter ChannelProtocol hsprotocol = P2PhaseBD;!!ChannelStatus status = idle;// Status of a channel!!logic req=0, ack=0;!// Handshaking signals!!logic hsphase=1;!// Used in two-phase!!!!!!// handshaking!!logic [WIDTH-1:0] data;!// Data being communicated! endinterface: Channel!
11 Interface Send and Receive Tasks task Send (input logic!!![width-1:0] d);!!begin!!!data = d;!!!req = 1;!!!status = s_pend;!!!wait (ack == 1 );!!!req = 0;!!!wait (ack == 0 );!!!status = idle;!!end! endtask!! Arbitrary handshaking protocol Support most commonly used task Receive(output logic![width-1:0] d);!!begin!!!status = r_pend;!!!wait (req == 1 );!!!d = data;!!!ack = 1;!!!wait (req == 0 );!!!ack = 0;!!!status = idle;!!!!end!! endtask! Send/Receive tasks are analogous to CSP s! (output) and? (input) Semantics are based on synchronization of concurrent processes using SystemVerilog s notion of update and evaluation events
12 Viewing Channel Status Enumerated types make viewing channel status inherent to all standard SystemVerilog simulators The designer can monitor if and what processes are engaged in the communication over time Status of channels as a waveform s:sender mid (SystemVerilog Interface) r:receiver
13 Supports Mixed-Levels of Abstraction Completed blocks can be simulated with others still at behavioral level Block1 Lreq Ldata Block2 C C PD CP Rack Rdata Block3 CD P Lack Rreq module mp_fb_csp (interface L, interface R); logic data; Gate-level always description High-level description of begin the buffer of the buffer L.Receive(data); (After (Before synthesis) synthesis) R.Send(data); end module mp_fb_gate (interface L, interface R);!! endmodule celement!ce(l.req, pd_bar, c);!! not!inv!(pd_bar, pd);! cap_pass!cp (c, L.ack, R.ack, pd, L.data, R.data);! endmodule!
14 Supports Design Verification Co-simulation: Implemented circuit vs. original circuit It is important to use the same Testbench Sometimes very complicated Verifies correct implementation No need for Shims [Saifhashemi 05] Testbench High Level Description Copy Merge & Compare Lreq Rack C Ldata C CP PD Rdata CD P Lack Rreq
15 Outline Introduction Why asynchronous circuit design? Hardware description languages SystemVerilog Abstract Communication Basic Features Channels - Send, Receive Channel status and mixed-level simulation SystemVerilog Abstract Communication- Advanced Features Peek and Probe Split and synchronized communication One-to-many and one-to-any channels Results and Conclusion
16 Peek and Probe Peek Sample data without committing to communication Probe Is the channel idle? Usually used for arbitration P task Peek (output logic[width-1:0] d);! wait (status == s_pend );! d = data;! endtask! P1 P2 Arbiter wait(ch0.status!=idle && ch1.status!= idle);! winner = Arbitrate (ch0.status, ch1.status);!! if(winner == 0)!!ch0.Receive(d);! if(winner ==1)!!ch1.Receive(d);! Q P3
17 Split Communication Handshaking of different channels might be interleaved in implementation Modeling interleaved behavior at high level is important for early system evaluation module buf (interface L, interface R); logic data; always begin L.Receive(data); R.Send(data); end module buf_split (interface L, interface R); logic data; always begin L.SplitReceive (data, 1); endmodule R.Send (data);! L.SplitReceive (data, 2); end endmodule
18 Synchronized Communications Sometimes implementation forces correlation of communication on multiple channels Synchronized start Synchronized finish Early performance evaluation of system requires modeling such behavior P1 P2 Concurrent body starts Acts like a barrier Adder P3 always!!begin!!!fork!!!!a.receive(a, 1);!!!!B.Receive(b, 1);!!!join!!!fork!!!!A.Receive(a, 2);!!!!B.Receive(b, 2);!!!join!!!sum = a + b ;!!!SUM.Send(sum);!!end!
19 One-To-Many Channels One sender to multiple receivers Option 1: Use a copy block Makes design cumbersome Option 2: Shared channels [JCSP, Welch et. al] Sender and receiver send and receive as if the channel is a normal one-to-one channel Top level module specifies the channel is broadcast Shared channels are closer to hardware implementation A shared data bus between sender and receivers Separate req and ack signals for receiving processes. P Copy Broadcast Channel Q1 Q2 Q3
20 One-To-Any Channel One sender to multiple receiver - JCSP [Welch et. al] Only one of the receiver participates in communication Q1 P Q2 task Receive(output logic[width-1:0] d);! status = r_pend;! Q3 wait (req == hsphase );! if (ONE2ANY)! req = 'z; // Inhibits! //other receivers! always! begin : main! wait (L.status!= idle);! randvalue = {$random()} % 3 ;! d = data;! if (randvalue ==1)! ack = hsphase;! status = idle;! endtask!! L.Receive(x);! else! begin! #0;! disable main;! end! end!
21 Outline Introduction Why asynchronous circuit design? Hardware description languages CSP Communication Channels SystemVerilog Abstract Communication Basic Features Channels - Send, Receive Channel status and mixed-level simulation SystemVerilog Abstract Communication- Advanced Features Peek and Probe Split and synchronized communication One-to-many and one-to-any channels Results and Conclusion
22 Results Simulation Run-Times Comparison to VerilogCSP [Saifhashemi 05] Simulation time of a linear pipeline with depth of 10 Platform: Sun UltraSPARC, Modelsim SE 6.6 simulator 12%-20% improvement Number of data items 100K 200K 300K 400K 500K Simulation time in Seconds (VerilogCSP) Simulation time in Seconds (SystemVerilogCSP) Ratio
23 Conclusions CSP-like communication and extensions can be modeled using SystemVerilog interfaces Features and advantages Ease of design: abstract communication, channel status Mixed asynchronous and synchronous designs can be modeled in same language and simulation environment Extensions: more accurate modeling of implemented hardware Make adoption of asynchronous technology easier Currently being used to teach the course EE-552 Asynchronous VLSI at the University of Southern California Future work Automated synthesis from SystemVerilogCSP
24 Supports Design Verification Testing DUT: Initially, modeled in SystemVerilogCSP Later implemented in gates It is important that Testbench does change Sometimes very complicated Communicates with other blocks Verifies correct implementation No need for Shims [Saifhashemi 05] Testbench should stay the same as DUT is implemented Testbench High Level Description Lreq Ldata Lack C C CD CP PD P Rack Rdata Rreq
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