BACKGROUND & TWI_CLKDIV

Transcription

1 BACKGROUND & TWI_CLKDIV I have one TS7500 and I2C sensors. The communication between TS7500 and sensors fail. I probed the i2c communication between the sensors and one Arduino and it was OK. This communication was in 11kbps min speed. I want get lower speed in the communication TS7500-sensors. Using this.pdf: CNS21XX-HRM-v.1.8.pdf The 146 page has TWI Time-Out reg: Where: [eq1] Insolating the variable: [eq2]

2 PERIPHERAL CLOCK(PCLK) The page 201 has the register to put PCLK value: System clock control register Where: If we choose CPU_PLL_Sel=0x0; FCLK_DIV=0x3; HCLK_DIV=0x3 we have that: Using eq2 we choose: We should have this speed: [eq2]

3 OTHERS REGISTERS TO CONSIDER From page 199:

4 From page200: Where PCLK_P2S_EN default =1 (PCLK TWI enable).

5 STEPS FOLLOWED FOR PROGRAM In first time i read the Clock gate control register 0 for AHB and APB devices, Clock gate control register 1 for AHB and APB devices and System clock control register. I use this function to access to registers: /* void *map_phys(off_t addr,int *fd): */ void *map_phys(off_t addr,int *fd) { off_t page; unsigned char *start; if (*fd == -1) //if fd it isnt -1,it was open *fd = open("/dev/mem", O_RDWR O_SYNC); if (*fd == -1) { perror("open(/dev/mem):"); //it isnt open ok return 0; } page = addr & 0xfffff000; start = mmap(0, getpagesize(), PROT_READ PROT_WRITE, MAP_SHARED, *fd, page); //start has the initial page direcction if (start == MAP_FAILED) { perror("mmap:"); return 0; } start = start + (addr & 0xfff); //now start has initial direccion + offset return start; } The TWI registers are since 0x direction. 102 page: So use the above function. reg_clk = map_phys(0x ,&fd_clk); //reg_clk[registroclk/sizeof(unsigned)] ya puede ser utilizado Now i read the registers: printf("register Clock gate control register 0 for AHB and APB devices = %X\n", reg_clk[0]); printf("register Clock gate control register 1 for AHB and APB devices = %X\n", reg_clk[0x4/sizeof(unsigned)]); printf("register System clock control register = %X\n", reg_clk[0])reg[0xc/sizeof(unsigned)]);

6 Results: Clock gate control register 0 for AHB and APB devices: 0x51F11003 Clock gate control register 1 for AHB and APB devices: 0x System clock control register: 0Xf9593 The default values are diferent from the values read. But PCLK is enable (ISNT IT???): De Clock gate control register 0 for AHB and APB devices: PCLK_NIC_EN=1; De Clock gate control register 1 for AHB and APB devices: PCLK_P2S_EN =1. De System clock control register : PCLK_DIV=1; NICCLK_Sel=1 (because HCLK<62.5MHz). In conclusion i have to change only the bits: 0, 1, 2, 3, 4 y 5 from System clock control register DUDE: DO I NEED MORE REGISTERS ENABLE FROM Clock gate control register 0 y 1 for AHB and APB devices? In second time i change PCLK y TWI_CLKDIV: void init_twi() { int TWI_CLKDIV=0; reg = map_phys(0x ,&fd); //reg[registrotwi/sizeof(unsigned)] it can use reg_clk = map_phys(0x ,&fd_clk); //reg_clk[registroclk/sizeof(unsigned)]it can use cavium_enable_twi(); } //reg_clk[0xc/sizeof(unsigned)]=0xf9593; //bydefult reg_clk[0xc/sizeof(unsigned)] = 0x3C; //CPU_PLL_SEL=0 -> PLL=175MHz; reg_clk[0xc/sizeof(unsigned)]&= (0x3C 0xFFFFC0);//FCLK_DIV=3 -> FCLK=175/4=43.75MHz //HCLK_DIV=3 -> HCLK=43.75/4= MHz //PCLK=HCLK/2= MHz TWI_CLKDIV=248; reg[0x4/sizeof(unsigned)] = (TWI_CLKDIV<<8); reg[0x4/sizeof(unsigned)] &= ((TWI_CLKDIV<<8) (0xFF)); reg[0x14/sizeof(unsigned)] = 3; //TWI_ACTDONE_FG y TWI_BUSERR_FG puestos a '0'

7 In last time i test it: int main(int argc,char *argv[]) { unsigned lectura=0; } init_twi(); //distv3 (sensor 1) write_twi_data(0x34,1,0x00); lectura=read_twi_data(0x34,4); //arduino use like a sensor (sensor2) write_twi_data(0x12,1,0xb3); lectura=read_twi_data(0x12,2); printf("lectura: 0x%X\n",lectura); cavium_disable_twi(); return 0;

8 RESULTS Distv3 sensor: Speed is not lowered and the data loss is evident. The speed is 128KBps is should be 11KBps.

9 Arduino sensor: Speed is not lowered and the data loss is evident. The speed communication is 128KBps it should be 11KBps. If Insolate PCLK from eq1: =61.5MHz. PCLK has not really changed.

10 CONCLUSIONS I think if I want lowered speed I need to enable some register that it isnt and I will can use System clock control register. The I2C speed before it s the same after that: Before (TWI_CLKDIV=511 y PCLK default): After (TWI_CLKDIV=511 y PCLK=5.4Mhz):

11 CPU_PLL_Sel=0x3; FCLK_DIV=0x0; HCLK_DIV=0x2 (when in first time they were readed): The next table its made with default PCLK, changing TWI_CLKDIV and measuring SCL frequency: It can be seen that the speed varies if it is changed TWI_CLKDIV. PCLK is 62.5MHz more or less.