UNIVERSITI MALAYSIA PERLIS

Transcription

1 UNIVERSITI MALAYSIA PERLIS SCHOOL OF COMPUTER & COMMUNICATIONS ENGINEERING EKT 124 LABORATORY MODULE INTRODUCTION TO QUARTUS II DESIGN SOFTWARE

2 : INTRODUCTION TO QUARTUS II DESIGN SOFTWARE OBJECTIVES To introduce Altera s Quartus II software as a CAD tool to create logic circuits. To analyze the waveforms simulated and develop truth tables from the analysis. EQUIPMENTS/COMPONENTS Computer Unit Altera Quartus II software INTRODUCTIONS Basic logic gate elements and some basic design circuits have been introduced in lecture sessions. As the fundamental point in the process of digital designs, logic gates are required to be used in their hundreds and even thousands for building up into sophisticated designs as demonstrated nowadays. Building these gates will produce CPLDs (Complex Programmable Logic Devices), PLAs (Programmable Logic Arrays), PALs (Programmable Array Logics) and FPGAs (Field Programmable Gate Arrays). But in order to design complex circuits, CAD tools are needed in order to reduce research and development costs. This lab experiment will introduce the procedures on how to perform basic tasks using one particular software, namely the Altera Quartus II. In this experiment also, you will construct the circuit of the following basic gates in Quartus II and acquire their particular output signals through simulation technique. 1

3 Pre-Laboratory Preparation Create a new folder in Drive D (or E). Name your folder using your Student Matric Number. PROCEDURE Part A: Initialization A schematic circuit design built in Quartus II requires a project name. Each time you begin with a new design, you will need to initiate and define a new project. A1. Open the Altera Quartus II software. You will see a main menu bar at the top of the screen with names similar to those found in most Windows -based programs. There are also other additional menu names for Altera Quartus II design aids. A2. Select File New Project Wizard Then, the New Project Wizard: Introduction dialog box will appear. This step-by-step wizard will help you to initialize the basic requirement for your coming new project. Click Next to continue to page 1 of 5. 2

4 A3. Page 1 of 5 in the New Project Wizard requests your working project folder, project name and top-level design entity name. Fill in the required fields as in the following figure. You will notice that when you type the project name, the entity name will follow what you have written. This only happens when no toplevel entity name is filled. Click next to page 2 of 5 once finished filling the fields. Working directory folder : D:\Student_Matric_Number\Tutorial Project name : Basic_gates Top-level entity name : Basic_gates A4. If you have not created the required folder to store your project, a pop-up window will appear for confirmation. Click Yes to proceed, and Quartus II will automatically generate the required folder and directory. 3

5 A5. Page 2 of 5 inquires whether other existing design files (schematics, hdls or blocks) are needed to be inserted into your new project. For the meantime, no files are needed. Therefore, you may proceed to page 3 of 5 by clicking Next. A6. Page 3 of 5 inquires the type of programmable chip (device) for the project to perform on. These devices are grouped in different families and each families have its own models with different characteristics. Successful projects can be downloaded onto the device for applications. You will understand more about these devices at a later stage. For the meantime, set your device to: Family : Cyclone II Model : EP2C35F672C6 Click next to continue to page 4 of 5. 4

6 A7. Page 4 of 5 inquires for any third party EDA tools to be added together for your project. In advance designs, industry-standard EDA tools are very important for design entries, synthesis, simulation and timing analysis. Quartus II provides bridges with third party elements to help strengthen the design environment. For the meantime, no EDA tools are required. You may click Next to proceed to page 5 of 5. A8. Finally, page 5 of 5 summarizes all your settings from page 1 to 4. Click Finish to end this wizard. 5

7 Part B: Design Entry Once the new project wizard finalizes your project properties, you can now begin to design your project such as creating schematic circuits, simulation waveforms and so on. Follow the given step-by-step procedures to create the schematic circuit of your basic gates. Your first tutorial exercise is to construct the circuit for the basic gates as in figure below: Creating your schematic file and importing components. B1. To begin your design, select File New [Ctrl + N]. The New pop-up window will appear inquiring the type of new file to create. Select Block Diagram / Schematic File and click OK. A blank Block1.bdf file will be spread out onto your Quartus II window for your schematic design. 6

8 B2. Adding components onto your schematic spreadsheet is called editing. To edit, right click on the spreadsheet and select Insert Symbol. A Symbol pop-up window will appear. Expand the library to show the list of logic gates. Logic library is found under primitives section. B3. The first logic gate to be used is the 2-input AND gate. The library name for this gate is called and2. Browse for and2 and you will see the graphic symbol on the right when you highlight the name and2. Click OK to select this symbol. Place the symbol anywhere on your spreadsheet. B4. Do the same as in Step B3 above to get the following logic gates: (a) 2-input OR gate (1 unit) (b) Inverter (1 unit) (c) 2-input NAND gate (1 unit) (d) 2-input NOR gate (1 unit) (e) Exclusive-OR gate (1 unit) (f) Exclusive-NOR gate (1 unit) CAUTION: Position your components so that the border does not overlap with each other No overlapping 7

9 B5. Each gates require input and output symbols. Therefore, it is necessary to apply input and output symbols, which represents the input and output ports of your circuit. In the Symbol window, the input and output symbols are categorized under library primitives pin. Since each gate (except inverter) have 2 inputs to be shared named A and B, hence only 2 input ports are required. However, each gate has its own output, which is not shared among each other. In total, 7 output ports will be needed for the circuit. Now, insert the input and output symbols on your spreadsheet. B6. Rename one input symbol to A, while the other input symbol to B. Rename your output symbols to AND, OR, NOT, NAND, NOR, XOR and XNOR. All the gates must be connected to the input and output symbols. Each gate has its own input and output nodes or terminals. Basically, the input nodes are on the left side of the symbol and the output nodes are on the right side. When positioning the mouse pointer (arrow) near a node, the arrow will change to a cross with wiring icon. This will allow the nodes to be connected with wires to other symbols. Connecting symbol nodes with wires. B7. Go to the left side of your AND gate symbol. There are two (2) input nodes. Point your mouse on the top node. When the pointer changes to a cross, click and drag outward. A line (wire) will appear coming from this node. Connect this wire to your input A node. Wire the lower node to input B. Finally, on the right side of the AND symbol, wire the single node to the output AND. Complete AND gate connection as illustrated below: B8. Continue to make wire connections for the remaining logic gates. All logic gates need A and B input wires (except inverter as only input A is needed) and separate output wires connected to the output symbols, respectively. 8

10 B9. Once done, save this spreadsheet by selecting File Save As. A pop-up window will appear to save your spreadsheet. The name Basic_gates will automatically appear as the name of your block diagram filename (in *.bdf format). Make sure that the Add file to current project is ticked. * Note* You can save your file anytime throughout this tutorial exercise. The earlier you save your project, the safer it is to keep your diagram updated and prevent you from starting all over if any computer malfunction such as hanging or not responding happens that may force you to reboot and restart the Quartus II software. B10. You should have created your basic gates diagram similarly like in the figure below: 9

11 After building the circuit, you will need processing modules so that: (a) The overall design has no violation or component and management errors (b) Logic design is minimized and other important files are generated (c) Device routing placement is successful (d) Programming files to the device are generated (e) Timing debugs are validated These processing modules can either come all in one or can be achieved separately. These tasks are known as a compilation process. Compilation process will cover Analysis & Synthesis, Fitter, Assembler and Classic Timing Analyzer. Remember, compilation does not check your operational design, it only checks overall design management. Performing a Compilation process B11. To compile your design, select Processing Start Compilation [Ctrl+L]. Quartus II will automatically begin the compilation process and check for overall errors, debug the system for timing and arrange your project to be fitted into the selected device. B12. A pop-up window will appear to report whether a successful or not successful has been achieved. Click OK. (For not successful compilation, double-click on the errors to locate the position of the failure.) Basically, you can download the program generated by the compiler onto a device without needing to perform simulation unless you are not sure whether your circuit performs the required operation. To be on the safe end, simulating your design to see whether the outputs are correct is always the wisest choice for confirming your operation. Performing a Simulation process B13. To simulate your design, you must first create the waveform file. To do this, select File New. The same New pop-up window will appear. This time, go to Verification/Debugging Files tab, and select University Program VWF. Click OK. A blank waveform1.vwf editor file will be spread out in Quartus II. 10

12 B14. Some pre-settings are needed for better viewing. First is to set the end time of the waveform to only ns. Select Edit Set End Time for the End Time popup window to appear. Type at the Time field and select ns. Click OK. Second is to set the grid interval for each transition. To set this, select Edit Grid Size for the Grid Size pop-up window to appear. In the Period field, type 50.0 and select ns. Click OK. B15. Save the file first before proceeding to the next step. Save As the file using name Basic_gates (in *.vwf format). Next, for better view, select View Fit in Window to display the entire range from 0.0ns to 400.0ns with a 50.0ns grid interval. B16. To insert the input and output nodes of your circuit design, select Edit Insert Insert Node or Bus A pop-up window will appear. Click on Node Finder The Node Finder pop-up window appears. At the Filter field, select Pins: all available from the drop down menu list. Click on the List tab. The list of all available pins will be displayed in the Nodes Found section. 11

13 B17. To select which pins to be put onto the waveform, you must transfer your selection from the Nodes Found field into the Selected Nodes field. In this case, all input and output pins must be chosen. Transfer all pins from the Nodes Found field to Selected Nodes field. B18. Click OK at the Node Finder window. Click OK again at the Insert Node or Bus window. The selected input and output pins will appear at the waveform editor file. By default, input nodes will have a value of logic 0 all along the timeframe, whereas the output pins will have an unknown logic value X. You can select your input and output pins and rearrange them in order of your preference. Figure below shows the best possible position. * Note* Notice how the symbol of the A and B input pins are looked like compared with an output pin symbol. 12

14 As you understand, to examine the behaviour of an output, the inputs must be set to a certain value. Apart from logic 0 applied to A and B input along the timeframe, these input pins must also show other values so that outputs can be fully generated when simulation is started. n inputs will have 2 n states, therefore, 2 inputs will have 2 2 = 4 states Input Output A B NOT AND OR NAND NOR XOR XNOR Setting the values on the inputs. B19. To assign logic 1 for input A, click and drag at time 200.0ns to 400.0ns. The selected area will be highlighted. Select Edit Value Forcing High (1) and the selected area will then has a value of logic 1. *Note* To easily highlight the waveforms, adjust the snap to grid format so that when you click and drag an area, the selected area will snap to grid. Use the Edit Snap to Grid function. 13

15 B20. Apply the same method in step B19 for input B at time interval: a. 100ns ~ 200ns b. 300ns ~ 400ns B21. Save your file settings when all input test patterns is made. To perform the simulation, select Simulation Run Functional Simulation. B22. When the simulation is done, another pop-up window of Simulation Waveform Editor will appear. You may now observe the waveform which you have just simulated. Part C: Creating Symbols Circuit designs can be very large at times. When adding a circuit onto another circuit project, the designs may become very confusing. To reduce the complications, add-on circuits can be reduced in size by just creating their symbols and adding onto another circuit design. C1. To create a default symbol for your schematic design, first you must make sure that the Basic_gates.bdf window is the active window. Select File Create/Update Create Symbol Files for Current File. A pop-up window will appear. Click on the Save button to save your design into a symbol file name Basic_gates.bsf. Next, click OK to continue. 14

16 C2. Open a new Block Diagram / Schematic file and select Edit Insert Symbol. You will now see a new library called Project. Expand this library and click on Basic_gates. The preview symbol will display on the right side. C3. Click OK and paste anywhere on your blank spreadsheet. The circuit Basic_gates now has its own symbol for use in another schematic project. Double click the symbol and you will see the contents of this symbol. 15

17 IMPORTANT NOTES 1. Always create a new folder for every new schematic project and place the folder under your D:\Student_Matric_Number directory folder. 2. At this stage, always use the New Project Wizard everytime you wish to create a new schematic circuit. When your new project requires an existing schematic file, you can use the add files on page 2 of 5 in the wizard to initiate your new project. 3. Save your project as frequently as possible to prevent from starting all over if the computer suddenly crashes and needs to reboot. 4. Understand that the commands used in this tutorial also have shortcut keys, and icons in toolboxes to help quicken and ease to design. Do not limit the usage of the commands alone but try to explore the icons and short keys available in Quartus II. 5. Practice with Quartus II as much as possible to understand the procedures of developing your projects. 16

18 EXERCISE a) Create a new folder name Lab1a in your D:\Student_Matric_Number. Evaluate the following Truth Table by constructing the schematic and generating the simulation waveform. INPUT OUTPUT A3 A2 A1 A0 B3 B2 B1 B b) Create a new folder name Lab1b in your D:\Student_Matric_Number. Find the output X and show the simulation waveform. c) Simulate the following circuit and show the simulation waveform. 17