WAVE GENERATION DESIGN using the ATLYS FPGA with INBUILD DSP/RAM

Transcription

1 All rights reserved & copyright PETER-PAUL TROENDLE 26 RUE DE VILLEBON SAULX LES CHARTREUX WAVE GENERATION DESIGN using the ATLYS FPGA with INBUILD DSP/RAM

2 Architecture The limit, gain, phase and frequency are defined on 32 bits aswell as the sweep values corresponding. They are programmed streamingwhise using UART (see Appendix E showing the setup for almost error free UART with1.8 MBaud). Note: the UDP also worked with 1500 byte packets send with 1Gbs, it was seen that a stream with unlimited size could be send with 500Mb/s using the Ethernet UDP protocoll The changes that are coded can be monitored on a VESA, VGA or HDMI screen giving a confortable user interface where the programming of the sequences can be practiced in real time (see Appendix F) Spur We use 2^16 point waves defined with an adjustable gain to have the spur better than 96bB (see Appendix A), that is also complemented by limit clamps Jitter The frequency is accurate up to 0.01 Hz as we define the frequency angle aswell as the phase very accurately (see Appendix A), For comparison, Agilent J-BERT N4903A is offering the frequency accuracy ppm, but with the deviation of 0.5% Chirp All parameters can be dynamically in transition with values increasing or decresasing according to the sweep parameters (In Appendix B you can see both the gain and frequency where it was applied) Accuracy The output is generated with 12.8Gbs (400MHz and 32 bits wide) and its monitored internally by the same rate (see Appendix D). Glitches <2.5nS are captured and visible with no noize, as the block <1mm away, within the same FPGA. For comparison we send the output to an Analog Device AD9122 DAC 1230MS/s and observed on a Lecroy 10Gbs (see Appendix C). Where it is unclear if the glitches where picked up by the anolgue set up or if they where observed. The system uses a 5 stage pipeline that can handle at any time an external trigger that will be implemented wihthin 12.5nS (5x 2.5nS) For comparaison the J-BERT N4903A Agilent the output is 12.5Gbs and there is a delay between trigger and data output of 32nS Bandwidth The waves can be generated with very low frequencies Hz as the sequences can be defined with nested loops for any duration. The highest frequency achieved using the Spartan 6 is 200MHz on only one channel. Using several channels in parallel, i.e. 5, we would achieve 1GHz or more.

3 Programming 1. Dual Port 400 MHz RAM, running with 2 half cycles, one for write and one for read, allowing the value read to be writen in next pr previous half cycle. This allows self increment and self decrementing of the values. 2. The Wave RAM is 32 bit wide, with selctable sectors allowing for any segment to be reprogrammed while executing the other. 3. The Instruction RAM is 256 bits deep and it feeds the instruction bus 288 bits wide running at 57Gbs (200MHz with parallel 9 x 32bit values: the control, the 4 parameters (gain, frequ, lim and phase) and 4 sweep values. 4. The Sweep top bit is the polarity if it is up or down counting, its also using the allows auto increment and auto decrementing. 5. The control bits specify the jump address, the current repeat value and the initial number of repeats. Normal instructions have the jump value set to zero and are simply followed by the next instruction. The Jump value is otherwise auto decremented for the nested loop condition, this allows for illimited nested loops.. 6. The 2 control bits specify the Wave RAM address upper bits, to select different banks. 7. The On the fly mode for instructions that do not reset the angle at wich the wave is playing, is specified by one control bit too. 8. Then for the Oscilloscope function, 4 bits select the different timescales for capture. 9. The oscilloscope RAM is 32bit wide and running at ful speed (400MHz) yielding captures at 12.8Gbs 10.Selectable inputs from Ethernet UDP/UART, outputs in parallel on the monitor (HDMI, VESA or VGA), to the UART and in the final model would also be given to the DAC

4 Memory Map 16 bits Oscilloscope READ ONLY 14 bits address (40.9uS capture) x 32 bit 400 MHz (12.8Gbs) 16Ksamples 00 Wave 16Ksamples 00 BANK: Sinus 4Ksamples 12 bits address x 32 bit values 01 BANK: Ramp 4Ksamples 12 bits address x 32 bit values 10 BANK: Exponent 4Ksamples 12 bits address x 32 bit values 11 BANK: Harmonics 4Ksamples 12 bits address x 32 bit values 11 Parallel Instructions 262Kbit 00 Gain 10 bits address x 128 bit values 01 Limit 10 bits address x 128 bit values 10 Phase 10 bits address x 128 bit values 11 Frequency 10 bits address x 128 bit values

5 Parallel Instructions 128 bits VALUE VARIATION CURRENT VALUE CONTROL [128:96]these 32 bits determines the initial VALUE for the DSP function used (Gain, Limit, Phase or Frequency). When the instruction is finished to be played and before the New Instruction comes in, CURRENT VALUE <= VALUE, this allows one instruction to be replayed as often as required [95:64]these 32 bits determines the amount the usual value auto increments or decrements, depending on the MSB, the computed value updates the CURRENT VALUE [63:32]these 32 bits determines the CURRENT VALUE for the DSP function used (Gain, Limit, Phase or Frequency) [31:0] with REPEAT, CURR. REPEAT, JUMP, BANK SEL, INIT, CONDITIONS REPEAT CURRENT REPEAT JUMP BANK SELECT INIT [31:24]these 8 bits determines how often the instruction must be played before the next consecutive one is selected (by the address auto increment) [23:16]these 8 bits are counting how often this instruction was allready played, when it is CURRENT REPEAT = REPEAT then the Signaling of a New Instruction is given and it updates the DDS and CURRENT VALUE aswell as CURRENT REPEAT <= 0, so next time used the instruction count is starting fresh [15:6] 10 bits. When a CONDITION is Triggering, the next instruction is the JUMP address, but the current REPEAT value is stored so the number of JUMPS is counted [5:4] 2 bits.determines which Wave will be played from the Wave Memory [3] 1 bit. continues from the previous Dynamic Values or Initialises them (DDS Angle, CURRENT VALUE AND CURRENT REPEAT) If 1: the Dynamic Values are NOT touched: the next instruction is executed ON THE FLY If 0: the Dynamic Values are Initialised CONDITIONS [2:0]. 000 ZERO CROSS DDS angle =0, used to play exactly N cycles, PLL LIMIT + active, can be used to adjust the gain automatically 010 LIMIT - active, can be used to adjust the gain automatically 011 EXT input, can be used for calibrating (Gain, frequency, PLL..) 100 ETHERNET UDP Single Shot - Trigger 111 NESTED LOOP the next instruction is always the JUMP addr.

6 RAM Pipeline The 400 MHz clock is halved into 200MHz (W), this controls the 2 stage pipeline: One cycle (W = 1) for RX inward data updates and one cycle (W = 0) with Normal R/W operation DSP Cycle o o o Normal R/W operation for DSP The RAM is used with write First Mode to allow the intruction read out to affect the next Program Counter (PC) value. Its using the CURRENT REPEAT value. Additionally its writes the next CURRENT VALUE for Chirp/ Sweep Rx Cycle o o o RX inward data is written any locations of any RAM can be selected to updating it a 16 bit global address is used with the top bit sthat select the RAM chosen 400 MHz DSP RX DSP RX DSP RX DSP RX DSP RX DSP RX DSP RX DSP RX W DSP RX When updating the CURRENT REPEAT/VALUE, we see that it I done within th clock cycle, so the next value is taking effect immediately one the next clock cycle The RAM s are running on 400 Mhz, but the System on the 200 MHz System clock (W) The Multiplyier cannot run much faster than 200 MHz, so we use the RAM 2 nd cysle for independent Writes, and use the RAM as pseudo DUAL PORT. We generate it using an inverter, that makes the transition W rising edge a bit delayed to the clock

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8 Datapath DSP

9 Datapath Instructions

10 Dynamic Instructions Registers The Data instruction from the RAM selected is modified for the 2 following fields, these are the Dynamic Instruction Register: CURRENT VALUE REGISTER, CURRENT REPEAT REGISTER, The DDS (Phase generator) 1. DDS DYNAMIC ANGLE The LAST Instruction implements the INIT DDS RESET All next instruction uses the same DDS Angle except if any of the instructions is nearly to change, on LAST occurrence if its INIT is set, then the synchronous reset of the DDS will be activated, calling for a reset on the next cycle where the NEW instruction comes in, both new instruction and reset then having the same latency of one additionnal cycle then. Otherwise the Angle will continue unaffected ON THE FLY 2. DYNAMIC INSTRUCTION VALUE (FOR CHIRP OR SWEEP) VARIABLE [31] NEW CURRENT VALUE REG + VARIABLE[30:0] CURRENT VALUE REG - VARIABLE[30:0] 0 1 NEW VALUE FROM RAM 0 CURRENT VALUE REG # 11 All next instruction causes the VALUE to be used as start CURRENT VALUE 3. DYNAMIC INSTRUCTION REPEAT (FOR LOOP, WHILE or DELAY) This is counting how often the instruction still need to be executed, the instruction uses the JUMP address the number of times specified by REPEAT: - per ex. for a DELAY in terms of how often it is REPEATED - In the case of a LOOP (NESTED bit is set) - or WHILE (other CONDITIONS) NEW NESTED LOOP NEW RAM CURRENT REPEAT FROM 1 0 CURRENT REPEAT REG # RX DATA 1 0 CURRENT REPEAT REG + 1 All next instruction causes the REPEAT current value to be reset, except when a CONDITION forces a Nested Loop JUMP, then the current value is kept for next time

11 Programming 11.Reading and writing the RAM for the Waves, for the Instructions and the Oscilloscope. 12.Switch between flat sinus, ramp, exponential and sinus with custom harmonics, update of a wave during operation 13.update of an instruction during operation, with a control bit to allow the modification to be on the fly with no angle reset. 14.Sweep on minutes/hours/days etc.. using the nested loop feature 15.Selecting different points of obeservation and scales with the internal Oscilloscope. UART output file visualised with Excel for full accurate values of each points on the graph (allowing for calculations etc..), direct HDMI/VGA output for visual monitoring and a 50Mbps DAC to output real waves as example (normally bit DAC running on 200MSps would be required) 16.UART or Ethernet UDP input 17.The external interrupt could be done inputting a trigger wave with a ADC and one would monitor the zero crossing and cause a sweep of the phase to lock on the main wave (synchronisation)

12 APPENDIX A APPENDIX B

13 APPENDIX C APPENDIX D

14 APPENDIX E

15 APPENDIX F