Avnet S6LX16 Evaluation Board and Maxim DAC/ADC FMC Module Reference Design

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1 Avnet S6LX16 Evaluation Board and Maxim DAC/ADC FMC Module Reference Design By Nasser Poureh, Avnet Technical Marketing Manager Mohammad Qazi, Maxim Application Engineer, SP&C Version 1.0 August 2010

2 1 Introduction This document describes a MicroBlaze embedded reference design using the Avnet S6LX16 evaluation board along with the Maxim DAC/ADC FMC module. This reference design shows how the MAX5135 DAC devices on the Maxim FMC module can be used to generate Sine waves, feed these Sine waves into the input of the MAX11040 and MAX11612 ADC devices on the Maxim FMC module using a loopback cable, sample the ADC data, and display the data using the ChipScope Pro Bus Plot feature. 2 Reference Design Requirements This reference design will require the following software and hardware setups. 2.1 Software The software requirements for this reference design are: WindowsXP Xilinx ISE Hardware The hardware setup for this reference design is: Computer with 1 GB RAM and 1 GB virtual memory (recommended) Avnet S6LX16 Evaluation board Maxim MAXSPCSPARTAN6+ Evaluation Kit Power supply JTAG programming cable (USB or PC4) Mini USB cable 3 Reference Design Block Diagram The following figure shows a high-level block diagram of the reference design. The reference design consists of the following major blocks: MicroBlaze Processor 32KB of BRAM for the processor code and data I2C and SPI Interfaces to the Maxim DAC/ADC FMC module 2KB of BRAM Buffer for MAX11040 ADC 2KB of BRAM Buffer for MAX11612 ADC Custom IP GPIO interface to the Maxim DAC/ADC FMC module Interrupt Controller RS232 Port Microprocessor Debug Module (MDM) JTAG connection 1

3 JTAG Header BRAM Controller BRAM (32K) BRAM Controller MicroBlaze Processor Core MDM Interrupt Controller PLB MAX11040 ADC Data Buffer GPIO GPIO MAX11612 ADC Data Buffer UART Data_Ready Data_Ready BRAM Controller Dual-Port BRAM (2K) Addr Custom IP Custom IP Addr Dual-Port BRAM (2K) BRAM Controller Data Data ChipScope Pro Cores RS232 Connector I2C FPGA SPI GPIO DRDYOUT FMC LPC Connector Maxim DAC/ADC FMC Module Figure 1 Reference Design Block Diagram 2

4 3.1 Maxim DAC/ADC FMC Module Interface A high-level block diagram of the Maxim DAC/ADC FMC module (Maxim MAXSPCSPARTAN6+ Evaluation Kit) is shown in the following figure. This module interfaces to the Avnet S6LX16 evaluation board via the FMC LPC connector and provides two low-speed DAC and ADC interfaces. The DAC interfaces are provided by two MAX5135 devices while the MAX11040 and MAX11612 devices provide the ADC interfaces. The SPI interface over the FMC LPC connector is used to interface to the MAX11040 and MAX5135 devices while the I2C interface over this connector is used to access the MAX11612 ADC device. FMC_SCLK FMC_MOSI FMC_MISO FMC_CS_MAX11040 FMC_CS_MAX5135 FMC_DRDYOUT FMC_OVERFLOW 2.5V/3.3V Level Translators MAX11040 ADC AD-[0:3] AD+[0:3] J3 Connector FMC LPC Connector MAX5135 DAC DA[4:7] FMC_SCL FMC_SDA 2.5V/5.0V Level Translators MAX5135 DAC MAX11612 ADC DA[0:3] AD[0:3] J2 Connector Figure 2 Maxim DAC/ADC FMC Module Block Diagram 3

5 3.2 MAX11040 and MAX11612 ADC Data Buffer Blocks These two blocks store the captured ADC data from the MAX11040 and MAX11612 ADC devices. In the case of the MAX11612 device, software reads the data over the I2C bus while SPI bus is used to read the data from the MAX11040 device. In either case, software writes this data to a 2KB dual-port BRAM (2KB for each, the MAX11040 and the MAX11612 device) until the buffer is full. Once the buffer is full, software will write to a single-bit GPIO port to set the Data_Ready signal active for each ADC device. At this time the data can be read from the second port of the dual-port BRAM by the Custom IP. SPI GPIO DRDYOUT FMC LPC Connector MAX11040 ADC BRAM Controller MAX11040 ADC Data Buffer Dual-Port BRAM (2K) Addr Data MicroBlaze Processor Core GPIO GPIO MAX11612 ADC Data Buffer Data_Ready Data_Ready Custom IP Custom IP Addr Dual-Port BRAM (2K) Data ChipScope Pro Cores BRAM Controller I2C FMC LPC Connector MAX11612 ADC Figure 3 - MAX11040 and MAX11612 ADC Data Buffers 4

6 3.3 ChipScope Pro Interface The ChipScope Pro is used to display the data read from the MAX11040 and MAX11612 ADC devices. Upon activation of the Data_Ready signal by software, the Custom IP will read the data from the second port of the 2KB dual-port BRAM at 50MHz speed and sends the data to the ChipScope Pro ILA core. ChipScope will use the Data_Ready signal as a trigger to display the data using the ChipScope Pro Bus Plot feature. 4 Demo Software The demo software uses the MAX5135 DAC devices to generate two Sine waves. The Sine waves are fed into the input of the MAX11040 and MAX11612 ADC devices on the Maxim FMC module using a loop-back cable, the ADC data is sampled by software, and displayed using the ChipScope Pro Bus Plot feature. The following figure describes the flow of program execution. Start Init Interrupt Controller Init Spi Driver Init UartLite Driver Init Gpio Driver Init I2C Driver Configure MAX11040 (Config Reg = 0x38) (DRC Reg = 0x4000) Wait for the MAX11040 DRDYOUT signal Read Data from MAX11040 over SPI and Write the Data to the MAX11040 Data Buffer in FPGA Write MAX11612 Setup Byte (0xD2) Write MAX11612 Config Byte (0x61) Read Data from MAX11612 over I2C and Write the Data to the MAX11612 Data Buffer in FPGA Write to DAC output register from Sine-Wave Look-up table 5

7 4.1 Generating Sine Wave by MAX5135 DAC MAX5135 is a SPI TM based 12-bit DAC, which can be connected in cascaded configuration as the two MAX5135 DAC devices are on the Maxim MAXSPCSPARTAN6+ FMC module. Each DAC has four output channels and provides buffered voltage-output. MAX5135 can use a precision internal reference or a precision external reference for rail-to-rail operation. In this application we are using internal reference which is 2.4V and therefore, the output-voltage range is set to 0-2.4V. A Sine wave look-up table is used to send data to DAC at 1ksps that yields a Sine wave with frequency of 8.6Hz. The formula for generating Sine wave look-up table is given below: where: (((Sine(2* *i/n))+1)/n) * N-1) n = Number of Sample Points i = 0 n N = 2^Number of DAC bits In this case, we ve taken n = 128 samples therefore, i = Since MAX5135 is a 12-bit ADC therefore, N = Any spreadsheet software can be used to generate the look-up table. The results of spreadsheet calculator should be rounded off to zero to make them integer. Once the look-up table is generated, data can be fed to a DAC particular output. The data byte is always preceded by a control byte that contains the command and the channel address. In this case, control byte = 0x31 for channel 1output. Please refer to Table 1 in MAX5135 Datasheet for more details. The data byte should always be shifted 4 bits towards left before writing to MAX5135 input register, as MAX5135 is a 12-bit left aligned DAC and is software-compatible to 16-bit versions. 4.2 Data Sampling by MAX11040 MAX11040 is a 24-bit, 4-channel true-differential, simultaneous sampling, Sigma-Delta ADC. This ADC is also SPI TM compatible and provides data rates of up to 64ksps. The ADC has internal reference of 2.5V and full-scale input range of ±2.2V. This ADC needs some configuration to start sampling. Please refer to Table-2 in MAX11040 Datasheet for details on Configuration Registers. In this case, ADC Configuration Register is written with 0x38 that enables 24-Bit operation and internal oscillator and disables the fault-protection circuitry. The Data-Rate configuration register is written with 0x4000 for 1ksps data conversion. Once the configuration is done, sampling will start and DRDYOUT signal goes low indicating data 6

8 is ready for output. A SPI TM based data read will make DRDYOUT high again and ADC will keep on sampling at the configured intervals. 4.3 Data Sampling by MAX11612 MAX11612 is a 12-bit, 4-Channel, Low SAR ADC. It is I 2 C compatible ADC with 4.096V internal reference and V full-scale input range. The ADC needs to be configured before every sample. That configuration includes writing the appropriate value to Setup Register and Configuration Register. Since ADC needs a very small conversion time (7.5µs) therefore, data can be sampled after a small delay. In this case, MAX11612 Setup Register is written with 0xD2 that enables writing to Setup Register and selects internal reference of 4.096V. Please refer to Table-1 and Table-6 in MAX11612 datasheet for more details. The Configuration Register is written with 0x61 that selects Channel 0 only in Single Ended configuration. Please refer Table-2, Table-3 and Table-5 in MAX11612 datasheet for more details. 7

9 5 Demo Setup Please perform the following steps to setup the hardware. 5.1 Maxim DAC/ADC FMC Module 1. Plug the Maxim FMC module into the FMC slot of the S6LX16 evaluation board. 2. Install jumpers on pins 2-3 of J6 and J7 located on the FMC module. 3. Connect pin 3 of the J2 connector to the pin 9 of the J3 connector on the FMC module. This will connect the AD0- input channel of the MAX11040 ADC device to ground. 4. Connect pin 4 of the J2 connector to the pin 10 of the J3 connector on the FMC module. This will connect the DA0 output of the first MAX5135 DAC device to the AD0+ input of the MAX11040 ADC device (DAC to ADC loop-back). 5. Connect pin 12 of the J2 connector to the pin 12 of the J3 connector on the FMC module. This will connect the DA4 output of the second MAX5135 DAC device to the AD0 input of the MAX11612 ADC device (DAC to ADC loop-back). 5.2 Avnet S6LX16 Evaluation Board 1. Install a jumper on JP1. 2. Install a jumper on JP2, JP3, JP6, JP7, JP8, JP18 and JP19 pins Connect the JTAG cable to J4 and the USB port of the PC. 4. Connect the mini USB cable to P1 and the USB port of the PC. 5. Connect power supply to J2. 6. Slide the SW1 power switch to the ON position. Maxim DAC/ADC FMC Module (MAXSPCSPARTAN6+) J2 Connector J3 Connector FMC LPC Connector S6LX16 Evaluation Board 8

10 6 Quick Demo Run 1. Start ChipScope Pro Analyzer via Start > All Programs > Xilinx ISE Design Suite 12.2 > ChipScope Pro >Analyzer. 2. Click on the Open Cable button as shown in the following figure. 3. When the following dialog box appears, click OK to continue. 4. Right-click on DEV:0 MYDevice0(XC6SLX16) and then select Configure. 9

$Browse to the \Demo_bit_file_and_chipscope_project folder of the reference design and double-click on download.bit file. c.$ Click OK to continue. The S6 FPGA will be configured and you should see the following in the ChipScope project window.

Click OK to continue. The S6 FPGA will be configured and you should see the following in the ChipScope project window.

11 5. In the following dialog box, a. Click on Select New File b. Browse to the \Demo_bit_file_and_chipscope_project folder of the reference design and double-click on download.bit file. c. Click OK to continue. The S6 FPGA will be configured and you should see the following in the ChipScope project window. You should also see the Overflow LED blinking on the Maxim DAC/ADC FMC module (the reason for the Overflow LED blinking will be covered later). If this LED is not blinking, please reset the S6LX16 evaluation board using the SW2 push button switch. 10

$\Demo_bit_file_and_chipscope_project folder$

12 6. Select File > Open Project from the ChipScope Pro GUI. 7. When the following dialog box appears, click No to continue. 8. Browse to the \Demo_bit_file_and_chipscope_project folder of the reference design and double-click on the maxim_dac_adc_fmc.cpj file. 11

The ChipScope Pro GUI should look as shown below for the

Click in Apply Settings and Arm Trigger button as shown in

ChipScope Pro is set to trigger when the

13 The ChipScope Pro GUI should look as shown below for the Avnet S6LX16 evaluation board. 9. Click in Apply Settings and Arm Trigger button as shown in the following figure. ChipScope Pro is set to trigger when the MAX11612_Data_Ready and MAX11040_Data_Ready signals are high. 10. Zoom in the Waveform Window to view the MAX11040 and MAX11612 ADC data. 12

14 11. Click on the Bus Plot as shown in the following figure. You should see the MAX11612 data being plotted as shown in the following figure (indicating that the DAC Sine wave output being connected to the input of the MAX11612 device). 13

15 12. Un-check the MAX11612_Data box and check the MAX11040_Data box to view the plot for the MAX11040 ADC device as shown in the following figure. The MAX5135 DAC output connected to the input of the MAX11040 ADC device can be as high as 2.4V. Since the MAX11040 internal reference voltage is 2.2V you will see clipping of the MAX11040 data as shown in the following figure. This is also the reason for the Overflow LED blinking on the FMC module. Note: The internal reference voltage of the MAX11612 ADC device is 4.096V and that s why there was no clipping on the MAX11612 data as shown in the previous figure. This concludes the demo portion of this document. For information on how to build this reference design and re-generate a bit file, please follow the steps shown below. 14

7 Implementing the Reference Design The following sections describe how to re-build the hardware platform, generate a bit file, and download the bit file to the Avnet board. 7.

16 7 Implementing the Reference Design The following sections describe how to re-build the hardware platform, generate a bit file, and download the bit file to the Avnet board. 7.1 Reference Design XPS Project Start the XPS tool via Start > All Programs > Xilinx ISE Design Suite 12.2 > EDK > Xilinx Platform Studio. Open the XPS project in EDK (the project file is located in the /Maxim_FMC_HW folder of the reference design). The XPS GUI should look as shown in the following figure. 15

implement the design and export it to SDK). 7.

17 Select Project > Export Hardware Design to SDK from the XPS GUI. When the following dialog box appears, click on Export Only to continue (this will take a few minutes as the XPS tool will implement the design and export it to SDK). 7.2 Reference Design SDK Project Start the SDK tool via Start > All Programs > Xilinx ISE Design Suite 12.2 > EDK > Xilinx Software Development Kit. When the following dialog box appears, browse to the /Maxim_FMC_SW folder of the reference design and click OK to continue. 16

18 The SDK GUI should look as shown in the following figure. 7.3 Downloading the Demo Bit File to the Board Select Xilinx Tools > Program FPGA from the SDK GUI. 17

19 Under the Software Configuration, select the /dac_adc_loopback_0.elf file. Click Program to configure the FPGA. Follow the Quick Demo Run steps as stated earlier, but skip the bit file download in ChipScope since the bit file is already downloaded to the board in SDK. 18

Spartan-6 LX9 MicroBoard Embedded Tutorial. Tutorial 5 Embedded Chipscope Debugging

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