Trends in Digital Interfaces for High-Speed ADCs

Transcription

1 Trends in Digital Interfaces for High-Speed ADCs Robbie Shergill National Semiconductor Corp. INTRODUCTION The analog-to-digital converter is a critical component in many of the most demanding applications in the world today. From cost-sensitive consumer products such as scanners to many types of industrial imaging products to ultra-high speed defense communications, you will find an analog-to-digital converter lurking in there. In many of these applications the A-to-D can be the determining factor in the price-performance tradeoff. Thus, optimization of this component's functionality is very important. The speed-resolution progression of the ADC technology is a well-established trend that goes back decades - back to the early days of the integrated circuits industry. Ever greater sampling rates at all levels of resolution, and greater resolutions at a given sampling rate, are a reality of this technology. At this time, the mainstream, cost-effective ADCs from major manufacturers are achieving performance levels shown in Table 1. These are advertised products that are either in or about to go into full production. Of course, the next generation of these products is already working in our labs as we speak. Sampling Rate (Fs) 8-bit 10-bit 12-bit 14-bit 16-bit Fs >= 1 Gs/s 500Ms/s =< Fs < 1Gs/s 200Ms/s =< Fs <500Ms/s 100Ms/s =< Fs < 200Ms/s 50Ms/s =< Fs < 100Ms/s Table 1: State of commercially available ADCs in late-2004 Recently another trend has made an appearance in this field. Certain applications that run multiple signal paths in parallel have driven the ADC manufacturers to integrate multiple ADC channels in one IC. Medical imaging has been the driving application and

2 12-bit Quad ADCs in the 40Ms/s to 65Ms/s range have been the result (an octal integration in one vendor's case). As a result, the total throughput through a highresolution ADC IC has taken a sudden jump. With a conventional parallel CMOS interface it would mean 48 data signal pins on such a Quad ADC chip - with 4 additional clock signals on top of that. The problem is lot worse on the ASIC or the FPGA end of the interface where an imaging system may be using 64 or 128 such channels. TIME FOR SOME NEW THINKING Until now, the digital data interface has been the most overlooked aspect of an ADC or DAC chip design. The main challenges in converter design have always been in the analog side of the chip. In fact, when the conversion speed became too fast for the standard CMOS parallel interface, as has been the case for the ultra-high-speed 8-bit converters shown in Table 1, we just de-multiplexed the parallel data by a factor of 2 or more and just burned more pins. This approach simply won't work for higher resolutions and in the cases where multiple ADC cores are integrated into one chip. The immediate solution has been to serialize the digital data words in the simplest manner. This means that just the data words are serialized and a serial bit-rate clock and a Frame signal are provided to latch and deserialize the data stream at the receiver end. This is shown in Figure 1. Current spate of 12-bit Quad or Octal ADCs from various vendors follow this scheme - which is often referred to as CDF for Clock-Data-Frame. The benefit is obvious - National's Quad 12-bit 65 Ms/s chip implements the digital interface with just 12 signals instead of the 52 previously mentioned. Interface power consumption is also reduced by close to 2/3. Each serial data channel runs at up to 780 Mbps (65Ms/s x 12) using LVDS differential signaling. N-bit ADC Core N Parallel-to-Serial SDATA Data Word (N bits) SCLK PLL & Timing N x CKs FRAME CKs Figure 1: The Clock-Data-Frame (CDF) Serialization Scheme

3 The CDF scheme works quite well for the ADCs and DACs in the 40 Ms/s to 100 Ms/s range, depending upon the resolution of the converter. The limit of this technique comes from the clock-to-data skew. Current FPGA LVDS I/O technology limits the maximum serial rate of this scheme to about 850 Mbps. Future FPGA technologies may allow this interface to operate up to 1 Gbps. It should also be kept in mind that the width of the interface also limits the maximum speed since the clock-to-data skew is the limiting factor. OPTIONS FOR GOING FASTER Figure 2 shows the magnitude of ADC throughput we have to transfer across this interface and how the problem is getting worse as we go forward. Clearly the CDF scheme will not take us very far. What are the options? Thruput (Gbits/sec) Quad Dual Single 5 3 Progression of Technology 2 1 Approximate Limit of CDF 8-bit 10-bit 12-bit 14-bit 16-bit Resolution (also # parallel data signals) Figure 2: Per-converter throughput requirements of today's high-speed ADCs a) Extend CDF: This is the simplest next step. Just as with ultra-high speed 8-bit converters we demux the parallel data bus, we could employ 2, or even 3, serial data streams (lanes) in the CDF scheme. This has the obvious drawback of additional pins and

4 it will also have lower per-signal speed limit than the single-lane scheme due to the greater skew; but it retains the simplicity of implementation. Standard ASIC/FPGA I/Os could still be used - thus giving the system engineer the lowest cost alternative. b) Available SERDES I/Os: Advanced FPGA and ASIC families have SERDES (Serializer-Deserializer) cells available that can operate in the 2.5 to little over Gbps range. These cells were originally developed for communications applications - such as, Ethernet. Recently the basic PLLs and encoders/decoders of these cells have been pressed into other applications as well - such as PCI-Express and Serial-ATA. All of these SERDES cells support the IBM 8B10B code and some support the 64B66B code as well. Because of their wide availability, these SERDES cells are an obvious alternative that must be considered. c) Other SERDES methods: Other SERDES schemes are also possible that would give a simpler, more optimal solution than the Comm-type SERDES mentioned above. For example, National has had a serialization solution available for many years that is designed to simply embed the clock and frame in the transmitter and then recover the same with a relatively simpler PLL implementation in the receiver. Figure 3 shows one such implementation. In this case, each 16-bit data word is turned into an 18-bit code word that is serially transmitted on the medium. The 2 added bits cost 12.5% in overhead but they provide a simple, repetitive clock/frame signal for the receiver. N-bit ADC Core N Embed Clock/Frame N+2 Parallel-to-Serial Serial Data (N+2) x CKs PLL & Timing CKs N=16 example Serial Data D0 0 1 D15 D0 0 1 D15 Embedded Clock/Frame Embedded Clock/Frame Figure 3: National's Embedded-Clock/Frame Scheme

5 Another key issue to resolve is that of the electrical interface. Most current CDF implementations have used LVDS. This is because of its proven reliability and wide availability. At least one vendor has used the JEDEC SLVS electrical interface. This is a relatively new specification that is not yet widely adopted. Standard LVDS, as specified by ANSI/EIA/TIA , was originally intended for connection amongst equipment so its maximum transfer rate is determined by the cable length. In a board level application LVDS can approach speeds of 1.5 Gbps. Since the signal strength of the standard LVDS is not necessary for this chip-to-chip application, some of it can be traded for higher speed. However, this would require some level of standardization of such a low-swing, lower-common-mode implementation. The SERDES I/O cells offered by all the FPGA and ASIC vendors use the CML interface. CML is a generic term and not a standard per se. This, along with the fact that CML interface's voltage levels are referenced to the power supply, causes many system implementations to use ac-coupling with CML in order to deal with different common-mode requirements of the transmitter and the receiver. Table 2 compares some key characteristics of these electrical interfaces and Figure 4 shows the interconnect topology. Parameter LVDS SLVS CML* Transmit amplitude (diff. p-p) V 0.8 V nominal V Transmit common-mode voltage ** V 0.2 V nominal V Receive amplitude (diff. p-p) V 0.32 V min V Receive common-mode range ** V V V Medium Cable Not spec'd FR-4 Distance several meters Not spec'd ~ 8" * CML specification based on OIF SXI-5 spec. ** Common-mode voltage defined as ((V+) + (V-)) / 2; except the Receive Common-mode Range for SLVS which is the single-ended voltage range of each signal. Table 2: Key electrical specs of candidate interfaces

6 Vdd-t Vdd-r D+ Tx Zt = 2Zo Rx D- LVDS Vdd-t Vdd-r D+ Tx Rx D- SLVS Vdd-t Vtt Vdd-r D+ Tx Rx D- CML Figure 4: Comparison of interconnect topologies UNIQUE REQUIREMENTS OF THIS APPLICATION In defining a new serial interface for the ADCs and DACs, certain unique requirements of this application must be kept in mind. a) As evident from Figure 2, a wide range of data word widths (converter resolution) and sampling rates must be accommodated.

7 b) High-speed, high-resolution converter chips are highly sensitive to noise. The serial interface, operating at multi-gigabit/sec speeds, can easily add enough noise to materially reduce the converter's dynamic performance specifications. One thing that can reduce the added noise is if the serial interface rate is not allowed to be a fractional multiple of the converter's sampling rate. c) The data stream in many ADC/DAC applications is continuous. The interface must not require control constructs that interrupt the data stream under normal conditions. d) Any self-clocking serial interface will introduce a certain amount of latency variation to the datapath. This is because of the clock recovery and resynchronization that must take place in the receiver. The interface must make provisions for dealing with this latency. WHERE DO WE GO FROM HERE? At this writing, there is an active effort underway to define a standard serial interface for high-speed ADC and DAC interconnects. Almost all major data converter vendors are participating in this effort. A key determinant of success for this group would be to have broad support for its chosen solution from converter as well as ASIC/FPGA vendors. To this end, it is important to leverage the technologies that are already wellsupported. This means that the standard scheme should utilize the 8B10B type SERDES cells that are widely supported by the ASIC and FPGA vendors. Same argument also applies to CML electrical interface. However, it must be recognized that the typical 8B10B SERDES would produce a relatively inefficient solution for this problem. ASIC/FPGA SERDES cells were originally developed for communication applications where the data is packetized and carried over a constant frequency interconnect. Trying to fit the multitude of converter resolution and speed combinations into an 8B10B-coded stream would yield high overhead for many of those combinations. This, of course, would lead to higher power and noise - two things the converter designers want the least. The simpler embeddedcontrol/frame SERDES would yield a more efficient solution. But this option presents a greater standardization challenge. No matter how the SERDES-based standardization proceeds, the de-facto CDF and its multi-lane variant scheme will also live on because in many cases they will provide the system designer with the lowest-cost solution. In conclusion, system designers utilizing high-speed, high-resolution data converters should expect to start working with serial interfaces in the near future.