Lecture #12 Structural VHDL Modeling
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1 Spring 2015 Ahmad El-Banna Benha University Faculty of Engineering at Shoubra ECE-322 Electronic Circuits (B) Lecture #12 Structural VHDL Modeling Instructor: Dr. Ahmad El-Banna
2 Agenda Modeling the Structure way Structural Example Behavioral & Structural Example Elec. Cts B, Lec#12, Spring 2015 Ahmad El-Banna 2
3 Modeling the Structurural way Structural architecture implements the module as a composition of subsystems contains signal declarations, for internal interconnections the entity ports are also treated as signals component instances instances of previously declared entity/architecture pairs port maps in component instances connect signals to component ports 3
4 Structural way Example Not complete example, just for concept justification.. bit0 d0 q0 d1 bit1 q1 d2 bit2 q2 Elec. Cts B, Lec#12, Spring 2015 Ahmad El-Banna d3 bit3 q3 en gate and2 a y b int_ 4
5 Structural way.. First declare D-latch and and-gate entities and architectures entity is port ( d, : in bit; q : out bit ); end entity ; architecture basic of is begin process (, d) begin if = 1 then q <= d after 2 ns; end if; end process; end basic; entity and2 is port ( a, b : in bit; y : out bit ); end entity and2; architecture basic of and2 is begin process (a, b) begin y <= a and b after 2 ns; end process ; end basic; Elec. Cts B, Lec#12, Spring 2015 Ahmad El-Banna 5
6 Structural way... Declare corresponding components in register architecture body architecture struct of reg4 is... component port ( d, : in bit; q : out bit ); end component; component and2 port ( a, b : in bit; y : out bit ); end component; signal int_ : bit; 6
7 Structural way... Now use them to implement the register d0 d1 d2 bit0 bit1 bit2 q0 q1 q2... begin bit0 : port map ( d0, int_, q0 ); bit1 : port map ( d1, int_, q1 ); bit2 : port map ( d2, int_, q2 ); Elec. Cts B, Lec#12, Spring 2015 Ahmad El-Banna d3 en gate and2 a y b int_ bit3 q3 bit3 : port map ( d3, int_, q3 ); gate : and2 port map ( en,, int_ ); end struct; 7
8 Trace the code & Draw the model structure 8
9 Trace the code & Draw the model structure.. 9
10 Trace the code & Draw the model structure.. the model Simulation waveform 10
11 Mixed Behavior and Structure An architecture can contain both behavioral and structural parts process statements and component instances collectively called concurrent statements processes can read and assign to signals Example: register-transfer-level (RTL) Model data path described structurally control section described behaviorally 11
12 Mixed Example Not complete example, just for concept justification.. multiplier multiplicand shift_reg control_ section shift_ adder reg product 12
13 Mixed Example entity multiplier is port (, reset : in bit; multiplicand, multiplier : in integer; product : out integer ); end multiplier; architecture mixed of mulitplier is begin signal partial_product, full_product : integer; signal arith_control, result_en, mult_bit, mult_load : bit; arith_unit : entity work.shift_adder(behavior) port map ( addend => multiplicand, augend => full_product, sum => partial_product, add_control => arith_control ); result : entity work.reg(behavior) port map ( d => partial_product, q => full_product, en => result_en, reset => reset );... Elec. Cts B, Lec#12, Spring 2015 Ahmad El-Banna 13
14 Mixed Example.. multiplier_sr : entity work.shift_reg(behavior) port map ( d => multiplier, q => mult_bit, load => mult_load, => ); product <= full_product; process (, reset) -- variable declarations for control_section -- begin -- sequential statements to assign values to control signals -- end process; end mixed; 14
15 Elec. Cts B, Lec#12, Spring 2015 Ahmad El-Banna For more details, refer to: VHDL Tutorial: Learn by Example by Weijun Zhang VHDL GUIDELINES FOR SYNTHESIS Introduction to VHDL presentation by Dr. Adnan Shaout, The University of Michigan-Dearborn The VHDL Cookbook, Peter J. Ashenden, 1 st edition, The lecture is available online at: For inquires, send to: ahmad.elbanna@feng.bu.edu.eg 15
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