Guidelines for Laboratory Sessions:

Transcription

1 University of Malta Faculty of Engineering Department of Electronic Systems Engineering Hardware Description Languages ELE 3103 Lecturer: Dr. Ivan Grech Laboratory Tutors: Dr. Edward Gatt Mr. Owen Casha Mr. Mark Bonnici Assessment: 60 % Examination 40 % Assignment Tutorial Sheet (15%) & Project (25%) Guidelines for Laboratory Sessions: 1. For the first laboratory session the student is required to bring along the walkthrough provided with this bundle and a softcopy of the sample code including the test bench. 2. It is important that the student provides a means to store his work as a softcopy e.g. pendrive, floppy disk etc. 3. Any preparatory work related to the assignments should be done before entering the lab sessions. No student will be allowed to enter the lab session without the requested work. 4. The assignment is divided into two parts: Tutorial Sheet: Project: o Carries 15% of laboratory work assessment o Includes short tasks to be solved by a VHDL code so that each student can capture good VHDL programming skills both behavioral and structural VHDL. o Students should deliver for each question preparation, code(s), test-benches, waveforms, results and any comments where applicable. o Carries the remaining 25% of laboratory work assessment o Includes a problem to be solved by a VHDL code and its aim is to test the skills acquired by students from the Tutorial Sheet. o Students should deliver a report which includes the following preparation, code(s), test-benches, waveforms, results and any comments where applicable. 5. The deliverables should be presented during an interview conducted by the laboratory tutors. The schedule for the interviews will be communicated later on. Hardware Description Languages ELE

2 Modelsim Walkthrough Design of a Simple ALU The following diagram shows the basic steps for simulating a design in Modelsim. Creating the working library In Modelsim, all designs, be they VHDL, Verilog, or a combination of the two, are compiled into a library. You typically start a new simulation in Modelsim by creating a working library called "work". "Work" is the library name used by the compiler as the default destination for compiled design units. Compiling your design After creating the working library, you compile your design units into it. The Modelsim library format is compatible across all supported platforms. You can simulate your design on any platform without having to recompile your design. Running the simulation With the design compiled, you invoke the simulator on a top-level module (Verilog) or a configuration or entity/architecture pair (VHDL). Assuming the design loads successfully, the simulation time is set to zero, and you enter a run command to begin simulation. Step 1: Creating a new Project. 1. Start Modelsim. 2. Create a new project. Select Create a Project from the Welcome dialog or File > New >Project (Main window) from the menu bar. This opens a dialog where you enter a Project Name, Project Location (i.e., directory), and Default Library Name. The default library is where compiled design units will reside. Type test in the Project Name field. Click Browse to select a directory where the project file will be stored. Leave the Default Library Name set to work. Click ok Hardware Description Languages ELE

3 Step 2: Adding items to the project Once you click OK to accept the new project settings, you will see a blank Project tab in the workspace area of the Main window and the Add items to the Project dialog will appear. From this dialog you can create a new design file, add an existing file, add a folder for organization purposes, or create a simulation configuration. Creating new files: In this walkthrough you will need two files: one for the VHDL code of the ALU and another for the test benches. Click Create New File. Click Browse. Write the file name you wish to give to file e.g. alu.vhd Click Open and then OK Repeat for any other files e.g. alu_tb.vhd and alu_tl.vhd These two files are attached to this walk-through. Hardware Description Languages ELE

4 Adding existing files: Click Add Existing File. Click Browse. Open the examples directory in your ModelSim installation tree Select alu.vhd, alu_tb.vhd and alu_tl.vhd Click Open and then OK You should now see two files listed in the Project tab of the Main window workspace. Question mark icons (?) in the Status column mean the file hasn t been compiled or the source file has changed since the last successful compile. The other columns identify file type (e.g., Verilog or VHDL), compilation order, and modified date. Changing compile order (VHDL) Compilation order is important in VHDL designs. Follow these steps to change compilation order within a project. Select Compile > Compile Order. Click the Auto Generate button. ModelSim "determines" the compile order by making multiple passes over the files. It starts compiling from the top; if a file fails to compile due to dependencies, it moves that file to the bottom and then recompiles it after compiling the rest of the files. It continues in this manner until all files compile successfully or until a file(s) can t be compiled for reasons other than dependency. Alternatively, you can select a file and use the Move Up and Move Down buttons to put the files in the correct order. Hardware Description Languages ELE

5 Step 3: Simulation Configurations A Simulation Configuration associates a design unit(s) and its simulation options. For example, say every time you load alu_tl.vhd you want to set the simulator resolution to nanoseconds (ns) and enable event order hazard checking. Ordinarily you would have to specify those options each time you load the design. With a Simulation Configuration, you specify options for a design and then save a "configuration" that associates the design and its options. The configuration is then listed in the Project tab and you can double-click it to load alu.vhd along with its options. Create a new Simulation Configuration: Select File > Add to Project > Simulation Configuration. Type alu in the Simulation Configuration Name field Select Top Level from the Place in Folder drop-down Click the + icon next to the work library and select alu_tl. Click the Resolution drop-down and select ns Click Ok The Project tab now shows a Simulation Configuration named alu. Step 4: Load the Simulation Configuration. Double-click the alu Simulation Configuration in the Project tab. In the Transcript pane of the Main window, the vsim (the ModelSim simulator) invocation shows the -t ps switches. These are the command-line equivalents of the options you specified in the Simulate dialog. Hardware Description Languages ELE

6 Step 5: Running Simulation Enter Simulation time in space allocated: e.g. 160 ns Select Simulate > Run > Restart Select Simulate > Run-All Step 6: Wave Window The Wave window allows you to view the results of your simulation as HDL waveforms and their values. The Wave window is divided into a number of window panes. All window panes in the Wave window can be resized by clicking and dragging the bar between any two panes. Adding items to the Wave window ModelSim offers several methods for adding items to the Wave window. In this exercise, you ll try out different methods. 1. Add items using drag-and-drop. You can drag an item to the Wave window from many other windows (e.g., Main, Signals, and Variables). Drag an instance from the sim tab of the Main window to the Wave. Drag a signal from the Signals window to the Wave window. In the Wave window, select Edit > Select All and then Edit > Delete. Hardware Description Languages ELE

7 2. Add items using a command. Type add wave * at the VSIM> prompt. ModelSim adds all items from the current region. Run the simulation for awhile so you can see waveforms. Using cursors in the Wave window Cursors mark simulation time in the Wave window. When ModelSim first draws the Wave window, it places one cursor at time zero. Clicking anywhere in the waveform pane brings that cursor to the mouse location. You can also add additional cursors; name, lock, and delete cursors; use cursors to measure time interval; and use cursors to find transitions. Working with a single cursor Position the cursor by clicking and dragging. Click the Select Mode icon on the Wave window toolbar. Click anywhere in the waveform pane. A cursor is inserted at the time where you clicked Drag the cursor and observe the value pane. The signal values change as you move the cursor. This is perhaps the easiest way to examine the value of a signal at a particular time. d In the waveform pane, drag the cursor to the right of a transition with the mouse positioned over a waveform. The cursor "snaps" to the transition. Cursors "snap" to a waveform edge if you click or drag a cursor to within ten pixels of a waveform edge. You can set the snap distance in the Window Preferences dialog (select Tools > Window Preferences). In the cursor pane, drag the cursor to the right of a transition. The cursor doesn t snap to a transition if you drag in the cursor pane. Hardware Description Languages ELE

8 VHDL Code for clk, reset Project : Simple Reset Author : Owen Casha Date : 10/10/ Company : UOM File : system.vhd Design : Walkthrough library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_misc.all; use IEEE.std_logic_unsigned.all; entity SYSTEM is port ( ); end SYSTEM; reset : out bit ; clk : out bit architecture SYSTEM_arch of SYSTEM is begin SIGNAL reset : bit := '1'; SIGNAL clk : bit; CONSTANT clk_pd CONSTANT reset_pd : time := 100 ns; --clock period : time := 200 ns; --reset period BEGIN clock generator clock_driver : PROCESS BEGIN clk <= '0'; WAIT FOR clk_pd / 2; LOOP clk <= '1', '0' AFTER clk_pd / 2; WAIT FOR clk_pd; END LOOP; END PROCESS; reset driver reset <= '0' after reset_pd; END SYSTEM_arch Hardware Description Languages ELE

9 VHDL Code for ALU Project : Simple Arithmetic Logic Unit Author : Owen Casha Date : 10/10/ Company : UOM File : alu.vhd Design : Walkthrough library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_misc.all; use IEEE.std_logic_unsigned.all; entity ALU is port ( Accumulator_in: in STD_LOGIC_VECTOR (7 downto 0); Data_in : in STD_LOGIC_VECTOR (7 downto 0); Opcode_in : in STD_LOGIC_VECTOR (3 downto 0); Result_out : out STD_LOGIC_VECTOR (7 downto 0) ); end ALU; architecture ALU_arch of ALU is begin Main: process(accumulator_in,opcode_in, Data_in) begin case Opcode_in is when "0000" => Result_out <= Data_in; -- result = Data_in when "0001"=> Result_out <= Accumulator_in; -- result = accumulator_in when "0010"=> Result_out <= " "; -- result = accumulator_in + Data_in when "0011"=> Result_out <= " "; -- result = accumulator_in - Data_in when "0100"=> Result_out <= Accumulator_in and Data_in; -- result = accumulator_in and Data_in when "0101"=> Result_out <= Accumulator_in or Data_in; -- result = accumulator_in or Data_in when "0110"=> Result_out <= Accumulator_in xor Data_in; -- result = accumulator_in xor Data_in when "0111"=> Result_out <= not(accumulator_in); -- result = not(accumulator_in) when "1000"=> Result_out <= not(accumulator_in); -- result = not(data_in); when "1001"=> Result_out <= " "; -- result = 0 when "1010"=> Result_out <= " "; -- result = 8 LSBs of ( accumulator_in * Data_in) when "1011"=> Result_out <= " "; -- result = 8 MSBs of ( accumulator_in * Data_in) when "1100"=> Result_out <= accumulator_in nand Data_in; -- result = accumulator_in nand Data_in when "1101"=> Result_out <= accumulator_in nor Data_in; -- result = accumulator_in nor Data_in when "1110"=> Result_out <= accumulator_in xnor Data_in; --result=accumulator_in xnor Data_in when "1111"=> Result_out <= " "; --result=accumulator_in+1 when others => Result_out <="XXXXXXXX"; end case; end process Main; end ALU_arch; Hardware Description Languages ELE

10 Test Bench for ALU Project : Simple Arithmetic Logic Unit Author : Owen Casha Date : 10/10/ Company : UOM File : alu_tb.vhd Design : Walkthrough library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_misc.all; use IEEE.std_logic_unsigned.all; entity alu_tb is port ( ); end alu_tb; Accumulator_out: out std_logic_vector (8 downto 1); Data_out : out std_logic_vector (8 downto 1); Opcode_out : out std_logic_vector (4 downto 1) architecture alu_tb_arch of alu_tb is begin operation_1: PROCESS begin wait for 0ns; Opcode_out <= "0000"; wait for 10 ns; Opcode_out <= "0001"; wait for 10 ns; Opcode_out <= "0010"; wait for 10 ns; Opcode_out <= "0011"; wait for 10 ns; Opcode_out <= "0100"; wait for 10 ns; Opcode_out <= "0101"; wait for 10 ns; Opcode_out <= "0110"; wait for 10 ns; Opcode_out <= "0111"; wait for 10 ns; Opcode_out <= "1000"; wait for 10 ns; Opcode_out <= "1001"; wait for 10 ns; Opcode_out <= "1010"; wait for 10 ns; Opcode_out <= "1011"; wait for 10 ns; Opcode_out <= "1100"; wait for 10 ns; Opcode_out <= "1101"; wait for 10 ns; Opcode_out <= "1110"; wait for 10 ns; Opcode_out <= "1111"; wait; end PROCESS operation_1; operation_2: PROCESS begin wait for 0ns; Data_out <= " "; wait; end PROCESS operation_2; operation_3: PROCESS begin wait for 0ns; Accumulator_out <= " "; wait; end PROCESS operation_3; end alu_tb_arch; Hardware Description Languages ELE

11 Top Level for ALU Project : Simple Arithmetic Logic Unit Author : Owen Casha Date : 10/10/ Company : UOM File : alu_tl.vhd Design : Walkthrough library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_misc.all; use IEEE.std_logic_unsigned.all; entity alu_tl is port ( Result : out std_logic_vector (8 downto 1) ); end alu_tl; architecture alu_tl_arch of alu_tl is component alu port ( Accumulator_in: in std_logic_vector (8 downto 1); Data_in: in std_logic_vector (8 downto 1); Opcode_in: in std_logic_vector (4 downto 1); Result_out: out std_logic_vector (8 downto 1) ); end component ; component alu_tb is port ( Accumulator_out: out std_logic_vector (8 downto 1); Data_out: out std_logic_vector (8 downto 1); Opcode_out: out std_logic_vector (4 downto 1) ); end component; signal Accumulator : std_logic_vector(8 downto 1); signal Data : std_logic_vector(8 downto 1); signal Opcode : std_logic_vector(4 downto 1); begin alu_1 : alu port map ( Accumulator_in => Accumulator, Data_in => Data, Opcode_in => Opcode, Result_out => Result ); tb_1 : alu_tb port map ( Accumulator_out => Accumulator, Data_out => Data, Opcode_out => Opcode ); end alu_tl_arch; Hardware Description Languages ELE

12 VHDL Coding style 1. VHDL directory format The following table is the recommended way to organize your project. Each project should be placed in a separate directory. Project directory Sub directories Description title doc Place any documentation here rtl synth testbench work Place vhdl files here Place synthesis script here Place simulation test files here Work directory for modelsim 2. VHDL file name description Project name File name Description title entity_name.vhd One architecture and one entity entity_name_arch.vhd One architecture entity_name_ent.vhd One entity entity_name_cfg.vhd One configuration entity_name_pkg.vhd Package entity_name_tb.vhd Test bench Rule: A VHDL file and the entity it contains have the same name. 3. VHDL signal naming convention Signal name _in _out _io _reg _lat _clk _rst _n _async Description Input signal Output signal Inout signal Output Signal of a flipflop Output signal of a latch Clock signal reset_signal Negative logic signal Asynchronous signal Hardware Description Languages ELE

13 4. VHDL File header Every VHDL file starts with standard header: -- Project : project or course name -- Author : Mark Bonnici -- Date : 01 jan Company : File : RISC1.vhd -- Design : Course exercise 1 --Description : RISC1 top module --Changes : 5. Architecture Architecture should be one of the following: name Description BEHAVIORAL implies physical logic, does not compiler with rtl tools RTL Implies physical logic, compiler with rtl tools STRUCTURAL GATE SIMULATION TESTBENCH Implies physical connections, but not any logic Gate level netlist Simulation model Test bench model 6. Code Appearance I.1 -VHDL code must be indented. Use three spaces for indentation. I.2 -The maximum length of lines is 80. I.3 - place each port on a different line. I.4 -Use lower case I.5 -Align the colons in the entity port. I.6 -Add a short comment to each port I.7 -Add other comments as necessary to make your code more readable and understandable. Example -- Project : project or course name -- Author : -- Date : -- Company : File : async_dff.vhd -- Design : Course exercise 1 --Description : asynchronous d type fliflop --Changes : --entity of asynchronous d flpflop Hardware Description Languages ELE

14 ENTITY async_dff is PORT ( async_rst : in std_logic; --asynchronous reset clk : in std_logic; --system clock d_in : in std_logic; --data input q_reg_out : out std_logic; --data output end async_dff; --architecture of asynchronous d flpflop architecture behav of async_dff is begin process (clk, async_rst) begin if (async_rst = '1') then q_reg_out <= '0'; elsif (clk'event and clk = '1') then q_reg_out <= d_in; end if; end process; end behav; Hardware Description Languages ELE

15 Hardware Description Languages ELE 3103 Tutorial Sheet Note: Any preparatory work related to the tutorial sheet should be done before entering the lab sessions. No student will be allowed to enter the lab session without the requested work. Question 1 Design a VHDL code to control the enable of a pump which fills a water tank. As shown in the figure 1 below the inputs to the controller are X and Y which are fed from two sensors connected to the water tank. The controller should issue a pump enable signal E. Note that X, Y and E are 1 bit signals. Figure 1 Water Tank System (WTS) You should assume that the sensor gives a logic high signal in presence of water. The controller should be designed in a way to enable the pump ONLY when the water level falls below the lower limit Y and switches off ONLY when the water level has risen beyond the upper limit X. Note that the controller should be synchronized to a clock and should have an asynchronous reset. Preparation: State Diagram, Implementation Code, Testing Sequence Question 2 Figure 2 Sequence Detector Design a sequential logic circuit using VHDL which can detect an input sequence of 110. Data (din) is fed serially in on every clock cycle. As soon as it detects a correct sequence, an output alert (sync_out) is issued and it will restart scanning the input for another correct sequence. Your answer should include a minimized state diagram and an appropriate test bench. Note that din and sync_out are 1 bit signals. Preparation: State Diagram, Implementation Code, Testing Sequence Question 3 (a) Describe a BCD to seven segment display decoder as a VHDL code. The value assigned to the output vector is to be determined according to Figure 3, where a should be placed as the MSB of your output vector. Figure 3 Seven Segment Display (b) Design a counter with the following specifications: Hardware Description Languages ELE

16 4 bit output BCD/binary counter Carry output signals Asynchronous Reset Synchronous Pre-Programming capability of the output value. Functional description: Figure 4 4-bit Output Counter When async_rst =1, cntr_out is resetted to zero. When pdata_en = 1, cntr_out is set to pdata_in in the next clock cycle. When cntr_en = 1, then cntr_out is incremented on every clock cycle. In BCD mode (bcd_mode = 1), the counter cycles from 0 to 9 In Binary mode (bcd_mode = 0), the counter cycles from 0 to 15 (c) Connect the blocks designed in parts (a) and (b) in a structural VHDL architecture and perform adequate testing. Figure 5 Counter with 7-segment display driver Preparation: Implementation Codes, Testing Sequences Hardware Description Languages ELE

17 Hardware Description Languages ELE 3103 Project Note: Any preparatory work related to the project should be done before entering the lab sessions. No student will be allowed to enter the lab session without the requested work. Aim: Implementation of an Integer Multiplier using VHDL To implement a sequential algorithm for multiplication of positive integer using a hardware description language. Theory: Integer Multiplication Algorithm The block diagram in Figure 1 shows the hardware arrangement for sequential multiplication. This circuit performs multiplication by using a single n-bit adder n times to implement the spatial addition performed in the standard long multiplication of numbers. Registers A and Q combined hold the i th partial product while multiplier bit qi generates the Add/NoAdd signal. If q i = 1 then Add else NoAdd. This signal controls the addition of the multiplicand M to the i th partial product to generate the i+1 th partial product. The product is computed in n cycles. The partial product grows in length by one bit per cycle from the initial vector PP0, of n zeros in register A. The carry-out from the adder is stored in flip-flop C. At the beginning, the multiplier is loaded into register Q, the multiplicand into register M, while C and A are cleared to 0. At the end of each cycle, C, A and Q are shifted right one bit position to allow for growth of the partial product as the multiplier is shifted out of register Q. After n cycles the higher-order half of the product is held in A and the low-order half is in register Q. Figure 1 Sequential Multiplier Hardware Description Languages ELE

18 Preparation 1. Work out the following using the above algorithm on a paper: x showing the contents of the respective registers after each cycle. 2. Identify using either a descriptive or pictorial approach, the minimum number of sub-systems required to implement the algorithms, giving the input, output and processing requirements of each block. Assume that the algorithm implementations will be capable of handling 4-bit integer numbers. Implementation Multiplier Figure 2 Input/Output Requirements of Multiplier When mult_start signal is enabled for one clock cycle, the multiplier load the multiplicand_in and multiplier_in in the respective registers and starts the operation. An output signal mult_ready will show when the result is ready. Describe the multiplier algorithm with a VHDL code. Remember to use structural VHDL in case you need to connect together the required sub-systems. Produce the required test benches to test your implementation. Use the examples given in part 1 of preparation to verify correct operation. Finally implement the multiplier algorithm on the Spartan-3 FPGA available in the HDL laboratory. Hardware Description Languages ELE