Overview of SOC Architecture design

Transcription

1 Computer Architectures Overview of SOC Architecture design Tien-Fu Chen National Chung Cheng Univ. SOC - 0 SOC design Issues SOC architecture Reconfigurable System-level Programmable processors Low-level reconfiguration On-chip bus Embedded Software Issues SOC - 1

2 Embedded Systems vs. General Purpose Computing - 1 Embedded System General purpose computing Runs a few applications often knownatdesigntime Not end-user programmable Operates in fixed run-time constraints, additional performance may not be useful/valuable Intended to run a fully general set of applications End-user programmable Faster is always better SOC - 2 Embedded Systems vs. General Purpose Computing - 2 Embedded System General purpose computing Differentiating features: power cost speed (must be predictable) CPU output analog input analog Differentiating features speed (need not be fully predictable) speed did we mention speed? cost (largest component power) Logic embedded computer mem SOC - 3

3 Embedded System: Examples Embedded System SOC - 4 Design Complexity Increase SoC Characteristics Average Gate Count Designs with Gate Count > 1M Units Shipped >5M # of lines of DSP SW # of lines of up SW Clock Speed >133mhz >400mhz >5 Clock Domains >9 Clock Domains Current Design 616K 18% 20% 54K 75K 44% 15% 25% 10% Next Design 1,000K 31% 37% 295K 266K 61% 22% 35% 12% Source: Collett International Research- December 2000 Research on 360 IC/ASIC Design Teams in North America SOC - 5

4 Embedded System on Chip (SoC) Design Zone 4: Global Satellite Zone 3: Suburban System Environment Zone 2: Urban Zone 1: In-Building Specification Untimed, Unclocked, C/C++ Level Macro-Cell Micro-Cell Pico-Cell Requirements Specification Embedded Systems Design Refinement Design Export Implementation Timed, Clocked, RTL Level Testbench Memory P/C µ Embedded Software Analog Software SOC Firmware Characterization Implementation CORE SOC - 6 Architectures Supplements Models by specifying how the system will actually be implemented Goal of each architecture is to describe Number of components Type of each component Type of each connection among above components General classification Application-specific architectures: DSP General-purpose architectures: CISC, RISC Parallel processors: VLIW, SIMD, MIMD SOC - 7

5 System Architecture Design System Architecture & Exploration What Hardware/Software partitioning; processor, and memory architecture choices; system timing budget, power management strategy, system verification strategy Partitioning into HW block hierarchy, cycle time budgeting, block interfaces, block verification, clock architecture and test strategy Fixed point architecture exploration and design How - Quickly assemble architecture(s) for exploration to measure system timing/performance. Need to accurately (enough) model the bottlenecks SOC - 8 System Integration & Verification System Design Environment for HW/SW Refinement, Verification and Integration What Enables hierarchical (manual or automatic) refinement of individual blocks of design in context of system. Maintain system and hierarchical test benches Verification of refined hardware/software with entire system design Define next level of clock architecture (derived) and test strategy How - Build a system verification hierarchy that allows integration of HW blocks, system software (HAL), embedded application SW and eventually verifying the entire design at cycle accurate (or RTL) level SOC - 9

6 CoDesign and Co-Synthesis Specification Partition HW: HDL (Behavioral, DataFlow, Structural), Schematic Co-Synthesis Synthesis SW: Algorithm, Textual/Graphical representation RTL, Gate level, Transistors, Layout Detailed Representation of Implementation Executable or Compilable code: The program(s), OS routines SOC - 10 Traditional design Tasks Traditional System Design Process System design SW design PCB test SW test ASIC design Fabrication Test Time SOC - 11

7 System-level Co-design Tasks Co-Design Process SW design SW test System design Shared Design PCB test ASIC design Fabrication Test System-Level Partitioning Time SOC - 12 Configurabilty and Embedded Systems Advantages of configuration: Pay (in power, design time, area) only for what you use Gain additional performance by adding features tailored to your application: Particularly for embedded systems: Principally in embedded controller microprocessor applications Some us in DSP SOC - 13

8 What to Configure? What parts of the microcontroller/microprocessor system to configure? Easy answers: Memory and Cache Sizes - get precisely the sizes your applications needs Register file sizes Interrupt handling and addresses Harder answers: Peripherals Instructions But first we need more context SOC - 14 Trickle Down Theory of Embedded Architectures Mainframe/supercomputers High-end servers/workstations High-end personal computers Personal computers Lap tops/palm tops Features tend to trickle down: #bits: 4->8->16->32->64 ISA s Floating point support Dynamic scheduling Caches I/O controllers/processors LIW/VLIW Superscalar Gadgets Watches... SOC - 15

9 Configurability in ARM Processor ARM allows for configurability via AMBA bus Offers ``prime cell peripherals which hook into AMBA Peripheral Bus (APB) UART Real Time Clock Audio Codec Interface Keyboard and mouse interface General purpose I/O Smart card interface Generic IR interface SOC - 16 ARM7 core SOC - 17

10 ARM s Amba open standard Advanced System Bus, (ASB) - high performance, CPU, DMA, external Advanced Peripheral Bus, (APB) - low speed, low power, parallel I/O, UART s External interface SOC - 18 Ex: ARM Infrared (IR) Interface SOC - 19

11 Ex : Audio Codec SOC - 20 Another Kind of Configurability Library HDL RTL Synthesis netlist logic optimization netlist physical design Synthesis of a processor core from an RTL description allows for: full range of other types of configurability additional degrees of freedom in quality of implementation Examples: ARM7 Motorola Coldfire Tensilica Xtensa layout SOC - 21

12 Issues in low-level Configurable Design Choice and Granularity of Computational Elements Choice and Granularity of Interconnect Network (Re)configuration Time and Rate Fabrication time --> Fixed function devices Beginning of product use --> Actel/Quicklogic FPGAs Beginning of usage epoch --> (Re)configurable FPGAs Every cycle --> traditional Instruction Set Processors SOC - 22 The Choice of the Computational Elements Reconfigurable Logic Reconfigurable Datapaths Reconfigurable Arithmetic In Reconfigurable Control CLB CLB CLB CLB mux reg0 reg1 adder buffer AddrGen Memory AddrGen Memory MAC Data Memory Datapath Data Memory Program Memory Inst ruction Decoder & Controller Bit-Level Operations e.g. encoding Dedicated data paths e.g. Filters, AGU Arithmetic kernels e.g. Convolution RTOS Process management SOC - 23

13 Multi-granularity Reconfigurable Architecture: The Berkeley Pleiades Architecture Configuration Bus Satellite Processor Arithmetic Processor Arithmetic Processor Communication Network Arithmetic Processor Configuration Dedicated Arithmetic Control Processor Configurable Datapath Configurable Logic Network Interface Computational kernels are spawned to satellite processors Control processor supports RTOS and reconfiguration Order(s) of magnitude energy-reduction over traditional programmable architectures SOC - 24 Matching Computation and Architecture AddressGen AddressGen Convolution Memory MAC Memory MAC L G C Control Processor Two models of computation: communicating processes + data-flow Two architectural models: sequential control+ data-driven SOC - 25

14 Execution Model of a Data-Flow Kernel Code seg Embedded processor start end for(i=1;i<=l;i++) AddrGen for(k=i;k<=l;k++) MEM: in phi[i][k]= phi[i-1][k-1] +in[np-i]*in[np-k] -in[na-1-i]*in[na-1-k]; MPY ALU MPY AddrGen MEM: phi Code seg ALU Distributed control and memory SOC - 26 Software Methodology Flow Algorithms C++ Kernel Detection Behavioral Estimation/Exploration SUIF+ C-IF Power & Timing Estimation of Various Kernel Implementations Partitioning Software Compilation Reconfig. Hardware Mapping Interface Code Generation µproc& Accelerator PDA Models Premapped Kernels C++ Module Libraries SOC - 27

15 The System-on-a-Chip Nightmare DMA CPU DSP System Bus Mem Ctrl. Bridge MPEG The Board-on-a-Chip Approach C I O O Custom Interfaces Control Wires Peripheral Bus SOC - 28 Sonics SOC Integration Architecture DMA CPU DSP MPEG Open Core Protocol { SiliconBackplane (patented) MultiChip Backplane C MEM I O SiliconBackplane Agent SOC - 29

16 Master vs. Slave IP Core IP Core IP Core Master Master Slave Slave Open Core Protocol Request Response Slave Initiator Slave Master Target Master On-Chip Bus SOC - 30 The Backplane: Why Not Use a Computer Bus? IP Core Data Transmit FIFO Arbiter Computer Bus Address Receive FIFO IP Core IP Core Time IP Core Expensive to decouple Not designed for real-time SOC - 31

17 Communication Buses Decouple and Guarantee Real Time IP Core Data Transmit FIFO TDMA Communications Bus TDMA Receive FIFO IP Core IP Core Time IP Core Connections are expensive Poor read latency SOC - 32 On-Chip Bus for SOC Example on- chip bus interconnects ARM s AMBA bus IBM s Core Connect Virtual Socket Interface Alliance group Open Connect Protocol group Example processor cores ARM MIPS PowerPC SOC - 33

18 Design Example: The Radio-on-a-Chip Reconfigurable State Machines FPGA Dedicated DSP Embedded up +DSPs Reconfigurable DataPath DSP and control intensive Mixed-mode Combines programmable, flexible, and application-specific modules Cost and energy are the key metrics SOC - 34 System Level Design Science Design Methodology: Top Down Aspect: Orthogonalization of Concerns: Separate Implementation from Conceptual Aspects Separate computation from communication Formalization: precise unambiguous semantics Abstraction: capture the desired system details (do not overspecify) Decomposition: partitioning the system behavior into simpler behaviors Successive Refinements: refine the abstraction level down to the implementation by filling in details and passing constraints Bottom Up Aspect: IP Re-use (even at the algorithmic and functional level) Components of architecture from pre-existing library SOC - 35

19 Separate Behavior from Micro-architecture System Behavior Front End 1 Functional Specification of System. No notion of hardware or software! Transport Decode 2 Rate Buffer 12 Rate Buffer 5 Rate Buffer 9 Mem 13 User/Sys Control 3 Synch Control 4 Video Decode 6 Audio Decode/ Output 10 Sensor Frame Buffer 7 Video Output 8 Implementation Architecture Hardware and Software Optimized Computer External I/O MPEG Peripheral Audio Decode Processor Bus DSP Processor DSP RAM Control Processor System RAM Mem 11 SOC - 36 Map Between Behavior from Architecture Transport Decode Implemented as Software Task Running on Microcontroller Rate Buffer 12 Mem 13 User/Sys Control 3 Sensor Communication Over Bus External I/O DSP Processor Front End 1 Transport Decode 2 Rate Buffer 5 Rate Buffer 9 Synch Control 4 Video Decode 6 Audio Decode/ Output 10 Mem 11 Frame Buffer 7 Video Output 8 MPEG Peripheral Audio Decode Processor Bus DSP RAM Control Processor System RAM Audio Decode Behavior Implemented on Dedicated Hardware SOC - 37

20 Embedded Software Crisis J. Fiddler - WRS Cheaper, more powerful Microprocessors Increasing Time-to to-market pressure Embedded Software Crisis More Applications J. Fiddler - WRS Bigger, More Complex Applications SOC - 38 SW: Embedded Software Tools U S E R application source code compiler Application software a.out RTOS debugger simulator C P U A S I C A S I C ROM RAM SOC - 39

21 Compiler Hardware Platforms Not Enough! Hardware platform has to be abstracted Interface to the application software is the API Software layer performs abstraction: Programmable cores and memory subsystem hidden by RTOS and compilers I/O subsystem with Device Drivers Network with Network Communication Software SOC - 40 Software Platforms Application Software Platform API Software Platform Hardware Platform Input devices Output Devices network Software Hardware I O RTOS API Device Drivers BIOS Network Communication SOC - 41

22 Platform-based methodology Platform based design: Application mapped on architecture Performance evaluation and iterative refinement Challenges: complete system simulation complexity management composability and reuse Key elements for composability Identification and use of useful models of computation FSMD, DE, DF, CSP,... A flexible, extensible language platform to capture the functionality. Composability can be achieved using Object-oriented mechanisms: SOC - 42 Final goal for SOC: Platform-Based Design Taking Design Block Reuse to the Next Level Pre-Qualified/Verified Foundation-IP* Hardware IP SW IP Programmable *IP can be hardware (digital or analogue) or software. IP can be hard, soft or firm (HW), source or object (SW) Foundation Block MEM Application Space CPU FPGA Foundry-Specific Pre-Qualification + Reference Design Scaleable bus, test, power, IO, clock, timing architectures Processor(s), RTOS(es) and SW architecture Methodology / Flows: System-level performance evaluation environment Rapid Prototype for End-Customer Evaluation SoC Derivative Design Methodologies Foundry Targetting Flow SOC - 43

23 Summary of SOC Design System Specification Verification Co-Synthesis Partitioning HW Parameter Estimation SW Parameter Estimation Verification HW Synthesis ASIC SW Synthesis OS EXE Code Verification Verification System Integration Final Verification SOC - 44