Design And Verification of 10X10 Router For NOC Applications

Transcription

1 Design And Verification of 10X10 Router For NOC Applications 1 Yasmeen Fathima, 2 B.V.KRISHNAVENI, 3 L.Suneel 2,3 Assistant Professor 1,2,3 CMR Institute of Technology, Medchal Road, Hyderabad, Telangana, India. 1 shaik.yasmeen90@gmail.com, 2 krishnavenibv@gmail.com, 3 suneel.430@gmail.com Abstract: Routers are the basic building blocks of NoCs, which are responsible for redirecting packets from source node to its destination and their throughput critically affects the whole network performance. One of the most important building blocks in the router is the arbitration circuit, which controls granting to various requesters when the network is heavily used. At a given time, when the network has many packets, many input ports at a router can request to send data to the same output port, and then an arbitration circuit is needed to decide from the output port requesters which one will be granted to pass through. The most widely used arbiter in NoCs is Fixed priority arbiter (FPA) which is simple in design, fast, and has strong fairness. In this work we focus on RRAs (Round Robin Arbiters) and their impact on router s performance and area on various FPGAs. In the existing system, we had 4X4 Router and round robin arbiter was used to setup the Priority level. In the proposed system we have extended it to 10x10 router, and instead of round robin arbiter we have used Fixed priority arbiter scheme. Due to priority level setup we can manage the multiple inputs who are trying to connect a particular output. This will avoid the data loss and by using fixed priority scheme we can connect a particular input to the desired output, and this will not increase the complexity even if the project is extended to 20x20 router. Introduction: A router is a device that forwards data packets between computer networks, creating overlay internetwork. A router is connected to two or more data lines from different networks. When a data packet comes in one of the lines, the router reads the address information in the packet to determine its ultimate destination. Then, using information in its routing table or routing policy, it directs the packet to the next network on its journey. Routers perform the "traffic directing" functions on the Internet. A data packet is typically forwarded from one router to another through the networks that constitute the internetwork until it reaches its destination node. The most familiar type of routers are home and small office routers that simply pass data, such as web pages, , IM, and videos between the home computers and the Internet. An example of a router would be the owner's cable or DSL modem, which connects to the Internet through an ISP. More sophisticated routers, such as enterprise routers, connect large business or ISP networks up to the powerful core routers that forward data at high speed along the optical fiber lines of the Internet backbone. Though routers are typically dedicated hardware devices, use of software-based routers has grown increasingly common. When multiple routers are used in interconnected networks, the routers exchange information about destination addresses using a dynamic routing protocol. Each router builds up a table IJCSIET-ISSUE5-VOLUME2-SERIES4 Page 1

2 listing the preferred routes between any two systems on the interconnected networks. A router has interfaces for different physical types of network connections, (such as copper cables, fiber optic, or wireless transmission). It also contains firmware for different networking communication protocol standards. Each network interface uses this specialized computer software to enable data packets to be forwarded from one protocol transmission system to another. Routers are small physical devices that join multiple networks together. Technically, a router is a Layer 3 gateway device, meaning that it connects two or more networks and that the router operates at the network layer of the OSI model. NoC: Network on chip or network on a chip (NoC or NOC) is a communication subsystem on an integrated circuit (commonly called a "chip"), typically between IP cores in a system on chip (SoC). NoCs can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NoC technology applies networking theory and methods to on-chip communication and brings notable improvements over conventional bus and crossbar interconnections. NoC improves the scalability of SoCs, and the power efficiency of complex SoCs compared to other designs. Fig 2 Communication structure in SoC a) traditionalbus based communication, b) dedicated point to point links c) network on a chip Network on chip is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. In a NoC system, modules such as processor cores, memories and specialized IP blocks exchange data using a network as "public transportation " sub-system for the information traffic. A NoC is constructed from multiple point-to-point data links interconnected by switches (like routers), such that messages can be relayed from any source module to any destination module over several links, by making routing decisions at the switches. A NoC is similar to a modern telecommunications network, using digital bit-packet switching over multiplexed links. Although packetswitching is sometimes claimed as necessity for a NoC, there are several NoC proposals utilizing circuit-switching techniques. This definition based on routers is usually interpreted so that a single shared bus, a single crossbar switch or a point-to-point network are not NoCs but practically all other topologies are. This is somewhat confusing since all above mentioned are networks (they enable communication between two or more devices) but they are not considered as network-on-chip approaches. The wires in the links of the NoC are shared by many signals. A high level of parallelism is achieved, because all links in the NoC can operate simultaneously on different data packets. Therefore, as the complexity of integrated systems keeps growing, a NoC provides enhanced performance (such as throughput) and scalability in comparison with previous communication architectures (e.g., dedicated point-to- IJCSIET-ISSUE5-VOLUME2-SERIES4 Page 2

3 point signal wires, shared buses, or segmented buses with bridges). Of course, the algorithms must be designed in such a way that they offer large parallelism and can hence utilize the potential of NoC. Benefits of adopting NoCs are Traditionally, ICs have been designed with dedicated point-to-point connections, with one wire dedicated to each signal. For large designs, in particular, this has several limitations from a physical design viewpoint. The wires occupy much of the area of the chip, and in nanometer CMOS technology, interconnects dominate both performance and dynamic power dissipation, as signal propagation in wires across the chip requires multiple clock cycles. NoC links can reduce the complexity of designing wires for predictable speed, power, noise, reliability, etc., thanks to their regular, well-controlled structure. From a system design viewpoint, with the advent of multi-core processor systems, a network is a natural architectural choice. A NoC can provide separation between computation and communication, support modularity and IP reuse via standard interfaces, handle synchronization issues, serve as a platform for system test, and, hence, increase engineering productivity. Paradigm: Fig 3. General Architecture of NoC Network on chip is an emergingparadigm for communications within large VLSI systems implemented on a single silicon chip. Sgroietal. call "the layered-stack approach to the design of the on-chip inter-core communications the network-on-chip (NOC) methodology." In a NoC system, modules such as processor cores, memories and specialized IP blocks exchange data using a network as a "public transportation" sub-system for the information traffic. A NoC is constructed from multiple point-to-point data links interconnected by switches (a.k.a. routers), such that messages can be relayed from any source module to any destination module over several links, by making routing decisions at the switches. A NoC is similar to a modern telecommunications network, using digital bit-packet switching over multiplexed links. Although packet-switching is sometimes claimed as necessity for a NoC, there are several NoC proposals utilizing circuitswitching techniques. This definition based on routers is usually interpreted so that a single shared bus, a single crossbar switch or a point- IJCSIET-ISSUE5-VOLUME2-SERIES4 Page 3

4 to-point network are not NoCs but practically all other topologies are. This is somewhat confusing since all above mentioned are networks (they enable communication between two or more devices) but they are not considered as network-on-chip approaches. Parallelism and Scalability: The wires in the links of the NoC are shared by many signals. A high level of parallelism is achieved, because all links in the NoC can operate simultaneously on different data packets. Therefore, as the complexity of integrated systems keeps growing, a NoC provides enhanced performance (such as throughput) and scalability in comparison with previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). Of course, the algorithms must be designed in such a way that they offer large parallelism and can hence utilize the potential of NoC. Research on NOC network: Although NoCs can borrow concepts and techniques from the wellestablished domain of computer networking, it is impractical to blindly reuse features of "classical" computer networks and symmetric multiprocessors. In particular, NoC switches should be small, energy-efficient, and fast. Neglecting these aspects along with proper, quantitative comparison was typical for early NoC research but nowadays they are considered in more detail. The routing algorithms should be implemented by simple logic, and the number of data buffers should be minimal. Network topology and properties may be application-specific. Some researchers think that NoCs need to support quality of service (QoS), namely achieve the various requirements in terms of throughput, end-to-end delays and deadlines. Real-time computation, including audio and video playback, is one reason for providing like VxWorks, RTLinux or QNX are able to achieve sub-millisecond real-time computing without special hardware. This may indicate that for many real-time applications the service quality of existing on-chip interconnect infrastructure is sufficient, and dedicated hardware logic would be necessary to achieve microsecond precision, a degree that is rarely needed in practice for end users (sound or video jitter need only tenth of milliseconds latency guarantee). Another motivation for NoClevel quality-of-service is to support multiple concurrent users sharing resources of a single chip multiprocessor in a public cloud computing infrastructure. In such instances, hardware QOS logic enables the service provider to make contractual guarantees on the level of service that a user receives, a feature that may be deemed desirable by some corporate or government clients. To date, several prototype NoCs have been designed and analyzed in both industry and academia but only few have been implemented on silicon. However, many challenging research problems remain to be solved at all levels, from the physical link level through the network level, and all the way up to the system architecture and application software. The first dedicated research symposium on networks on chip was held at Princeton University, in May The second IEEE International Symposium on Networks-on-Chip was held in April 2008 at Newcastle University. IJCSIET-ISSUE5-VOLUME2-SERIES4 Page 4

5 Research has been done on integrated optical waveguides and devices comprising an optical network on a chip (ONoC). Benefits of adopting NOC: Traditionally, ICs have been designed with dedicated point-to-point connections, with one wire dedicated to each signal. For large designs, in particular, this has several limitations from a physical design viewpoint. The wires occupy much of the area of the chip, and in nanometer CMOS technology, interconnects dominant both performance and dynamic power dissipation, as signal propagation in wires across the chip requires multiple clock cycles. (See Rent's rule for a discussion of wiring requirements for point-to-point connections). NoC links can reduce the complexity of designing wires for predictable speed, power, noise, reliability, etc., thanks to their regular, well-controlled structure. From a system design viewpoint, with the advent of multi-core processor systems, a network is a natural architectural choice. It separation between computation and communication, support modularity and IP reuse via standard interfaces, handle synchronization issues, serve as a platform for system test, increase engineering productivity. NOC benchmarks: NoC development and studies require comparing different proposals and options. And NoC traffic patterns are developed to help such evaluations. Existing NoC benchmarks include NoCBench and MCSL NoC Traffic Patterns. Arbiter: This block works in conjunction with a round robin priority encoder and the credit based flow control FSM. Due to this design choice, a very efficient way of congestion control and avoiding resource starvation was deployed. The arbiter has four allocators, one for each input-output port pair. The arbiter may receive resource allocation request from all four input ports simultaneously, and hence the priority logic is essentially processing multiple requests and once an output channel is matched to an input port, the selection logic holds the allocator active till a tail flit is processed through the crossbar. Crossbar Switch: The switch is implemented using four 4x1 multiplexers (MUX). The output of each MUX is registered and goes straight to its corresponding output port. The crossbar is controlled by one of the select signals from the arbiter block. Below figure 3 shows a node-tonode traversal example. In this scenario, data packets 1 & 2 arrive at N4 from N1 and N3 respectively and need to be routed to N5. In this example, N4 determines that packet 1 gets priority and hence allocates the corresponding port resources to its traversal. Once packet 1 is routed, packet 2 gets the resource allocation. A flit traverses only after a credit is received back from the downstream node. Since the router immediately registers inbound and outbound data, the timing restriction of routers are self-contained. As a result, the router is compatible with globally asynchronous and locally synchronous (GALS) NoC topology as well. The ability to reduce the zero load latency per hop to adjust 1 clock cycle is a significant improvements over which take a least 2 cycles and other contemporary NoC router which require 7-8 cycles. IJCSIET-ISSUE5-VOLUME2-SERIES4 Page 5

6 is ready to receive one. Using this method, several nodes can simultaneously trigger data transactions and load the network considerably in different fashions. traversal Implementation: Fig. 4: Node to node The evaluation strategy of the proposed design consists of verifying the accuracy of the data routed by putting the network under various traffic loads and the transaction of packets ranging from small to large packet sizes. Each flit is 18 bits in size and therefore that is the required bus width for interconnecting different routers. In order to run experiments, a simple traffic generator is associated with each router on each node which may also be considered as a model of an associated core to the router. This provides the flexibility of sending data from a source node to any random destination node. The random destination is generated within the traffic generator using a linear feedback shift register. A block diagram of the interface is shown in figure. 4 below. The traffic generator follows the same flow control principle and will keep track of the capacity of the connecting router s input buffer. The traffic generator should produce a flit only once the local router s input buffer Another aspect of the router design and NoC performance is the area consumed via the interconnect fabric and the underlying logic. The address of each router is a 6-bit value, the 3 MSBs are the x-coordinate and 3 LSBs are the y- coordinate for each router on the NoC. Due to this, a maximum of 64 nodes can be implemented on one NoC topology. In order to get a fair estimate of the area consumption, 3 different networks are implemented and synthesized on each NoC in order to record their device utilization. They are as follows: a) 1-D 8 node ring b) 2-D 4x4 mesh and c) 2-D 8x8 mesh. The synthesis and timing results provide the maximum applicable clock rate to the network. Fig. 5: Block diagram for traffic generator Last but not least, another important parameter to evaluate is the power dissipation. For this experiment, a single source to single destination transaction is targeted where data travels the highest possible hop count, which is IJCSIET-ISSUE5-VOLUME2-SERIES4 Page 6

7 14 hops, and an intermediate hop count, which are 8 hops. This experiment requires the creation of a userconstrained file (UCF), synthesis of the design and the place and route of the design to get a fairly accurate estimate by including the device placement and its associated routing. the flow control is a credit based flow control are presented in this project. Using the router as underlying architecture, several different size NoC topologies were implemented and validated. Architecture: In any design all three factors (latency, area & power dissipation) can affect the feasibility of its usage and any tradeoffs required to optimize the design for the target application will typically start from here. Sets of experiments are conducted to estimate the maximum clock rates for each design for each network topology. The data was obtained post synthesis of the design and also providing the user controlled inputs. Table I shows the achievable clock rates of the three NoC architectures under consideration. Also shown in the table are the setup and hold margin for the designs. The latency associated with data transactions based upon hop count. As expected, latency increases from a 3-hop transaction to 8 hop transaction to a 14 hop transaction. Figure 6 provides the pie chart distribution between the three major categories of the 8x8 mesh network on chip these are the clock buffers, router logic and signal (routing). The most power hungry component of the design is the clock buffers. This can be attributed to the fact that a global clock is used to synchronize the network. As a result the buffers have become quite large in size and quantity to make sure the clock skew and transition is within desired limits. At some point though, with increased network size and traffic, it would be expected the signal power consumption surpassed the clock buffer power consumption. Fig 6. Architecture Block diagram Results: Schematic View: The details of the design of a packet switched wormhole router where IJCSIET-ISSUE5-VOLUME2-SERIES4 Page 7

8 RTL Schematic: and in the future extension we can replace the fixed priority and can change the priority dynamically according to our requirement. REFERENCES Waveform: Conclusion: In this paper, we have designed and verified 10x10 router with reduced complexity and easy flow of data. With this method we can extend this project to number of inputs and no of outputs and this will also reduce the complexity and easy flow of data. we can conclude that the Fixed priority arbiter is one of the major bottleneck building blocks in the router and it influences the performance of the router. Without any loss of data [1] W. J. Dally and B. Towles, Route Packets, Not Wires: On-Chip Inteconnection Networks, In Proc. of 38th Design Automation Conference (DAC), [2] L. Benini, G. De Micheli, "Networks on chips: a new SoC paradigm," Computer, vol.35, no.1, pp.70-78, [3] E. Cota, M. Kreutz,, C.A. Zeferino, L. Carro, M. Lubaszewski, and A. Susin, "The impact of NoC reuse on the testing of core-based systems," In Proc. of 21st VLSI Test Symposium, pp , [4] P.P. Pande, C. Grecu, A. Ivanov, R. Saleh, and G. De Micheli, "Design, synthesis, and test of networks on chips," IEEE Design & Test of Computers, vol.22, no.5, pp , [5] T. Bjerregaard and S. Mahadevan, "A survey of research and practices of Network-on-chip," ACM Computing Surveys, vol. 38, pp. 1-51, [6] E. Salminen et al., "Survey of Network-on-Chip proposals," white paper, Opec Core Protocol International partnerchip (OCP-IP), [7] A. Agarwal, C. Iskander, and R. Shankar, Survey of Network on Chip (NoC) Architectures & Contributions, Jornal of Engineering, Computing and Architectures, vol. 3, Issue 1, [8] W. J. Dally and B. Towles. Principles and Practices of Interconnection Networks, Morgan Kaufmann Publishers, San Francisco, CA, [9] B. C. Shubha, and P. Srikanta, "FPGA implementation of network on chip framework using HDL," Students' Technology Symposium (TechSym), pp , 2010 IJCSIET-ISSUE5-VOLUME2-SERIES4 Page 8

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