Architectural Options for LPDDR4 Implementation in Your Next Chip Design

Transcription

1 Architectural Options for LPDDR4 Implementation in Your Next Chip Design Marc Greenberg, Director, DDR Product Marketing, Synopsys JEDEC Mobile & IOT Forum Copyright 2016 Synopsys, Inc.

2 Introduction / Agenda LPDDR4 is different from earlier JEDEC Ways to connect LPDDR4 multiple channels How to handle 2-die and 4-die packages Dividing memory traffic across channels Floorplanning and making connections Using LPDDR4 low power features Key features of an LPDDR4 solution

3 Introduction / Agenda LPDDR4 is different from earlier JEDEC Ways to connect LPDDR4 multiple channels How to handle 2-die and 4-die packages Dividing memory traffic across channels Floorplanning and making connections Using LPDDR4 low power features Key features of an LPDDR4 solution

4 LPDDR4 is Different From Earlier DDR2,3,4 are all one die per package with one command/address bus input and one data bus LPDDR2,3 offer one or two dies per package, each die with its own command/address input and data bus LPDDR4 have two command/address inputs (channels) and two data busses per die Some LPDDR4 packages have two dies 4 channels

5 Introduction / Agenda LPDDR4 is different from earlier JEDEC Ways to connect LPDDR4 multiple channels How to handle 2-die and 4-die packages Dividing memory traffic across channels Floorplanning and making connections Using LPDDR4 low power features Key features of an LPDDR4 solution

6 What is Multi-Channel? One device: only 1 way to connect Data Command/Address Chip select (example: LPDDR3) What happens if we have two devices, or one device with 2 independent interfaces like LPDDR4?

7 What is Multi-Channel? Two devices: 4 ways to connect Parallel (lockstep) Series (multi-rank) Multi-channel Multi-channel with Shared-CA Data Command/Address. Chip select Data * * * One die of LPDDR2/3 or one channel of LPDDR4 Parallel connection: Both devices receive the same command & address but transmit data over different byte lanes. Both devices are accessed simultaneously

8 What is Multi-Channel? Two devices: 4 ways to connect Parallel (lockstep) Series (multi-rank) Multi-channel Multi-channel with Shared-CA Chip selects Data Command/Address * * One die of LPDDR2/3 or one channel of LPDDR4 * Series (Multi-rank) Connection: Both devices receive the same command & address and use the same byte lanes. Chip select signals determine which device is being accessed

9 What is Multi-Channel? Two devices: 4 ways to connect Parallel (lockstep) Series (multi-rank) Multi-channel Multi-channel with Shared-CA Chip select Data Command/Address Command/Address * Multi-Channel Connection: Each device operates independently of the other, receives a different command & address, transmits over different byte lanes Data * Chip select * One die of LPDDR2/3 or one channel of LPDDR4

10 What is Multi-Channel? Two devices: 4 ways to connect Parallel (lockstep) Series (multi-rank) Multi-channel Multi-channel with Shared-CA Chip select Data Command/Address. Data Chip select Multi-channel with Shared-CA (aka Shared-AC): Both devices receive the same command & address but only one device is accessed with an active chip select at a time, so each device operates independently devices use different byte lanes OK for DDR4/3, not recommended for LPDDR4

11 Review: 4 Ways of Connecting 2 Channels (1 Die) of LPDDR4 Parallel CA pins: 6 DQ pins: 32 CS pins: 1 Banks: 8 Fetch: 64 Series CA pins: 6 DQ pins: 16 CS pins: 1 Banks: 8 Fetch: 32 Multi-channel CA pins: 12 DQ pins: 32 CS pins: 2 Banks: 16 Fetch: 32 Shared-CA CA pins: 6 DQ pins: 32 CS pins: 2 Banks: 16 Fetch: 32/64 = 1 channel of LPDDR4 CA Bus DQ (Data) Bus CS(Chip Select)

12 Review: 4 Ways of Connecting 2 Channels (1 Die) of LPDDR4 Difficult Parallel for PoP implementation. CA pins: 6 Less DQ effective pins: 32 bank CS utilization. pins: 1 64 Banks: byte fetch. 8 Fetch: 64 Difficult Series for PoP implementation. CA pins: 6 Half the DQ bandwidth pins: 16 of other CS solutions. pins: 1 Saves Banks: some 8DQ pins. Fetch: 32 Multi-channel Good choice CA for LPDDR4. pins: 12 DQ pins: 32 CS pins: 2 Banks: 16 Fetch: 32 Difficult Shared-CA for PoP implementation. CA pins: 6 Better DQ pins: suited 32to DDR CS pins: systems. 2 Banks: 16 Fetch: 32 = 1 channel of LPDDR4 CA Bus DQ (Data) Bus CS(Chip Select)

13 Introduction / Agenda LPDDR4 is different from earlier JEDEC Ways to connect LPDDR4 multiple channels How to handle 2-die and 4-die packages Dividing memory traffic across channels Floorplanning and making connections Using LPDDR4 low power features Key features of an LPDDR4 solution

14 8 Ways of Connecting 4 Channels (2 Dies) of LPDDR4 = 1 channel of LPDDR4 CA Bus DQ (Data) Bus CS(Chip Select)

15 8 Ways of Connecting 4 Channels (2 Dies) of LPDDR4 Some are good Some are not! = 1 channel of LPDDR4 CA Bus DQ (Data) Bus CS(Chip Select)

16 8 Ways of Connecting 4 Channels (2 Dies) of LPDDR4 4 Channel CA pins: 24 DQ pins: 64 CS pins: 4 Banks: 32 Fetch: 32 2 Channel & Parallel CA pins: 12 DQ pins: 64 CS pins: 2 Banks: 16 Fetch: 64 4 Channel & Shared-CA CA pins: 12 DQ pins: 64 CS pins: 4 Banks: 32 Fetch: 32/64 2 Channel & Serial CA pins: 12 DQ pins: 32 CS pins: 4 Banks: 32 Fetch: 32 Parallel CA pins: 6 DQ pins: 64 CS pins: 1 Banks: 8 Fetch: 128 Complicated CA pins: 6 DQ pins: 32 CS pins: 2 Banks: 16 Fetch: 32/64 Complicated CA pins: 6 DQ pins: 32 CS pins: 4 Banks: 32 Fetch: 32/64 Serial CA pins: 6 DQ pins: 16 CS pins: 4 Banks: 32 Fetch: 32 = 1 channel of LPDDR4 CA Bus DQ (Data) Bus CS(Chip Select)

17 Suggested 2-Die LPDDR4 Implementations 4 Channel CA pins: 24 DQ pins: 64 CS pins: 4 Banks: 32 Fetch: 32 2 Channel & Parallel CA pins: 12 DQ pins: 64 CS pins: 2 Banks: 16 Fetch: 64 Most flexible and potentially highest performance Most familiar implementation especially for LPDDR3 users & LPDDR3/LPDDR4 combination = 1 channel of LPDDR4 CA Bus DQ (Data) Bus CS(Chip Select)

18 Expanding to Quad-die Example 2-die LPDDR4 multichannel implementation Example 4-die LPDDR4 multichannel and serial implementation adds capacity. This solution is compatible with 2-die packages. = 1 channel of LPDDR4 CA Bus DQ (Data) Bus CS(Chip Select)

19 Introduction / Agenda LPDDR4 is different from earlier JEDEC Ways to connect LPDDR4 multiple channels How to handle 2-die and 4-die packages Dividing memory traffic across channels Floorplanning and making connections Using LPDDR4 low power features Key features of an LPDDR4 solution

20 Partitioning for LPDDR4 PoP Channel A Channel C Channel A Channel C LPDDR4 Package Ballout Memory Controller and PHY placement sbould be close to LPDDR4 ballout Channel B Channel D Channel B Channel D LPDDR4 package layout

21 Partitioning for LPDDR4 PoP Channel A Channel A Channel C Channel C Channel B Channel B Channel D Channel D

22 Real Examples: Five LPDDR4 chip floorplans 4x16bit LPDDR4-only Applications Processors Chip Area LPDDR4 area 2x32bit LPDDR4-only Applications processor 1X64bit DDR4/LPDDR4 Special purpose Sizes/locations are approximate and not to scale. Images derived from commercially purchased chips. Chips shown include Synopsys and non-synopsys designs.

23 Dual Channel Block Diagram DDR area on chip schematic view Good option for LPDDR4/LPDDR3 combo 2 channels can share one set of on-chip busses or two sets

24 Dual Channel Floorplan CH-A A/C CH-A DQ[15:8] CH-C DQ[7:0] CH-C A/C CH-A DQ[7:0] 32b MCTL CH-C DQ[15:8] 32b PUB 32b PUB CH-B DQ[7:0] 32b MCTL CH-D DQ[15:8] Good option for LPDDR4/LPDDR3 combo CH-B A/C CH-B DQ[15:8] CH-D DQ[7:0] CH-D A/C 2 channels can share one set of on-chip busses or two sets 2015 Synopsys, Inc. 25

25 Quad Channel Block Diagram DDR area on chip schematic view Channels A-B shown, repeat for channels C-D LPDDR4-focus 2 channels can share one set of on-chip busses or two sets 4 independent interfaces also possible

26 Quad Channel Floorplan CH-A A/C CH-A DQ[15:8] CH-C DQ[7:0] CH-C A/C CH-A DQ[7:0] 16b PUB 16b PUB CH-C DQ[15:8] 32b MCTL 32b MCTL CH-B DQ[7:0] 16b PUB 16b PUB CH-D DQ[15:8] LPDDR4-focus 2 channels can share one set of on-chip busses or two sets CH-B A/C CH-B DQ[15:8] CH-D DQ[7:0] CH-D A/C 4 independent interfaces also possible 2015 Synopsys, Inc. 27

27 Introduction / Agenda LPDDR4 is different from earlier JEDEC Ways to connect LPDDR4 multiple channels How to handle 2-die and 4-die packages Dividing memory traffic across channels Floorplanning and making connections Using LPDDR4 low power features Key features of an LPDDR4 solution

28 Three key areas to save power Use low-power states Powerdown, Self-Refresh Automatic Entry & Exit by controller Different channels in different power states Always On Always Connected data in one channel Control by logical to physical address map Frequency Changing Change drive & termination with frequency

29 Logical to Physical Address Map Separate Memory Map Consecutive addresses are in one memory channel or the other The address ranges do not overlap between channels Good for power control Logical Address Y MByte Physical location Two memory channels are completely different memory spaces Application data, video buffer, etc X MByte 0 Operating System and always on always connected functions Channel A Channel B

30 Logical to Physical Address Map Interleaved Memory Map Consecutive addresses are striped across both memory channels Good for load balancing, not good for power Logical Address Y MByte X MByte Physical location The whole logical space is interleaved across the whole memory 0 Channel A Channel B

31 Logical to Physical Address Map Hybrid Memory Map Different regions in each channel are used to provide high bandwidth and controllable power Logical Address Y MByte Physical location Memory for programs that are associated with high bandwidth Memory for highperformance and video functions may be interleaved across both memory channels to distribute traffic when both channels are on X MByte 0 Operating System and always on always connected functions Channel A Channel B

32 LPDDR4 Use Model for Mobile Devices Drives replacement cycle 1% LPDDR4 3200Mbps 4267Mbps Highest performance 9% Mbps (LPDDR3 range) Phone, browse, photograph, text, read, puzzles, easy games Balance performance and power 90% Off or low speed, one channel active Device dark and in pocket or at bedside Maintain cell contact, receive texts, receive and display push notifications, sync mail, show clock, Longest battery life Performance Focus Best Performance under lowspeed power limits Power Focus

33 Introduction / Agenda LPDDR4 is different from earlier JEDEC Ways to connect LPDDR4 multiple channels How to handle 2-die and 4-die packages Dividing memory traffic across channels Floorplanning and making connections Using LPDDR4 low power features Key features of an LPDDR4 solution

34 Checklist Key features of LPDDR4 solution Max Operation frequency ( MT/s) Power, Performance, Bandwidth, Latency, Area Flexible Chip-Level Implementation Multi-Channel Implementation Use LPDDR4 power states Control of logical to physical address map Use frequency changing Change drive & termination with frequency Special Features ECC & reliability for Automotive, Temperature monitor & change, refresh flexibility,

35 Conclusions LPDDR4 multichannel architecture provides new opportunities for novel system architectures LPDDR4 multichannel architecture can improve performance and save power Consider performance, power, and complexity when considering your LPDDR4 architecture Questions?