IoT, Wearable, Networking and Automotive Markets Driving External Memory Innovation Jim Cooke, Sr. Ecosystem Enabling Manager, Embedded Business Unit

Transcription

1 IoT, Wearable, Networking and Automotive Markets Driving External Memory Innovation Jim Cooke, Sr. Ecosystem Enabling Manager, Embedded Business Unit 2016Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject to change without notice. All information is provided on an AS IS basis without warranties of any kind Statements Micron Technology, regarding Inc. products, All rights including reserved. regarding Information, their products, features, and/or availability, specifications functionality, are subject or compatibility, to change are without provided notice. for All informational purposes is provided only on and do AS not IS modify basis without the warranty, warranties if any, of any applicable kind. to any Statements product. regarding Drawings products, may not including be to scale. regarding Micron, their the features, Micron availability, logo, and all functionality, other Micron or trademarks compatibility, are the are provided property for of informational Micron Technology, purposes Inc. only All and other do trademarks not modify are the the warranty, property if any, of their applicable respective to any owners. product. Drawings may not be to scale. Micron, the Micron logo, and all other Micron trademarks are the property of Micron Technology, Inc. All other trademarks are the property of their respective owners.

2 Agenda: SPI Overview Applications Evolution Memory Solutions Packaging: Standard packages 24b BGA package flexibility Multi-Chip Packages (MCP) Quality / Reliability Cadence controller offerings 2

3 Applications Driving Requirements Market IoT Wearables Networking Automotive Application Performance Needs Density Needs MCU external memory Graphics, Icons Primary boot Instrument cluster, ADAS, IVI Medium to High Medium Medium to High Medium to High Wide Range High (128MB-1GB) Medium (32-256MB) Medium (32-256MB) 3

4 The Evolution of SPI 500 MB/s 450 MB/s SPI Interface Bandwidth 400 MB/s 350 MB/s Octal 400MB/s 300 MB/s 250 MB/s 200 MB/s 150 MB/s 100 MB/s 50 MB/s 0 MB/s 1.25MB/s 9MB/s Dual-I/O 18MB/s Quad (SDR) 40MB/s Twin-Quad 180MB/s Quad (DDR) 90MB/s SPI Dual-SPI Quad-SPI Twin Quad Octal # of Signals Clock (max) 75MHz 75MHz 180MHz SDR (90MHz DDR) 180MHz SDR (90MHz DDR) 166MHz SDR (200MHz DDR) Bandwidth (max) 9MB/s 18MB/s 90MB/s 180MB/s 400MB/s 4

5 Micron Solutions SPI NOR Flash SPI NAND Flash Product Quad SPI (N25Q, MT25Q) Twin-Quad (MT25T) Octal (MT35X) Quad MT29F1G High-Level Attributes Wide range of densities and packages Good in-between Product Highest performance Highest density for the lowest cost Read Performance 90MB/s 180MB/s 400MB/s 83MB/s* Density Range 32Mb to 2Gb (4MB-256MB) 256Mb to 1Gb (32MB-128MB) 256Mb to 2Gb (32MB-256MB) 1Gb to 8Gb VCC Range 1.7 to to 3.6V 1.7 to to 3.6V 1.7 to to 3.6V 1.7 to to 3.6V IT Temperature Range AT -40C to +85C -40C to +125C -40C to +85C -40C to +105C -40C to +85C -40C to +105C -40C to +85C -40C to +105C * Note: 83MB/s with on-die ECC disabled Per Micron product datasheets Emerging Performance, Density Solutions 5

6 Micron Read Performance Comparisons Transfer Rate (MBytes/sec) NOR and NAND Performance Comparisons Random Read Access Performance vs. Data Size x8 200MHz DDR Octal NOR (MT35X) x8 166MHz SDR Twin Quad Serial NOR (MT25T) x4 166MHz SDR/ 83MHz DDR Serial NOR (MT25Q) 1.8V x4 133MHz SPI NAND x8 NAND ONFI 3.0 x8 emmc 4.5 x8 emmc 5.0 Cache Line Fills + + Octal SPI NOR Highest Performance BOOT or Read time at 400MB/s Bit density 512Mb 1Gb 2Gb Byte density 64MB 128MB 256MB Time to read.16 sec.32 sec.64 sec Graphic image (65K colors) Pixel Size 1K x 1K 4K x 4K Byte density 2MB 34MB Time to read 5.2ms 88ms SPI NAND Highest Density 1Gb, 2Gb, 4Gb k 2k 4k 8k 16k 32k 64k 128k 256k 512k 1M 2M Bytes per Fetch

7 Applications Driving Requirements Market IoT Wearables Networking Automotive Application Performance Needs Density Needs MCU external memory Graphics, Icons Primary boot Instrument cluster, ADAS, IVI Medium to High Medium Medium to High Medium to High Wide Range High (128MB-1GB) Medium (32-256MB) Medium (32-256MB) Flash Technology that Best matches the Application Octal SPI NOR 400MB/s 32MB to 256MB SPI NAND 83MB/s 128MB to 1GB Octal SPI NOR 400MB/s 32MB to 256MB Octal SPI NOR 400MB/s 32MB to 256MB 7

8 Micron Octal: The fastest and lowest power NOR Flash Parallel NOR Flash High performance Fast boot Reliability Want reduced pin count/package size Octal SPI NOR (MT35X) Serial NOR Flash Reduced pin counts Simple PCB design Reliability Need more performance with same package 512Mb Quad-SPI MT25Q 512Mb Twin-Quad MT25T 512Mb Octal SPI NOR MT35X Bandwidth 90MB/s (90MHz, DDR mode) 180MB/s (90MHz, DDR mode) 400MB/s (200MHz, DDR mode) Initial Word Access Time 139ns (1.8V, 4-bit) 157ns (1.8V, 16-bits) 139ns (1.8V, 8-bit) 145ns (1.8V, 16-bit) 85ns (1.8V, 8-bit) 87.5ns (1.8V, 16-bit) Subsequent Word Access 6ns (4-bits) 24ns (16-bits) 6ns (8-bits) 12ns (16-bits) 2.5ns (8-bits) 5ns (16-bits) Package and Pins (Several other packages supported) 24-BGA (6x8mm) 6 Active Pins 24-BGA (6x8mm) 11 Active Pins 24-BGA (6x8mm) 11 Active Pins Energy Per Bit 41 pj/bit 41 pj/bit 28 pj/bit 5X THE PERFORMANCE, 4X FEWER PINS, 3X LESS ENERGY, AND 2X SMALLER PACKAGE * * Compared to Micron Page Mode Parallel NOR 8

9 MT35X (Octal) 9

10 NAND ECC Requirements and Trends 8b On-die ECC built into SPI NAND removes the ECC burden on the host controller 10

11 SPI NAND On-Die ECC 8 bit correction strength Auto-load page 0 on power up 11

12 Power (Typical/Max Current) 512Mb Quad-SPI MT25Q 512Mb Twin-Quad MT25T 512Mb Octal MT35X 1Gb SPI NAND MT29F1G Standby (ua) 55/ / / / 50 Deep Power Down (ua) 2/ 30 4/ 60 2/ 30 Read Random (ma) -/ 28 -/ 56 -/ 70 -/ 35 Energy Per Bit (pj/bit) * Program (ma) -/ 30 -/ 70 -/ 35 -/ 25 Erase (ma) -/ 30 -/ 70 -/ 35 -/ 25 Typical / Maximum 0.5X MAX STANDBY CURRENT VS. PAGE-MODE PARALLEL NOR AND ALSO HAS DEEP POWER DOWN MODE SAME STANDBY AND DEEP POWER DOWN CURRENT VS. QSPI SERIAL NOR DC CURRENT 1.8V/ INDUSTRIAL GRADE * NOTE: DOES NOT INCLUDE THE NAND PAGE READ TIME 12

13 Packaging

14 SPI Flash Package Options SPI NOR COMMON FOOTPRINT FOR ANY DENSITY SO8 4Mb DFN 6x5* 4Mb 128 Mb 256 Mb SPI NAND Packages Supported DFN 8x6 64Mb SO16W 64M 4 Gb 2 Gb

15 Single 24 ball BGA (5mm X 6mm) FOOTPRINT SUPPORTS QUAD SPI, TWIN-QUAD, OCTAL, SPI NAND Quad SPI (SPI NOR, SPI NAND) supported = Data = Control = Power = Ground Tech Note: TN25-08: October 7, 2016

16 BGA for Twin Quad (2C, 2S#) BGA for Octal SPI Package = Data = Control = Power = Ground MT25T512 Die0: C S# DQ3-DQ0 Die1: C S# DQ7-DQ4 Added DQS Vcc INT# (Optional) VPP (Optional) = Data = Control = Power = Ground MT25T 24 Ball BGA package MT35X 24 Ball BGA package October 7, 2016

17 Micron MCP Technology Advantage Reduces PCB board space vs. multiple discrete packages Established ecosystem/chip-set support Micron offers the industry s largest MCP portfolio utilizing our own silicon Discrete Discrete MCP Shared Pins, Reduced Ball Pitch, Smaller Package, Lower Cost October 7, 2016

18 MCP Technology Overview Contains at least two memory technologies NOR Flash + PSRAM Shared-bus: low ball count/shared signals/power delivery NAND/NOR Flash + LPDDR1/2 Multi-bus: separate Flash and RAM bus in single package MCP configurations: Non-Volatile Memory (NVM): stores Critical Boot & Application code, OS, and other key parameters Parallel NOR Flash stacked with a PSRAM or Low Power DRAM (LPDRAM) NAND Flash stacked with LPDRAM Volatile Memory (PSRAM/LPDRAM): stores temporary memory, high speed compared to Flash October 7, 2016

19 What is an e.mcp/e.pop? e.mcp is a Multi Chip Package including e.mmc and LPDDRx e.pop is an e.mcp in a PoP(Package on Package) design Benefits include 30-40% savings on board space through vertical stacking of several memory chips Minimize bill of materials for simplified manufacturing and cost savings High density, low power consumption, shortest interconnections possible Accelerated time to market through rapid integration of modules NAND MCP e.mmc POP emcp epop e.mmc LPDRAM SLC NAND LPDRAM Application Processor -Driver MLC NAND Controller LPDRAM Application Processor -Driver e.mmc LPDRAM Application Processor -Driver Application Processor -Driver Substrate Substrate Substrate Substrate Low cost smart phones Medical, Cameras, Connected Home Premium smart phones & Tablets Auto, Consumer, Connected Home Mid-to-Low cost smart phones Wearables, IoT, M2M, Medical, Telemetrics High-to-Mid cost wearables, Industrial, IoT

20 Micron: Industry s Broadest MCP Portfolio

21 MCP Package Examples 21

22 Quality / Reliability

23 Micron s NOR Flash Satisfies Auto Reliability & Temperature Needs QUALITY & RELIABILITY Temperature Range -IT -40 to +85 C -AIT/-AAT AIT: -40 to +85 C AAT: -40 to +105 C Qualification Spec Reference JESD47 AECQ100 Striving Towards Zero Defect Approach No Yes, according to AEC-Q100 (SYA, PAT,CHAR ) Material Selection for Eligibility to Automotive No Yes PPM Quality Agreement No Can be negotiated ISO/TS-Certified Fab and Assembly Location Not guaranteed Yes 8D for Failure analysis (including 5Whys) response Not guaranteed standard report Yes, according to rule SERVICE & SUPPORT PPAP Submission No Yes Supply Prioritization No Yes Buffer Stock/CMI/VMI No Can be negotiated Documentation Support (Questionnaire) Submission of Micron s Internal Qualification and Reliability Report under NDA Full Questionnaire Support Fab and Assembly Audit Support ISO 9001 (limited) ISO/TS (full) on roadmap fab and assembly 23

24 Micron is Your Long-Term Partner Product Longevity Program (PLP) Products For customers with application life cycles of 7 10+years Select DRAM, NAND, and NOR products Stability and longevity for mission-critical applications with extensive design-in or requalification requirements Minimum 10-year form, fit, function compatibility from the date of introduction (to the PLP program) Extended 2-year conversion timeline in case of part number change or discontinuance Micron is committed to supporting NOR Flash for the future Continued investment to drive manufacturing efficiency, supply, and cost reductions Micron is the ideal, one stop shop pure-play memory supplier Financially stable 5th largest semiconductor manufacturer and 3rd largest memory supplier in the world Not distracted by non-memory products such as MCUs Micron can provide all of your NOR Flash, NAND Flash, and DRAM memory needs 24

25 Cadence Controller IP

26 Cadence Quad/Octal SPI Controller and PHY IP Quad/Octal SPI Controller SoC Interfaces Benefits: Optimized for ease of integration Works across all technology nodes, 65nm and below Ease of I/O integration Optimized synthesis scripts Robust architecture SPI Control Logic Integrated digital DLL Soft RTL implementation for maximum flexibility Supports up to 4 devices SPI I/F Performance Device clock frequency up to 200MHz DDR Soft PHY XIP and boot support Protocols Octal / Twin Quad QSPI Supported Devices Single, Dual, Quad and Octal SPI Supports Micron Octal SPI and Twin-Quad SPI Programmable page / block sizes Direct and Indirect modes of operation Cadence Design Systems, Inc.

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