Low Power & High Bandwidth Memory Trend

Transcription

1 Low Power & High Bandwidth Memory Trend JEDEC Mobile & IOT Forum Copyright 2016 [ SK hynix / Sungmin(Sam) Park]

2 Where Do We Stand? SK hynix Developed the World s First Next Generation Mobile Memory: LPDDR4 Evolutionary Way SK hynix Developed the Industry s First Wide IO2 Mobile DRAM Revolutionary Way Source: link Source: link 溫故知新 By comprehending the ways of the past, we gain understanding of the future.

3 Evolutionary Way of Mobile DRAM Transition Year System Requirement Low Power & Small Form Factor LP & SFF + Increased Speed for various segments Quick transition from existing version Maximizing B/W w/ Low Power Memory Solution LPDDR 400Mbps LPDDR2 800/1066Mbps LPDDR3 1600/2133Mbps LPDDR4 3200/4266Mbps TCSR / PASR Low VDD/Q(1.8V) x32 Die Edge Simple Trainings 2bit prefetch Lower VDD/Q(1.2V) 4/2bit prefetch & N More Trainings 8bit prefetch Lower VDD/Q(1.1V) 2ch. X16 DQs on Edge Sophisticated Trainings 16bit prefetch

4 Bandwidth Trend of LPDDRx Mobile System s Bandwidth Trend w/ LPDDRx Spectrum of Mobile DRAM s Solution 6400 LPDDR5??? 3200 LPDDR4 25.6GBps LPDDR3 12.8GBps LPDDR2 6.4GBps LPDDR 3.2GBps Requirements of Mobile Systems Performance Enhancing performance, while meeting all other requirements, is the most desirable way. Power Form Factor Cost

5 Revolutionary Way of Mobile DRAM Transition Year System Requirement Providing 12.8GBps / Die Maximizing B/W Up to 68GBps w/ Low Power Memory Solution WIO SDR 200Mbps TCSR/PASR Low VDD/Q(1.2V) 4ch. X128 ubump DQs Simple CMOS signaling 1bit prefetch WIO2 800/1066Mbps Lower VDD/Q(1.1V) 8ch. X64 ubump DQs Simple CMOS signaling 4bit prefetch

6 Bandwidth Trend of WIOx WIO s Bandwidth Curve Example of WIO s SiP Ecosystem 2.5D 3D Logic Memory Interposer Memory Logic 6400 LPDDR5??? Substrate Substrate 3200 LPDDR4 25.6GBps DRAM Die 1600 LPDDR3 12.8GBps WIO3??? Logic Die 800 LPDDR2 6.4GBps WIO2 51.2GBps Bonding Packaging On Substrate Final Test (SiP test) Ship Final Product 400 LPDDR 3.2GBps Package substrate 200 WIO SDR 12.8GBps Foundry Company Memory Company OSAT Company SoC Company Which one will get an authority of the SiP process? Set Company

7 Future Mobile System Requirement 1. Performance 2. Power 3. Form Factor 4. Cost 5. Openness to Change of memory hierarchy Note: Stars indicate the relative comparison of each applications, with 3 stars representing those with the highest priority

8 Consideration 1. Performnace Evolutionary Way Revolutionary Way Effective in utilizing existing experiences. However, we are reaching the speed limit. Can we get more transition of IO speed? ( Mbps?) The obvious benefit of bandwidth increase. However, we are facing ecosystem challenges. Can we solve the ecosystem challenge? (Is the SiP only way?)

9 Consideration 2. Power Optimal definition of Fetch Size is required. (Page Size / Burst Length / DQ count) Mainly follows the Power = CV^2f*DQs equation. Minimizing each elements value will be important. More smarter way of optimizing refresh interval will be required as we face increasing die density.

10 Consideration 3. Balancing (btw performance & power) DQ Toggling power = C * V^2 * f * DQ counts Evolutionary Way Revolutionary Way Cmax (DQ) VDDQ f DQs (system) Cmax (DQ) VDDQ f DQs LPDDR3 1.8pF 1.2V ~2133M 64 LPDDR4 1.3pF 1.1V ~3200M 64 LPDDR4X TBD 0.6V ~4266M 64 WIO SDR V 400M 512 WIO V 1066M 512 WIO next????????? LPDDR5????? ~????M 64 The lowest values possible are required for the target IO speed. Continuous Increase Changing f * DQs relationship may require other optimal values. What will be the optimal f * DQs definition providing better ecosystem?

11 Consideration 4. Power (wearables) [Restrictions on Wearables] [Considerations for DRAM Definition] Battery Capacity(mAh) Power Profile (hr) 0 1,000 2,000 3, Capacity Minimal Can be charged During sleeping, driving, dining, meeting, + Extra Battery Operation Power Unit Fetch Size BL / DQ, Page Size) VDD target Operating Frequency Mostly used during working hours Goal: 24/7 working like typical watches with frequent wake-ups Standby Power Optimizing Refresh intervals : Charge time during DOU

12 Consideration 5. Form Factor Evolutionary Way Revolutionary Way Package on Package (FBGA) FBGA is the most favorable one, but pin speed increase may require other types of packaging method. Will there be more easier way of packaging like FBGA for WIO memory? Side by Side (FBGA) Silicon In Package w/ 3DIC Will 3DIC like concept be required for the better connection between memory & processor? 3DIC is the best way for making shortest path, but it requires complicated ecosystem issue.

13 Consideration 6. Cost Memory Cost PKG/ Test PKG/ Test PKG cost is targeted to be the same, but costs may increase due to high speed test. (~6Gbps) PKG/ Test Special Test & Packaging method may act as a cost adder. Die Die Small die cost adder is desirable due to minimized increase of pin count. Die Die cost adder is critical as it may require many IO pins. LPDDR4 Evolutionary way Revolutionary way

14 SK hynix TSV Technology SK hynix s 3DS Tech. Leadership SK hynix s HBM Tech. Leadership SK hynix 128GB are based on Through Silicon Via(TSV) technology SK hynix develops high speed TSV Memory chip SK hynix starts production of HBM DRAM Chip modules using 3D TSV

15 Consideration 7. Memory Hierarchy LPDDRx memory for Cost Saving & Capacity Increase WIOx memory for Performance, Low Power and Small form factor

16 Where Are We Heading For? Balancing all requirements across segments Performance Power Form Factor Cost