PI74FCT373T PI74FCT573T Octal Transparent Latches
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1 ctal Transparent Latches Fast CMS ctal Transparent Latches Features: PI74FCT373/573T are pin compatible with bipolar FAST Series at a higher speed and lower power consumption TTL input and output levels Low ground bounce outputs Extremely low static power Hysteresis on all inputs Industrial operating temperature range: 40 C to +85 C evice models available upon request Packaging: -pin TSSP (L) -pin SSP (H) -pin QSP (Q) -pin SIC (S) escription: Pericom Semiconductor s PI74FCT373T and PI74FCT 573T are 8-bit wide octal transparent latches designed with 3-state outputs and are intended for bus oriented applications. When Latch Enable (LE) is HIH, the flip-flops appear transparent to the data. The data that meets the set-up time when LE is LW is latched. When E is HIH, the bus output is in the high impedance state. Block iagram LE E
2 CTAL TRANSPARENT LATCHES PI74FCT373 Pin Configuration E N PI74FCT573 Pin Configuration E N PIN L P Q S -PIN L P Q S Vcc LE Vcc LE Pin escription Pin Name E LE N VCC Truth Table () Inputs utputs N LE E N H H L H L H L L X X H Z. H = High Voltage Level L = Low Voltage Level X = on t Care Z = High Impedance escription utput Enable Input (Active LW) Latch Enable Input (Active HIH) ata Inputs 3-State utputs Complementary 3-State utputs round Power 2
3 CTAL TRANSPARENT LATCHES Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature C to +50 C Ambient Temperature with Power Applied C to +85 C Supply Voltage to round Potential (Inputs & Vcc nly) V to +7.0V Supply Voltage to round Potential (utputs & / nly) V to +7.0V C Input Voltage V to +7.0V C utput Current... ma Power issipation W Note: Stresses greater than those listed under MAXI- MUM RATINS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. C Electrical Characteristics (ver the perating Range, TA = 40 C to +85 C, VCC = 5.0V ± 5%) Parameters escription Test Conditions () Min. Typ (2) Max. Units VH utput HIH Voltage VCC = Min., VIN = VIH or VIL IH = 5.0 ma V VL utput LW Current VCC = Min., VIN = VIH or VIL IL = 64 ma V VL utput LW Current VCC = Min., VIN = VIH or VIL IL = 2 ma (25Ω Series) V VIH Input HIH Voltage uaranteed Logic HIH Level 2.0 V VIL Input LW Voltage uaranteed Logic LW Level 0.8 V IIH Input HIH Current VCC = Max. VIN = VCC µa IIL Input LW Current VCC = Max. VIN = N µa IZH High Impedance VCC = MAX. VUT = 2.7V µa IZL utput Current VUT = 0.5V µa VIK Clamp iode Voltage VCC = Min., IIN = 8 ma V IFF Power own isable VCC = N, VUT = 4.5V 00 µa IS Short Circuit Current VCC = Max. (3), VUT = N 60 ma VH Input Hysteresis 0 mv Capacitance (TA = 25 C, f = MHz) Parameters (4) escription Test Conditions Typ Max. Units CIN Input Capacitance VIN = 0V 6 0 pf CUT utput Capacitance VUT = 0V 8 2 pf Notes:. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25 C ambient and maximum loading. 3. Not more than one output should be shorted at one time. uration of the test should not exceed one second. 4. This parameter is determined by device characterization but is not production tested. 3
4 CTAL TRANSPARENT LATCHES Power Supply Characteristics Parameters escription Test Conditions () Min. Typ (2) Max. Units ICC Quiescent Power VCC = Max. VIN = N or VCC µa Supply Current ICC Supply Current per VCC = Max., VIN = 3.4V (3) ma TTL HIH ICC Supply Current per VCC = Max., VIN = VCC ma/ Input per MHz (4) utputs pen VIN = N MHz E = N LE = VCC ne Bit Toggling 50% uty Cycle IC Total Power Supply VCC = Max., VIN = VCC (5) ma Current (6) utputs pen VIN = N fi = 0 MHZ 50% uty Cycle E = N VIN = 3.4V (5) LE = VCC VIN = N ne Bit Toggling VCC = Max., VIN = VCC (5) utputs pen VIN = N fi = 2.5 MHZ 50% uty Cycle E = N VIN = 3.4V (5) LE = VCC VIN = N Eight Bits Toggling Notes:. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at Vcc = 5.0V, +25 C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or N. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested. 6. IC =IQUIESCENT + IINPUTS + IYNAMIC IC = ICC + ICC HNT + ICC (fcp/2 + fini) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) H = uty Cycle for TTL Inputs High NT = Number of TTL Inputs at H ICC = ynamic Current Caused by an Input Transition Pair (HLH or LHL) fcp = Clock Frequency for Register evices (Zero for Non-Register evices) fi = Input Frequency NI = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 4
5 CTAL TRANSPARENT LATCHES PI74FCT373T Switching Characteristics over perating Range 373T 373AT 373CT 373T Com. Com. Com. Com. Parameters escription Conditions () Min Max Min Max Min Max Min Max Unit tplh Propagation elay CL = 50 pf ns tphl N to N RL = 500Ω tplh Propagation elay ns tphl LE to N tpzh utput Enable Time ns tpzl E to N tphz utput isable Time (3) ns tplz E to N tsu Setup Time HIH or ns LW, N to LE th Hold Time HIH or ns LW, N to LE tw LE Pulse Width (3) ns HIH Switching Characteristics over perating Range 573T 573AT 573CT 573T Com. Com. Com. Com. Parameters escription Conditions () Min Max Min Max Min Max Min Max Unit tplh Propagation elay CL = 50 pf ns tphl N to N RL = 500Ω tplh Propagation elay ns tphl LE to N tpzh utput Enable Time ns tpzl E to N tphz utput isable Time (3) ns tplz E to N tsu Setup Time HIH or ns LW, N to LE th Hold Time HIH or ns LW, N to LE tw LE Pulse Width (3) ns HIH Notes:. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation elays. 3. This parameter guaranteed but not production tested. 5
6 CTAL TRANSPARENT LATCHES Packaging Mechanical: -Pin TSSP (L) BSC Max SEATIN PLANE ENTES CNTRLLIN IMENSINS IN MILLIMETERS Packaging Mechanical: -pin QSP (Q) uage Plane MIN etail A REF BSC REF SEATIN PLANE.05 x etail A ENTES IMENSINS IN MILLIMETERS 6
7 CTAL TRANSPARENT LATCHES Packaging Mechanical: -Pin SSP (H) Max SEATIN PLANE BSC Max Min ENTES IMENSINS IN MILLIMETERS Packaging Mechanical: -pin SIC (S) x REF SEATIN PLANE BSC ENTES CNTRLLIN IMENSINS IN MILLIMETERS 7
8 CTAL TRANSPARENT LATCHES PI74FCT373T rdering Information rdering Code Package Code Speed rade Package Type PI74FCT373TL L Blank -pin TSSP PI74FCT373TQ Q Blank -pin QSP PI74FCT373TS S Blank -pin SIC PI74FCT373ATH H A -pin SSP PI74FCT373ATL L A -pin TSSP PI74FCT373ATS S A -pin SIC PI74FCT373ATQ Q A -pin QSP PI74FCT373CTH H C -pin SSP PI74FCT373CTL L C -pin TSSP PI74FCT373CTS S C -pin SIC PI74FCT373CTQ Q C -pin QSP PI74FCT373TH H -pin SSP PI74FCT373TL L -pin TSSP PI74FCT373TQ Q -pin QSP rdering Information rdering Code Package Code Speed rade Package Type Q Q Blank -pin QSP S S Blank -pin SIC PI74FCT573ATH H A -pin SSP PI74FCT573ATL L A -pin TSSP PI74FCT573ATS S A -pin SIC PI74FCT573ATQ Q A -pin QSP PI74FCT573CTH H C -pin SSP PI74FCT573CTL L C -pin TSSP PI74FCT573CTS S C -pin SIC PI74FCT573CTQ Q C -pin QSP Q Q -pin QSP Notes:. Thermal characteristics can be found on the company web site at Pericom Semiconductor Corporation
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MC1488, SN55188, SN75188 QUADRUPLE LINE DRIVERS
Meet or Exceed the Requirements of ANSI EIA/ TIA--E and ITU Recommendation V. Designed to Be Interchangeable With Motorola MC1 Current-Limited Output: ma Typical Power-Off Output Impedance: Ω Minimum Slew
PI3B3253. Description. Features. Pin Configuration (QSOP, TSSOP) Block Diagram. Pin Configuration (UQFN) Truth Table (1)
3.3V, Dual 4:1 Mux/DeMux NanoSwitch Features Near-Zero propagation delay 5Ω switches connect inputs to outputs Fast Switching Speed: 5.2ns max. Ultra Low Quiescent Power (0.2µA typical) Ideally suited
AT29C K (32K x 8) 5-volt Only CMOS Flash Memory. Features. Description. Pin Configurations
Features Fast Read Access Time - 70 ns 5-Volt-Only Reprogramming Page Program Operation Single Cycle Reprogram (Erase and Program) Internal Address and Data Latches for 64-Bytes Internal Program Control
PI6C182B. Precision 1-10 Clock Buffer. Features. Description. Diagram. Pin Configuration
Features Low noise non-inverting 1-10 buffer Supports frequency up to 140 MHz Supports up to four SDRAM DIMMs Low skew (
Rev. No. History Issue Date Remark
Preliminary 512K X 8 OTP CMOS EPROM Document Title 512K X 8 OTP CMOS EPROM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue June 17, 1998 Preliminary 1.0 Change CE from VIL to VIH
SSTL for DIMM Applications. SCBA014 December 1997
SSTL for DIMM Applications SCBA014 December 1997 1 Introduction The stub series-terminated logic (SSTL) interface standard is intended for high-speed memory interface applications and specifies switching
AT28C16. 16K (2K x 8) CMOS E 2 PROM. Features. Description. Pin Configurations
Features Fast Read Access Time - 150 ns Fast Byte Write - 200 µs or 1 ms Self-Timed Byte Write Cycle Internal Address and Data Latches Internal Control Timer Automatic Clear Before Write Direct Microprocessor
TIL311 HEXADECIMAL DISPLAY WITH LOGIC
SOLID-STATE HEXADECIMAL DISPLAY WITH INTEGRAL TTL CIRCUIT TO ACCEPT, STORE, AND DISPLAY -BIT BINARY DATA 7,6-mm (0.300-Inch) Character Height High Brightness Internal TTL MSI Chip With Latch, Decoder,
Description. Application. Block Diagram
3.3V PCI Express 3.0 2-Lane Exchange Switch Features ÎÎ8 Differential Channel (2-lane) Exchange ÎÎPCI Express 3.0 performance, 8.0 Gbps ÎÎBi-directional operation ÎÎLow Bit-to-Bit Skew: 10ps (between ±
Low Voltage 1.65 V to 3.6 V, Bidirectional Logic Level Translation, Bypass Switch ADG3233
Data Sheet Low Voltage. V to. V, Bidirectional Logic Level Translation, Bypass Switch ADG FEATURES Operates from. V to. V supply rails Bidirectional level translation, unidirectional signal path -lead
DATASHEET HCS109MS. Features. Pinouts. Description. Ordering Information. Radiation Hardened Dual JK Flip Flop. FN2466 Rev 2.
DATASHEET HCS109MS Radiation Hardened Dual JK Flip Flop FN2466 Rev 2.00 Features 3 Micron Radiation Hardened SOS CMOS Total Dose 200K RAD (Si) SEP Effective LET No Upsets: >100 MEV-cm 2 /mg Single Event
512K bitstwo-wire Serial EEPROM
General Description The provides 524,288 bits of serial electrically erasable and programmable read-only memory (EEPROM), organized as 65,536 words of 8 bits each. The device is optimized for use in many
LP621024E-I Series 128K X 8 BIT CMOS SRAM. Document Title 128K X 8 BIT CMOS SRAM. Revision History. AMIC Technology, Corp.
128K X 8 BIT CMOS SRAM Document Title 128K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue January 14, 2008 Preliminary 1.0 Final version release September 21, 2010
4bit LVDS Driver BU90LV047A. LVDS Interface ICs
LVDS Interface ICs 4bit LVDS Driver BU90LV047A Description LVDS Interface IC of ROHM "Serializer" "Deserializer" operate from 8MHz to 150MHz wide clock range, and number of bits range is from 35 to 70.
XR33193/XR33194/XR33195
3.3V, 20Mbps, TSOT23 RS-485/RS-422 Transmitters with ±15kV ES Protection escription The XR33193, XR33194, and XR33195 are a high performance RS-485/RS-422 driver family offered in a tiny TSOT23 package
SN54F38, SN74F38 QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS
SNF, SN7F SDFS0A MARCH 7 REVISED OCTOBER Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 00-mil DIPs description These devices contain four
COM L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/20/25. Programmable AND Array (44 x 132) OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL
FINAL COM L: H-5/7//5/25, -/5/25 IND: H-/5/2/25 PALCE22V Family 24-Pin EE CMOS Versatile PAL Device DISTINCTIVE CHARACTERISTICS As fast as 5-ns propagation delay and 42.8 MHz fmax (external) Low-power
A24C08. AiT Semiconductor Inc. ORDERING INFORMATION
DESCRIPTION The provides 8192 bits of serial electrically erasable and programmable read-only memory (EEPROM), organized as 1024 words of 8 bits each. The device is optimized for use in many industrial
AT24C01A/02/04/08/16. 2-Wire Serial CMOS E 2 PROM. Features. Description. Pin Configurations. 1K (128 x 8) 2K (256 x 8) 4K (512 x 8) 8K (1024 x 8)
AT24C01A/02/04/08/16 Features Low Voltage and Standard Voltage Operation 5.0 (V CC = 4.5V to 5.5V) 2.7 (V CC = 2.7V to 5.5V) 2.5 (V CC = 2.5V to 5.5V) 1.8 (V CC = 1.8V to 5.5V) Internally Organized 128
3.3V ZERO DELAY CLOCK BUFFER
3.3V ZERO DELAY CLOCK BUFFER IDT2309A FEATURES: Phase-Lock Loop Clock Distribution 10MHz to 133MHz operating frequency Distributes one clock input to one bank of five and one bank of four outputs Separate
TLC1549C, TLC1549I, TLC1549M 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
0-Bit-Resolution A/D Converter Inherent Sample and Hold Total Unadjusted Error...± LSB Max On-Chip System Clock Terminal Compatible With TLC549 and TLV549 CMOS Technology description The TLC549C, TLC549I,
A24C02. AiT Semiconductor Inc. ORDERING INFORMATION
DESCRIPTION provides 2048 bits of serial electrically erasable and programmable read-only memory (EEPROM), organized as 256 words of 8 bits each. The device is optimized for use in many industrial and
Low Voltage 1.65 V to 3.6 V, Bidirectional Logic Level Translation, Bypass Switch ADG3233
Low Voltage. V to. V, Bidirectional Logic Level Translation, Bypass Switch FEATURES Operates from. V to. V supply rails Bidirectional level translation, unidirectional signal path -lead SOT- and MSOP packages
NOT RECOMMENDED FOR NEW DESIGNS SINGLE SUPPLY QUAD PECL/TTL-TO-PECL
NOT RECOMMENDED FOR NEW DESIGNS Micrel, Inc. SINGLE SUPPLY QUAD PECL/TTL-TO-PECL FEATURES Quad PECL version of popular ECLinPS E Low skew Guaranteed skew spec TTL enable input Selectable TTL or PECL clock
PALCE16V8 Family EE CMOS 20-Pin Universal Programmable Array Logic
FINAL COM L: H-5/7/10/15/25, -10/15/25 IND: H-10/15/25, -20/25 PALCE16V8 Family EE CMOS 20-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS Pin and function compatible with all 20-pin
PI4IOE5V bit I 2 C-bus and SMBus low power I/O port with interrupt and reset
Features Operation power supply voltage from 2.3V to 5.5V 2-bit I 2 C-bus GPIO with interrupt and reset 5V tolerant I/Os Active Low interrupt output Active Low reset input Polarity inversion register Low
DUAL TTL-to-DIFFERENTIAL PECL TRANSLATOR
DUAL TTL-to-DIFFERENTIAL PECL TRANSLATOR FEATURES DESCRIPTION 300ps typical propagation delay
Distributed by: www.jameco.com -800-83-4242 The content and copyrights of the attached material are the property of its owner. SOLID-STATE HEXADECIMAL DISPLAY WITH INTEGRAL TTL CIRCUIT TO ACCEPT, STORE,
Description. Block Diagram DDC_SCL DDC_SDA AUX+ AUX- TB_Rx_1(p) TB_Rx_1(n) CA_DET_Out. CA_DET_Out
10.3Gbps Thunderbolt and DisplayPort Switch Features ÎÎSupports 5.4Gbps for DisplayPort 1.2 and 10.3Gbps for Thunderbolt Electrical Standard ÎÎSupports DP and DP++ Configuration ÎÎSupports AUX and DDC
ACE24AC02A1 Two-wire Serial EEPROM
Description The ACE24AC02A1 is 2048 bits of serial Electrical Erasable and Programmable Read Only Memory, commonly known as EEPROM. They are organized as 256 words of 8 bits (1 byte) each. The devices
PI4IOE5V bit I 2 C-bus and SMBus I/O port with reset. Description. Features. Pin Configuration
Features Operation power supply voltage from 2.3V to 5.5V 8-bit I 2 C-bus GPIO with interrupt and reset 5V tolerant I/Os Polarity inversion register Active LOW Reset Pin Low current consumption 0Hz to
SN74BCT756 OCTAL BUFFER/DRIVER WITH OPEN-COLLECTOR OUTPUTS
BiCMOS Design Significantly Reduces I CCZ ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C = 200 pf, R = 0) Open-Collector Outputs Drive Bus Lines or Buffer Memory
Description OUT0 1 OUTA1 OUTA1 2 OUTA2 3 OUTA3 OUTA4 OUTB1 6 OUTB2 7 OUTB2 OUTB3 OUTB4. All trademarks are property of their respective owners.
Features Maximum rated frequency: 133 MHz Low cycle-to-cycle jitter Input to output delay, less than 200ps Internal feedback allows outputs to be synchronized to the clock input Spread spectrum compatible
LY68L M Bits Serial Pseudo-SRAM with SPI and QPI
REVISION HISTORY Revision Description Issue Date Rev. 0.1 Initial Issued May.6. 2016 Rev. 0.2 Revised typos May.19. 2016 Revised the address bit length from 32 bits to 24 bits Oct.13. 2016 0 FEATURES GENERAL
2-Megabit (256K x 8) 5-volt Only CMOS Flash Memory AT29C020. Features. Description. Pin Configurations
Features Fast Read Access Time - 90 ns 5-Volt-Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 1024 Sectors (256 bytes/sector) Internal Address and Data Latches for
Features. (opt) A EN0 A EN1 A V CC5_EN A V CC3_EN MIC2563 B EN0 B EN1 B V CC5_EN B V CC3_EN
MIC2563A ual-slot /CardBus Power Controller General escription The MIC2563A dual-slot (Personal Computer Memory Card International Association) and CardBus power controller handles all PC Card slot power
Am27C128. Advanced Micro Devices. 128 Kilobit (16,384 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL
FINAL 128 Kilobit (16,384 x 8-Bit) CMOS EPROM Advanced Micro Devices DISTINCTIVE CHARACTERISTICS Fast access time 45 ns Low power consumption 20 µa typical CMOS standby current JEDEC-approved pinout Single
Am27C020. Advanced Micro Devices. 2 Megabit (262,144 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL
FINAL 2 Megabit (262,144 x 8-Bit) CMOS EPROM Advanced Micro Devices DISTINCTIVE CHARACTERISTICS Fast access time 70 ns Low power consumption 100 µa maximum CMOS standby current JEDEC-approved pinout Plug
1-Megabit (128K x 8) 5-volt Only Flash Memory AT29C010A. Features. Description. Pin Configurations
Features Fast Read Access Time - 70 ns 5-Volt Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 1024 Sectors (128 bytes/sector) Internal Address and Data Latches for
A24C64. AiT Semiconductor Inc. ORDERING INFORMATION
DESCRIPTION provides 65536 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 8192 words of 8 bits each. The is optimized for use in many industrial and commercial