SN74LVC1G07YZAR SINGLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT. description/ordering information

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1 vailable in the Texas Instruments NanoStar and NanoFree Packages Supports 5-V V CC Operation Input and Open-Drain Output ccept Voltages up to 5.5 V Max t pd of 4.2 ns at 3.3 V Low Power Consumption, 0 µ Max I CC ±24-m Output Drive at 3.3 V I off Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 00 m Per JESD 78, Class II ESD Protection Exceeds JESD V Human-Body Model (4-) 200-V Machine Model (5-) 000-V Charged-Device Model (C0) SN74LVCG07 SINGLE BUFFER/DRIVER WITH OPEN-DRIN OUTPUT SCES296K FEBRURY 2000 RESED SEPTEMBER 2002 DBV OR DCK PCKGE (TOP EW) NC GND V CC Y NC No internal connection YE OR YZ PCKGE (BOTTOM EW) GND DNU DNU Do not use Y V CC description/ordering information This single buffer/driver is designed for.65-v to 5.5-V V CC operation. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. The output of the SN74LVCG07 device is open drain and can be connected to other open-drain outputs to implement active-low wired-or or active-high wired-nd functions. The maximum sink current is 32 m. This device is fully specified for partial-power-down applications using I off.the I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. T 40 C to 85 C ORDERING INFORMTION PCKGE NanoStar WCSP (DSBG) YE (Lead) NanoFree WCSP (DSBG) YZ (Lead-free) Tape and reel Tape and reel ORDERBLE PRT NUMBER SN74LVCG07YER SN74LVCG07YZR TOP-SIDE MRKING _CV_ SOT (SOT-23) DBV Tape and reel SN74LVCG07DBVR C07_ SOT (SC-70) DCK Tape and reel SN74LVCG07DCKR CV_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YE/YZ: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments. PRODUCTION DT information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2002, Texas Instruments Incorporated POST OFFICE BOX DLLS, TEXS 75265

2 SN74LVCG07 SINGLE BUFFER/DRIVER WITH OPEN-DRIN OUTPUT SCES296K FEBRURY 2000 RESED SEPTEMBER 2002 FUNCTION TBLE INPUT H L OUTPUT Y H L logic diagram (positive logic) 2 4 Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 6.5 V Input voltage range, V I (see Note ) V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, V O (see Note ) V to 6.5 V Voltage range applied to any output in the high or low state, V O (see Notes and 2) V to 6.5 V Input clamp current, I IK (V I < 0) m Output clamp current, I OK (V O < 0) m Continuous output current, I O ±50 m Continuous current through V CC or GND ±00 m Package thermal impedance, θ J (see Note 3): DBV package C/W DCK package C/W YE/YZ package C/W Storage temperature range, T stg C to 50 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD POST OFFICE BOX DLLS, TEXS 75265

3 SN74LVCG07 SINGLE BUFFER/DRIVER WITH OPEN-DRIN OUTPUT SCES296K FEBRURY 2000 RESED SEPTEMBER 2002 recommended operating conditions (see Note 4) MIN MX UNIT VCC Supply voltage Operating Data retention only.5 V VCC =.65 V to.95 V 0.65 VCC H High-level input voltage VCC = 2.3 V to 2.7 V.7 VCC = 3 V to 3.6 V 2 V VCC = 4.5 V to 5.5 V 0.7 VCC VCC =.65 V to.95 V 0.35 VCC L Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 V VCC = 4.5 V to 5.5 V 0.3 VCC Input voltage V VO Output voltage V VCC =.65 V 4 VCC = 2.3 V 8 IOL Low-level output current 6 m VCC =3V 24 VCC = 4.5 V 32 VCC =.8 V ± 0.5 V, 2.5 V ± 0.2 V 20 t/ v Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 0 ns/v VCC = 5 V ± 0.5 V 5 T Operating free-air temperature C NOTE 4: ll unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCB004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PRMETER TEST CONDITIONS VCC MIN TYP MX UNIT IOL = V to 5.5 V 0. IOL = 4 m.65 V 0.45 VOL IOL = 8 m 2.3 V 0.3 IOL = 6 m 0.4 3V IOL = 24 m 0.55 IOL = 32 m 4.5 V 0.55 V II input = 5.5 V or GND 0 to 5.5 V ±5 Ioff or VO = 5.5 V 0 ±0 ICC = 5.5 V or GND, IO = 0.65 V to 5.5 V 0 ICC One input at VCC 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 Ci = VCC or GND 3.3 V 4 pf Co VO = VCC or GND 3.3 V 5 pf ll typical values are at VCC = 3.3 V, T = 25 C. POST OFFICE BOX DLLS, TEXS

4 SN74LVCG07 SINGLE BUFFER/DRIVER WITH OPEN-DRIN OUTPUT SCES296K FEBRURY 2000 RESED SEPTEMBER 2002 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure ) PRMETER FROM (INPUT) TO (OUTPUT) VCC =.8 V ± 0.5 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MX MIN MX MIN MX MIN MX tpd Y ns operating characteristics, T = 25 C V CC =.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V PRMETER TEST CONDITIONS UNIT TYP TYP TYP TYP Cpd Power dissipation capacitance f = 0 MHz pf 4 POST OFFICE BOX DLLS, TEXS 75265

5 PRMETER MESUREMENT INFORMTION (OPEN DRIN) SN74LVCG07 SINGLE BUFFER/DRIVER WITH OPEN-DRIN OUTPUT SCES296K FEBRURY 2000 RESED SEPTEMBER 2002 From Output Under Test CL (see Note ) RL RL S VLOD Open GND TEST tpzl (see Notes E and F) tplz (see Notes E and G) tphz/tpzh S VLOD VLOD VLOD LOD CIRCUIT VCC INPUT tr/tf VLOD CL RL V.8 V ± 0.5 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VCC VCC 3 V VCC 2 ns 2 ns 2.5 ns 2.5 ns VCC/2 VCC/2.5 V VCC/2 2 VCC 2 VCC 6 V 2 VCC 30 pf 30 pf 50 pf 50 pf kω 500 Ω 500 Ω 500 Ω 0.5 V 0.5 V 0.3 V 0.3 V Timing Input 0 V Input tw 0 V Data Input tsu th 0 V VOLTGE WVEFORMS PULSE DURTION VOLTGE WVEFORMS SETUP ND HOLD TIMES Input 0 V Output Control 0 V Output Output tplh tphl tphl tplh VOLTGE WVEFORMS PROPGTION DELY TIMES INVERTING ND NONINVERTING OUTPUTS VOH VOL VOH VOL Output Waveform S at VLOD (see Note B) Output Waveform 2 S at VLOD (see Note B) tpzl tpzh tplz VOL + V tphz VOLTGE WVEFORMS ENBLE ND DISBLE TIMES LOW- ND HIGH-LEVEL ENBLING VLOD/2 VOL VLOD/2 VLOD/2 V 0 V NOTES:. CL includes probe and jig capacitance. B. Waveform is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. ll input pulses are supplied by generators having the following characteristics: PRR 0 MHz, ZO = 50 Ω. D. The outputs are measured one at a time with one transition per measurement. E. Since this device has open-drain outputs, tplz and tpzl are the same as tpd. F. tpzl is measured at. G. tplz is measured at VOL + V. H. ll parameters and waveforms are not applicable to all devices. Figure. Load Circuit and Voltage Waveforms POST OFFICE BOX DLLS, TEXS

6 MECHNICL DT MPDS08E FEBRURY 996 RESED FEBRURY 2002 DBV (R-PDSO-G5) PLSTIC SMLL-OUTLINE 0, ,50 5X 0,30 0,20 M,70,50 3,00 2,60 0,5 NOM 3,00 2,80 3 Gage Plane 0, ,55 0,35,45 0,95 0,05 MIN Seating Plane 0, /G 0/02 NOTES:. ll linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. Falls within JEDEC MO-78 POST OFFICE BOX DLLS, TEXS 75265

7 MECHNICL DT MPDS025C FEBRURY 997 RESED FEBRURY 2002 DCK (R-PDSO-G5) PLSTIC SMLL-OUTLINE PCKGE 0,65 0,30 0,5 0,0 M 5 4,40,0 2,40,80 0,3 NOM 3 2,5,85 Gage Plane 0, ,46 0,26,0 0,80 0,0 0,00 Seating Plane 0, /D 0/02 NOTES:. ll linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. Falls within JEDEC MO-203 POST OFFICE BOX DLLS, TEXS 75265

8 MECHNICL DT MXBG00B UGUST 200 RESED MY 2002 YE (R XBG N5) DIE SIZE BLL GRID RRY 0,95 0,85 B 0,50 0,25 C,45,35 ÉÉ B 0,50,00 2 PIN INDEX RE 5X 0,9 0,5 0,05 M CB 0,05 M C 0,35 MX 0,50 MX 0,05 C SETING PLNE 0,5 C 0, /C 04/2002 NOTES:. ll linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. NanoStar package configuration. D. Package complies to JEDEC MO 2 variation E. E. This package is tin lead (SnPb). Refer to the 5 YZ package (drawing 42045) for lead free. POST OFFICE BOX DLLS, TEXS 75265

9 MECHNICL DT MXBG004 JNURY 2002 RESED PRIL 2002 YZ (R-XBG-N5) DIE-SIZE BLL GRID RRY 0,95 0,85 B 0,50 0,25 C,45,35 B,00 0,50 2 Pin Index rea 5X 0,9 0,5 0,05 0,05 M M C C B 0,35 MX 0,50 MX 0,5 C 0,0 0,05 C Seating Plane /B 03/2002 NOTES:. ll linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. NanoFree package configuration. D. Package complies to JEDEC MO-2 variation E. E. This package is lead-free. Refer to the 5 YE package (drawing ) for tin-lead (SnPb). NanoFree is a trademark of Texas Instruments. POST OFFICE BOX DLLS, TEXS 75265

10 IMPORTNT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. ll products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing ddress: Texas Instruments Post Office Box Dallas, Texas Copyright 2002, Texas Instruments Incorporated

SN54LVTH16374, SN74LVTH V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

SN54LVTH16374, SN74LVTH V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS Members of the Texas Instruments Widebus Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input