An Alternative Scheme of FOM Bit Mux with Pre-interleave

Transcription

1 An Alternative Scheme of FOM Bit Mux with Pre-interleave Tongtong Wang, Wenbin Yang, Xinyuan Wang IEEE 802.3bs 400 GbE Task Force

2 Background PMA options as in gustlin_3bs_04_0714 are: Bit Muxing, used in 802.3ba Orthogonal Multiplexing Block muxing There might be a complex line encoding that has a unique multiplexing method In this presentation, we provide an optimized choice of Orthogonal Multiplexing by pre-interleaving to relax the constraints on layout implementation and support any lane to anywhere feature. Page 2

3 Brief Introduction of FOM Bit Mux Orthogonal Multiplexing is a general approach to help performance, it is mature technology and already deployed to face correlate error applications. From previous analysis, we can see the improvement of coding gain by FOM bol mux and FOM bit mux against burst errors.* FOM bol mux vs. NonFOM bol mux FOM bit mux vs. NonFOM bit mux Some concerns raised about FOM for its constraints on layout of CDAUI as stated in wang_400_01a_0114, although we think implementation with this restriction is feasible. Can we have tradeoff between flexibility and performance if any lane to anywhere architecture is preferable? *refer to anslow_3bs_02_0714 Page 3

4 Optimize FOM Bit Mux with Pre-interleave 0 & lanes [3:0] 1 & lanes [7:4] Pre-interleave Electrical Lanes [3:0] Electrical Lanes [7:4] & lanes [11:8] Electrical Lanes [11:8] & lanes [15:12] Electrical Lanes [15:12] MAC/RS 400G PCS MAC/RS 400G PCS 1 st stage PMA[16:16] in PCS The same color lanes from sub- s distribute to different Mux/Demux group. Pre-interleave between different lanes PMA Interleave on bol/bit from different lanes to get data pattern on Electrical Lanes 1 st stage PMA[16:16] in Host Each electrical lane is multiplexed from all 4 sub-s. Bit mux Bit mux Each bit mux block based on 4/2 electrical lanes from different sub- Bit Bit mux Bit Bit mux mux Bit Bit mux mux 2 nd stage PMA[16:4/8] or PMA[8:4] in module Optical Module Bit mux Bit mux Each bit mux block based on 4/2 electrical lanes Bit Bit mux Bit Bit mux mux Bit Bit mux mux 2 nd stage PMA[16:4/8] or PMA[8:4] in module Optical Module PMD Medium MDI Does Pre-interleave require additional logic? PMD Medium MDI Page 4

5 Hardware Implementation of Pre-interleave Take TX logic for example, each encoder output parallel data bus according to 100Gbps throughput. RS1 Encoder bol lanes Serders interface 0 RS1 Encoder FOM Bit Mux with Pre-interleave 10b Serders interface 0 It is just different logic place and route option inside host ASIC to feature One Lane to one Serdes interface Or, Symbols from multiple Lanes to one Serdes interface RS2 Encoder RS3 Encoder Serders interface 4 Serders interface 8 Electical Lanes 0~15 RS2 Encoder RS3 Encoder Serders interface 4 Serders interface 8 Electical Lanes 0~15 No multiplexers involved No additional latency cost No additional area cost RS4 Encoder Serders interface 12 RS4 Encoder Serders interface 12 RX logic procedure is similar and operable on parallel logic. Only for logic illustration, not necessarily a physical register Page 5

6 RX Side: Alignment and Reorder Before De-interleave MAC/RS 400G PCS Each Output Lanes is bit mux by Lanes from different Sub-s PMD Medium MDI Bit mux Bit mux PMA Each bit mux block based on 4/2 electrical lanes Bit Bit mux Bit Bit mux mux Bit Bit mux mux Lanes [15:0] With different AM ID Pre-interleave on all Lanes and Output Electrical Lanes 1 st stage PMA[16:16] in Host Electrical lanes[15:0] is un-restrict route to any bit mux/demux group 2 nd stage PMA[16:4/8] or PMA[8:4] in module Optical Module Optical Module MAC/RS 400G PCS Lane0 Lane1 Lane2 Lane4 Lane5 Lane6 Lane8 Lane9 Lane10 Lane12 Lane13 Lane14 Lane3 Lane7 Lane11 Lane15 Each Input Lanes is bit De-mux to recovery Lanes By de-interleave Reorder Alignment Lock & Deskew PMA Bit Demux Bit Demux PMD Medium Bit Demux MDI Bit Demux Use alignment and reorder mechanism in RX side across all lanes as in 100GE. Page 6

7 Example: 2:1 Bit Mux with CDAUI-16 interface Data stream on16 electrical lanes is bit interleaved from different Sub-s by Pre-interleaving. Use 16 electrical lanes on CDAUI-16 and multiplex to 50G optical lanes. As bit pattern on each electrical lanes is from 4 different sub-s, any two electrical lanes can bitmux together. NO layout restriction on CDAUI interface. Use AM Lock/Alignment and Reorder on RX side to restore all lanes before de-interleave; The worst case of performance is showed in RED block in right diagram, when bits from same are aligned. Bit mux group pattern depends on different skew and trace implementation 4X25Gbps Electrical lanes after pre-interleave Egress PCS/PMA Elane 0Elane1 Elane2 Elane3 TX:CDAUI-16 Two 50Gbps Optical Link Bit Mux 2:1 Page 7

8 Error Symbol Number and Probability - Worse case Orthogonal Bit Mux 2:1 with Pre-interleave Burst Error Pre-interleaved Electrical Lanes Adjacent bits from the perspective of one codeword A bl bit burst corrupts x bits on each bol lane. x = ceil bl%8 8 + floor( bl 8 ) This x corrupted bits cause erroneous bols as in following equation. x x% m1 ceil( ) 1; of prob1 ErrorSymbolNumber m m x ceil( ); of prob2 1 prob1 m Total number of erroneous bol is the sum of error bols from 2 lanes. ErrorSymbol Number error_number error_number ; of prob Prob Prob lane1 lane2 lane1 * lane2 Page 8

9 Comparison of Error Symbol Number and Probability Number of erroneous bols caused by burst errors for different PMA muxing methods are listed. Table 1: Non FOM bitmux (worst case) Table 2: PreInterleave bitmux(worst case) Table 3: FOM bitmux(no worst case) Burst Length E rroneous Probability (bits) bols % % 2 90% 4 4 1% 3 18% 2 81% 5 4 6% 3 38% 2 56% 6 4 4% 3 32% 2 64% Burst Length E rroneous Probability (bits) bols % % 2 90% % 3 18% 2 81% % 3 26% 2 72% % 3 32% 2 64% Burst Length Erroneous Probability (bits) bols % 3 2 5% 1 95% % 1 90% 2 15% 1 85% 2 20% 1 80% Pre-interleaving method has better resistance of burst errors than NonFOM bitmux(random muxing), but worse than FOM bitmux. The advantage of Pre-interleaving method is supporting any lane to anywhere. Page 9

10 performance of FOM 2:1 Bit Mux with Pre-interleave FOM bit mux with Pre-interleave require ~0.3dB/0.25db CG Penalty compare to KR4/KP4 in burst error application Page 10

11 Summary Pre-interleaving gives another way to do FOM bit mux. It can support any lane to anywhere routing with compromised coding gain. We have tradeoff between performance and flexibility for FOM bit mux. For BER objective 1e-13 RS(528,514) RS(544,514) Any to any conncetion Coding Gain BERin Coding Gain BERin Random Errors E E-04 Yes 1:2 FOM bol mux E E-04 No, Partial lane order required 1:2 FOM bit mux E E-04 No, Partial lane order required 1:2 NON FOM bol mux E E-04 Yes, as.bj 1:2 FOM bit mux with Pre-interleave E E-04 Yes 1:2 NON FOM bit Mux E E-05 Yes Gray coding in PAM4 could limit correlated error to one bit per PAM4 bol and help to improve performance in bit mux. We will investigate it in the future. Page 11

12 Thank you