40-Gbps and 100-Gbps Ethernet in Altera Devices
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1 40-Gbps and 100-Gbps Ethernet in Altera Devices Transceiver Portfolio Workshops 2009
2 Agenda 40/100 GbE standards 40/100 GbE IP in Altera devices Stratix IV GT FPGA features and advantages Altera standards compliance and validation 2
3 40/100 GbE Standard Functional Layer Structure, Altera Solution Scope, and Key Skew Test Points Altera device Altera device Soft IP Soft IP Hard IP Hard IP PHY Optical module/ copper media Optical modul/ copper media 40 GbE, 40GBASE-R 100 GbE, 100GBASE-R 3
4 40/100 GbE Standard Functional Layer Structure and Altera Solutions Scope Altera device Altera device Soft IP Soft IP Hard IP Hard IP PHY Altera device or an ASSP Altera device or an ASSP Optical module/ copper media Optical module/ copper media 40 GbE, 40GBASE-R 100 GbE, 100GBASE-R 4
5 40/100 GbE MAC in Altera FPGA lanes x Gbps Interlaken TM or PP device. Altera Stratix IV GT FPGA single-chip MAC device Sarance Technologies Interlaken User logic IP from MorethanIP or Sarance Technologies 40G/100G MAC 40G/100G PCS 4 or x 10.3-Gbps XLAUI (40 GbE) 10 x 10.3-Gbps CAUI (100 GbE). 40/100 Gbps CFP or QSFP module System manager (host controller) Soft core Hard silicon 5
6 Altera 40/100GbE Solution Advantage vs. Competitor Altera Stratix IV GT FPGA IP from MorethanIP or Sarance Technologies 4 x 10.3-Gbps XLAUI (40 GbE) / 10 x 10.3-Gbps CAUI (100 GbE) 40G/100 GbE MAC 40G/100 GbE PCS 4 or /100 Gbps CFP or QSFP module Competitor FPGA IP from MorethanIP or Sarance Technologies 4 x 10.3-Gbps XLAUI (40 GbE) / 10 x 10.3-Gbps CAUI (100 GbE) 4 x 10.3 Gbits (40 GbE) / 10 x 10.3 Gbits (100 GbE) 40G/100 GbE MAC 40G/100 GbE PCS 8 or RXAUI multiplexer and 10-Gbit SFI PHY. X 8 or 20 X 3 or 5 RXAUI multiplexer and 10-Gbit SFI PHY 40/100 Gbps CFP or QSFP module 6
7 Altera 40/100GbE Solution Advantage vs. Competitor cont. 100 GbE Resource usage: SERDES and power External RXAUI multiplexer-phy power, cost System-side Interlaken Altera 100 GbE MAC solution: The only single-chip solution available NOW The most optimal solution with integrated 11.3-Gbps SERDES Substantial power savings Higher reliability due to lower system power, fewer components Board space savings * Source: Xilinx Virtex-5 TXT website Altera 7 Competitor 10 Gbps 6 Gbps 171 mw * 200 mw 10 channels 20 channels 1.71 W * 4.0 W 0 W High power $0 $$$ 6 or 5 Gbps 6 or 5 Gbps Gbps * Gbps 20 or 24 channels 20 or 24 channels 2.70 W * 4.00 W Total 4.60 W 8++ W
8 40/100 GbE PCS IP Example Implementation XLGMII/CGMII to/from MAC TXD 40G&100G: 384-b 100G: 512-b 40G: 256-b TXC (16/64-b) MAC_CLK > 260.4/ > 225 MHz /200 MHz 40/100 GbE PCS soft IP Tx clock compensation FIFO 64b/66b encoder X 58 scrambler MLD Tx: Striping, alignment block insertion, block distribution (Ext) REF_CLK( / MHz) Tx gearbox MHz 20x 5-Gbit FEC Enc PCS local loopback Tx AN ALTGX PLL Altera PMA service interface MHz RXD RXC (16/64-b) (RxFifoRdClk) Rx clock comp FIFO and rate matcher 64b/66b decoder X 58 descram. MLD Rx: Physical to virtual lane demultiplexer, alignment block detection and removal, VL alignment and re-order, VL multiplexer Rx 66-b lane sync and gearbox, and phasecomp FIFO 20x 5G FEC Dec Rx AN MHz and 4/10 x RX_CLK s Avalon -MM internal management interface Mgmt. bus control and registers module... BER monitor To/from ALTGX (PMA) Datapath Control/Clk Mgm t Reconfig_Block 8
9 40/100 GbE PCS IP Features Supports Altera Stratix IV GT and GX FPGAs Compatible with the latest IEEE 802.3ba (40/100 GbE) PCS spec Will follow the IEEE 802.3ba standard when ratified General and basic minimum features Each IP provider s product can have additional and differentiating features Supports 40 Gbps and/or 100 Gbps data rates in full duplex 64b/66b encoder and decoder X 58 scrambler and descrambler MLD inverse multiplexer (striping logic), alignment marker insertion, de-skew, reorder, alignment logic and multiplexer logic Error detection and monitoring Interfaces PMA to Ethernet network: XLAUI and CAUI, 4/10 x 10.3 Gbps to support 40-Gbps and 100-Gbps pluggable modules PCS to PMA: 160/ Mbps PCS to MAC: IP provider specific XLGMII or CGMII Management (configuration and status) interface 9
10 40/100 GbE MAC IP Example Implementation 40/100 GbE MAC soft IP TXD 40G and 100G: 384-b 100G: 512-b 40G: 256-b Tx control Optional Tx FIFO Tx MAC control module XLGMII/ CGMII transmit interface MAC_CLK 40G and 100G: > 260 MHz 100G: > 225 MHz 40G: > 200 MHz Flow control Reconciliation sub-layer To/from PCS IP To/from internal system SYS_CLK RXD Rx control Rx FIFO Rx MAC control module XLGMII/ CGMII receive interface Internal management interface Mgmt. bus control, registers, and statistics module MDIO controller MDIO-MDC management interface Datapath Control/Clk Mgm t 10
11 40/100 GbE MAC IP Features Supports Altera Stratix IV GT and GX FPGAs Compatible with the latest IEEE 802.3ba MAC and reconciliation sub-layer specs Will follow the IEEE 802.3ba standard when ratified General and basic minimum features Each IP provider s product can have additional and differentiating features Supports 40 Gbps,100 Gbps, or 40/100 Gbps data rates in full duplex (IP vendor specific) CRC-32 generation, insertion, and checking Preamble, SFD insertion, and deletion Maximum frame length (up to jumbo frame) Dynamic IPG for WAN and deficit idle counter (DIC) Statistics counters Interfaces Internal system: IP vendor specific 40Gb: higher than Mbps; 100Gb: higher than Mbps; 40Gb: 200 Mbps, 100Gb: higher than 225/312.5 Mbps IP management (configuration and status) interface PHY management, IEEE compliant MDIO-MDC serial link (IP vendor specific) 11
12 IEEE /100 GbE PHY Skew Limits Skew points Maximum skew variation (ns) a Maximum skew for 40GBASE-R PCS lane (UI) b Maximum skew for 100GBASE-R PCS lane (UI) c Altera Stratix IV GT FPGA and IP skews (prelim.) SP1 29 ~299 ~ UI SP2 43 ~443 ~222 N/A SP3 54 ~557 ~278 N/A SP4 134 ~1382 ~691 N/A SP5 145 ~1495 ~748 N/A SP6 160 ~1649 ~824 N/A At PCS receive 180 ~1856 ~928 40/100 GbE PCS: 1856/928 UI a The skew limit includes 1 ns allowance for PCB traces that are associated with the skew points b Note that for 40GBASE-R, 1 UI is equal to ps at PMD lane signaling rate of GBd c Note that for 100GBASE-R, 1 UI is equal ps at PMD lane signaling rate of GBd Source: IEEE 802.3ba Draft
13 IEEE /100 GbE PHY Skew Variation Limits Skew points Maximum skew variation (ns) Maximum skew variation for GBd. PMD lane (UI) a Maximum skew variation for GBd. PMD lane (UI) b Altera Stratix IV GT FPGA and IP skews (prelim.) SP1 0.2 ~2 SP2 0.4 ~4 ~10 N/A SP3 0.6 ~6 ~15 N/A SP4 3.4 ~35 ~88 N/A SP5 3.6 ~37 ~93 N/A SP6 3.8 ~39 N/A At PCS receive 4 ~41 a Note that for 40GBASE-R, 1 UI is equal to ps at PMD lane signaling rate of GBd b Note that for 100GBASE-R, 1 UI is equal to ps at PMD lane signaling rate of GBd Source: IEEE 802.3ba Draft
14 IEEE 802.3ba 40 or 100GBase-R Block Diagram Key Test Points and Test Criteria Measured characteristics Jitter generation Vod Measured characteristics Jitter tolerance Vid Altera or another device Transmit compliance point Receive compliance point Altera or another device MAC PCS PMA XLAUI/CAUI PMA channel PCS MAC Receive compliance point Transmit compliance point Soft core Hard silicon 14
15 IEEE /100 GbE PHY Transmit Characteristics 15 Source: IEEE 802.3ba Draft 1.2
16 IEEE /100 GbE PHY Receive Characteristics Source: IEEE 802.3ba Draft
17 40/100 GbE Validation Verification plan with Stratix IV GT FPGA Device characterization tests for compliance with 40GBASE-R and 100GBASE-R PMA (XLAUI and CAUI) latest specifications Interoperability tests ( ) using Stratix IV GT FPGA development kit QSFP and CFP optical modules Copper cable and connectors Third-party 40/100 GbE products University of New Hampshire (UNH) validation tests for 40/100 GbE PMA, PCS, and MAC when tests are available 17
18 40/100 GbE IP for Stratix IV GT FPGA Altera IP partner Ethernet IP Core frequency and MAC system bus width Resource usage KLE/registers (K)/memory bits IP availability MorethanIP 40/100 GbE MAC > MHz, 384 bits 20.4K LEs/18K/0 or 48 Kbits Now MorethanIP 40/100 GbE PCS > MHz, 384 bits 30K LEs/31.8K/42 Kbits Now Sarance Technologies 40 GbE MAC + PCS 200 MHz, 256 bits 25K LEs Now Sarance Technologies 100 GbE MAC + PCS MHz or > 225 MHz, 512 bits 60K LEs for non-segmented bus, 67K LEs for segmented * bus Now * Segmented bus: Current frame s EOP and next frame SOP can appear on the same word 18
19 Thank You
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