Pessimism removal in a system analysis of a 28Gbps SERDES link

Transcription

1 Pessimism removal in a system analysis of a 28Gbps SERDES link SERDES system modeling analysis from silicon macro to connector Olivier BAYET & Massimo Cereda, STMicroelectronics May 11 th 2016 from 9:50 to 10:10

2 Introduction 2 Networking processor integration and performance increase: Pushing the limits of the serial interface data transfer rates. Requiring new techniques for the optimization of the system to ensure signal integrity of the serial link. This presentation: Shows the limitation of the conventional approach for modeling. Proposes a solution to remove pessimism for simulation. Highlights the advantages and drawbacks of both solutions.

3 Context - SERDES 3 In networking applications, the serial link (based on SERDES macro) is the standard interface to exchange data between different devices. What is a SERDES? A SERializer- DESerializer which provides 2 differential pairs to input and output differential signals from and to the external environment. Enables bidirectional data exchange at different data rate depending on standards SERDES standards for 25-28Gbps links: IEEE 802.3: IEEE802.3bj 100GBASE-CR4 CEI-3.1: CEI-25G-LR, CEI-28G-SR or CEI-28G-MR

4 Context - System 4 A SERDES macro is integrated in a silicon device which is part of a package building a component. The component is integrated on a board which is linked to the external environment with a connector and a cable: SERDES macro on silicon die TP TP TP TP Package Board Connector TP Cable Case 1 Case 2 TP = Test Point

5 Modeling & simulation approaches 5 Study case: A test vehicle of a 28Gbps SERDES macro in ST 28FD-SOI technology node. A silicon device embedding a SERDES macro of 8 data slices & 1 clock slice. A BGA package using a laminate substrate built with low loss dielectric material. A test board with connectors. Modeling & simulation using the ANSYS Electronic Desktop 16.2 tool suite with HFSS, HFSS 3D Layout and Circuit Design. Supported standards: CEI-28G-MR. 2 approaches: Conventional method: S-parameter stitching. Holistic method: Merged layout.

6 Balls Bumps Balls Conventional method - S-parameter stitching Description Considers each contributor to the system as independent. 3D views in ANSYS HFSS 6 Modeling of each element separately. The resulted models are stitched together to create the system schematic. The created system is then analyzed. Package Connectors Board + Connector

7 Conventional method - S-parameter stitching Results Differential return loss: Package 7 RX1 & TX1 at die bump & package ball Differential return loss: Board 4.5dB margin on TX 6.8dB margin on RX RX1 or TX1 at package ball & connector

8 Conventional method - S-parameter stitching Results Case 1: Differential return loss: Package + Board + Connector 8 Package model Board + connector model Increasing loss compared to package or board alone RX1 at die bump & connector 4dB margin on RX

9 Conventional method - S-parameter stitching Results Case 2: Differential return loss: Die + Package + Board + Connector 9 SERDES die model Package model Board + connector model RX1 & TX1 at connector Violation on TX1

10 Bumps Holistic method Merged layout Description 10 Builds the system at layout level Corresponds to a merge of the layouts from the different contributors 3D view in ANSYS HFSS Connectors Modeling of a single element The resulted model is directly used to analyze the system. Package + Board + Connector

11 Holistic method Merged layout Results Case 1: Differential return loss: Package + Board + Connector 11 RX1 at die bump & connector Model stitching Merged layout Worst case improved by ~2dB

12 Holistic method Merged layout Results Case 2: Differential return loss: Die + Package + Board + Connector SERDES die model Package + board + connector model 12 Worst case improved by ~2dB RX1 & TX1 at connector TX1 now passing

13 Result summary 13 Case 1: Package + board + connector Conventional Merged layout Return loss margin 4dB 6dB Case 2: System with die + package + board + connector Conventional Merged layout Return loss margin Violation 2dB Conventional Merged layout Package Package + Board + Combining Board + Connector model Connector Setup time 30min 1h 30min 1h30 Run time 2h 2h40 1min 5h RAM 32GB 20GB - 32GB Could be in // Package Conventional Board + Connector Combining model Merged layout Package + Board + Connector Combining model Setup time 30min 1h 35min 1h30 15min Run time 2h 2h40 2min 5h 2min RAM 32GB 20GB - 32GB - Could be in // Conventional approach for design update loops & Merged layout approach for final analysis

14 Simulation vs Measurement 14 Partial correlation done thanks to measurement of test traces on board and comparison with simulation of the same setup. Board only Short trace: 44mm Simulation Measure Differential return loss

15 Simulation vs Measurement 15 Partial correlation done thanks to measurement of dedicated board and comparison with simulation of the same setup Board only Long trace: 90mm Simulation Measure Differential return loss

16 Conclusion 16 The study confirms the need to take into account not only the package, but at least a piece of the board when studying a SERDES link. Conventional approach: Enables quick setup and analysis, with flexibility to change models, Leads to some pessimism in the results due to model connectivity. Holistic approach: Defines accurately the physical interface between the layouts, Requires mature layout and more computing resources, Allows to go from a failing system simulation to a passing one without layout updates Switching from conventional to holistic method reduces the risk of redesign or overdesign as well as extra cost to meet specifications

17 17 Thanks Any questions?