A Utilization Aware Robust Channel Access Mechanism for Wireless NoCs

Transcription

1 A Utilization Aware Robust Channel Access Mechanism for Wireless NoCs Sri Harsha Gade *, Sidhartha Sankar Rout *, Mitali Sinha *, Hemanta Kumar Mondal, Wazir Singh * and Sujay Deb * * Department of ECE, Indraprastha Institute of Information Technology Delhi, New Delhi, India CNRS Lab-STICC, University of Southern Brittany, Lorient, France Abstract Wireless Network-on-Chip (WNoC) has been proposed to overcome long-distance communication bottlenecks of wired NoCs. Token passing mechanism has generally been adapted to allocate the wireless channel among Wireless Interfaces (WIs). In this work, we propose a comparator based controller to provide a flexible and efficient channel allocation scheme. It utilizes a comparator attached to the antenna, along with modifications to header flit to perform channel allocation along with power gating WIs to save energy. Evaluation of proposed scheme on CPU/GPU system shows 53% reduction in token passes and 9% energy saving as compared to timer based approach. Keywords WNoCs, Channel access mechanism, Power gating I. INTRODUCTION Network-on-Chip (NoC) is the enabling technology for interconnecting tens and hundreds of cores on a single chip in Chip Multiprocessors (CMPs) for achieving high performance computing [1][2]. Wireless NoCs (WNoCs) further improve the performance by augmenting wired NoCs with low latency, low energy wireless links to overcome their communication bottlenecks. Traditional wired NoCs do not scale well to large system sizes due to the high latency and energy in transferring data over long distances using wired links. WNoCs overcome this by few optimally placed Wireless Interfaces (WIs) that communicate over long distances with low latency to improve the performance significantly. WIs, in general, are optimized to be placed far apart and are used only for long distance communication. Besides providing low latency and low energy communication, wireless links also offer the broadcast capability and are compatible with existing CMOS processes. Many WNoC architectures have been proposed with different wireless link designs, channel implementations, performance and overheads [3][4][5][6][7]. Though significant advances have been made, WNoCs still face several challenges before their implementation becomes feasible and ubiquitous. The wireless channel design, sharing and allocation among different WIs, along with high power consumption are two such major challenges of WNoC implementations. On-chip wireless links, in general, adopt single channel communication to keep WI overheads to a minimum and hence require a mechanism to allocate and share the channel judiciously with each WI. Even with multi-channel implementation, it is not feasible to allocate separate channel for each transmission and the channels must be shared among the WIs. Token passing mechanism [8][9][10] [11][12], in general, has been adopted to provide access of wireless channel and to eliminate the overheads associated with centralized controllers. Centralized access control mechanisms have access to global information about all WIs, but incur significant overheads to transfer control signals. Token passing control performs efficiently as compared to centralized mechanisms, but there are still several issues with their current implementations. Most existing implementations of token passing use a timer based approach [9][12] to determine passing of token from one WI to another WI. Though this approach is simple, it is not flexible to accommodate different requirements of WNoCs. Firstly, data packets, even in homogeneous NoCs, vary in the number of flits and secondly, the load at each WI varies considerably with time. Hence, a fixed timer based token passing does not efficiently accommodate the varying packet size and WI utilization scenarios, leading to inefficient use of the channel. This further becomes a critical limitation in WNoCs for heterogeneous system architectures like [13]. In heterogeneous architectures, different computing subsystems have different latency and bandwidth requirements, leading to an even skewed WI channel access requirement and a simple timer based access control method does not cater to this. To overcome the limitations of existing token passing mechanisms, we propose a comparator based controller design that performs channel allocation to different WIs. The comparator in the proposed controller is attached to the antenna in WI and pre-processes the transmitted data to control channel allocation to the WIs. In addition to channel allocation, the comparator based controller also controls the power gating operation to reduce the power consumption in WIs. WIs, not actively involved in transmission, can be power gated to significantly reduce their leakage energy [14][15][16]. For channel allocation, we append additional information in the packet header transmitted over wireless links. This information and comparator based controller, not only perform channel allocation, but also help set additional features like channel access time, channel access priority, making the proposed mechanism robust and applicable to most scenarios. The main contributions of the work are: 1. A comparator based controller for channel allocation and power gating for wireless links in WNoCs. 2. Header flit modifications for packets to control channel allocation, access time and perform power gating. 3. Detailed implementation of controller and performance evaluation of the proposed mechanism in WNoCs. II. COMPARATOR BASED CONTROLLER In this section, we describe the comparator based controller design for channel allocation mechanism of the proposed work.

2 BR BR HR BR HR BR BR BR BR BR BR HR BR HR BR BR Regular Links Wireless Links Wired inputs RX LNA Demodulator Deserializer I/P Wireless Port Buffer Header Decoder A. System Architecture The WNoC topology, shown in Fig. 1, augments 2D wired mesh topology with single hop, long-range wireless links, where WIs are used for long distance communication. The placement of the WIs in the topology is obtained using a simulated annealing based optimization technique adopted from [3]. The WNoC topology consists of Base Routers (BRs) and few Hybrid Routers (HRs) that integrate WIs with BR components. Each BR is a five port, fully connected wired router and includes wired I/O ports, buffers, crossbar, Route Computation (RC) unit, and Switch Allocator (SA). It communicates with the neighboring routers using wired links. HR router, along with BR components, also contains WI to convert packet data between digital and RF domains. It is comprised of serializer/deserializer, modulator/demodulator, power amplifier and LNA components. A single antenna is used to transmit and receive the data and the wireless channel is shared between all WIs. A comparator based controller is integrated with each WI to perform channel allocation and power gate the WI to reduce energy consumption. B. Comparator based Channel Allocation The comparator based controller design for performing channel allocation in the proposed work is shown in Fig. 2. The comparator is attached to the antenna and processes the RF signal as it is received over the channel. A pattern matching RC VC1 VCn VC1 VCn Hybrid Router Comparator based Controller Base Router Base Router TX PA Modulator Serializer O/P Wireless Port Buffer Arbiter SA Crossbar fabric Fig. 1. WNoC Topology and Hybrid Router with Wireless Interface Comparator LNA Demodulator PG Switch Demux Select Enable Deserializer I/P Buffer WI Address 0 X X X Pattern Matching Fig. 2. Comparator based Controller for Channel Allocation and Power Gating Wired outputs Bits transmitted serially over wireless link Bits to compensate for Actual packet data to be wakeup latency transmitted t 0 Dummy Header Payload Bits Dummy Bits circuit sits at the output of demodulator, which demodulates the signal and converts it to serial digital data stream before it is deserialized and written to the router input buffers. A Demux circuit controls the data stream to switch between the pattern matching circuit and input buffers. To perform channel allocation and determine appropriate receiver for a transmission and arbitration control, we modify the header flit of the packet transmitted over the wireless link. The modified packet stream is shown in Fig. 3. The dummy bits added at the start of packet transmission are to compensate for wake-up latency associated with power gating (explained in section III). For channel allocation, a unique WI Address is assigned to each WI and the WI Address of both source and destination WI are added to the header flit. These addresses are different from the actual source and destination addresses of the packet, which are also present in the header flit. The source WI Address is used to determine the arbitration and token passing, while the destination WI Address is used to resolve packet destination once WI transmission starts. Once a WI initiates a transmission, the transmitted signal is received at all WIs and the associated comparator detects a valid received signal. Upon the detection of valid signal and receiving of header flit, the source and destination WI Address bits are processed by pattern matching circuit. At each WI, the received source WI Address is matched with the address of WI that comes before itself in the arbitration. If there is a mismatch, the source address bits are discarded. Otherwise, the controller sets a single bit token signal to indicate that the WI is the next in arbitration to get access of the channel, thereby passing the token. The elegance of the proposed method is that it passes the token with few modifications to the packet format. It does not require token to be passed separately or incur additional control signaling overheads. The destination WI Address is matched with its own address to verify if the intended receiver of the packet is the current WI or not. If the address matches, the packet reception is continued, otherwise the reception is stopped using power gating mechanism. The output of the comparator indicates the start and end of any WI transmission, thereby allowing the next WI in arbitration to start its transmission immediately. To ensure fair usage and allocation of channel among all WIs, the access of channel to each WI is controlled based on load at the WI. The total packet load to be transmitted at each WI is divided into multiple levels in the proposed method and channel access time (time for which the channel is allocated to the WI) is set proportional to the current load at the input buffers of WI. The channel access time in proportion to input load is Tail Extra bits for processing t t t a t 0 t a Source Dest Source WI Dest WI Access Time Fig. 3. Format of Packet Transmitted over Wireless Link Header

3 universal across all WIs and the proposed method ensures that channel allocation is efficient in accordance with the utilization of each WI in the network. The channel access time and arbitration sequence are both written in user controlled buffers at each WI, thereby allowing them to be modified as per the user needs. Furthermore, the channel access time for each transmission is also included in the header flit as shown in Fig. 3, allowing the receiving WIs to make adaptive routing decision in regards with the usage of wireless links. By using simple comparator based controller and few modifications to the header flit format, the proposed method performs channel allocation, token passing and control of channel access time and arbitration sequence providing greater flexibility to match the requirements of any application or system architecture. III. WI POWER GATING CONTROL The comparator based controller, in addition to performing channel allocation, also reduces energy consumption in WIs by power gating them when they are not actively involved in communication. Initially, all WIs are kept in idle state. At any HR, when routing strategy decides to use WI and associated WI has token to transmit data, the transmitter in WI is brought to active state. The transmitted signal from source WI is received at the antennas of all other WIs and their receiving end is brought to active state upon detecting a valid signal in the channel. The comparator of the proposed controller differentiates the valid signal from channel noise. The threshold of the comparator is set to the average value of signal strength of the most far apart nodes and worst case noise floor value of the wireless channel. This allows the receiving WIs to be brought to active state without any additional control information. The received packet is then demodulated and deserialized through WI components. A small wake up latency is associated with power gating mechanism and the data received over wireless channel are lost while the WIs are brought to active state. To avoid this, dummy bits are added at the start of packet and the size of dummy bits is proportional to the wakeup latency of the power gating switch. Furthermore, since all WIs, along with the intended receiver of the packet become active, the packet is unnecessarily processed at all WIs, leading to unwanted energy consumption. The pattern matching circuit of received WI Address is used to detect the intended receiver of the packet (as described before) and all WIs (except the actual receiver) are put back in sleep state once the pattern matching operation is completed. This reduces the unwanted data processing and energy consumption at all WIs, thereby further increasing the energy efficiency of proposed method. While the transmission is active, all the components in both transmitting and receiving WI are kept active. Once the transmission is complete, the source WI relinquishes the access of channel, both WIs are put back to sleep state and next WI in arbitration starts transmission as described before. Hence the proposed comparator based design also controls power gating of WIs efficiently with little overhead to reduce the energy consumption in WIs. TABLE I. SYSTEM ARCHITECTURE AND NETWORK TOPOLOGY Component Configuration Cores 8 x86 OOO cores, 32 GPU cores Caches 32 KB L1 cache, 256 KB L2 cache, 8 L2 caches, 2 MB L3 cache Topology 8x8 WNoC (Mesh augmented with wireless links), 4 wireless hubs Router 8 flit buffers, 5 I/O wired ports, 2 16 flit packets, 32 bit flits Wireless 60 GHz carrier, 16 Gbps bandwidth, single cycle Link latency mechanisms. For evaluation, we have used WNoC topology designed for CPU/GPU architectures adopted from [13]. The NoC evaluation is done by simulating proposed design on cycleaccurate Noxim simulator [17]. Full system simulation of Rodinia [18] benchmarks with gem5-gpu [19] are used to generate the network traces for Noxim simulator. The details of evaluated system architecture and WNoC are shown in Table I. All cores and wired network elements are operated at clock frequency of 2 GHz. The controller is designed using Cadence Virtuoso with 65nm technology. We evaluate the proposed controller in terms of channel utilization, token passes, packet latency and energy consumption. The results are compared with timer based token passing mechanism, which uses 8 cycle access time for each WI in one arbitration sequence. A. Wireless Channel Utilization We first evaluate the efficiency of proposed controller in improving channel utilization and allocating the channel to each WI. Fig. 4 shows the improvement in channel utilization and channel allocation over the entire application duration for different benchmarks. The channel allocation improvements are measured in terms of the number of token passes at each WI. As observed from the figure, comparator based controller improves the wireless channel utilization over most of the benchmarks. On average, it improves channel utilization by 9% as compared to timer based approach. Similarly, the number of token passes at each WI using comparator based approach is reduced by 53%, on average over timer based token passing mechanism. Unlike a timer based approach which uses fixed duration at each pass, proposed approach sets the channel access time as per the load during that pass. This makes the token passing adaptable to the packet sizes and utilization of each WI, thereby improving both channel IV. EXPERIMENTAL RESULTS In this section, we discuss the experimental setup, performance benefits and overheads of proposed channel access mechanism as compared to timer based token passing Fig. 4. Improvement in Wireless Channel Utilization and Token Passes using Comparator based Controller

4 access time in proportion to the input buffer load at each WI. By allowing larger access time to WIs with high load or vice-versa, the proposed method allows for faster access to data thereby significantly reducing the overall latency of the network. This is especially the case with WI associated with GPU cores, which require high volume of data to be transmitted between the cores and main memory. Fig. 5. Average Number of Token Passes across all WIs for Different Packet Sizes utilization and token passes. This is evident from Fig. 5, which shows the number of token passes with different packet sizes for Backprop benchmark. In this scenario, the packet size is kept fixed in each case. As the packet size increases, number of token passes using timer based approach increases exponentially. At large packet sizes, each WI can transmit only a part of the packet in fixed time duration and hence requiring multiple token passes for each packet. This significantly increases the total number of token passes. In comparator based approach, the channel access time is proportional to WI input load. Hence, a large packet size translates to larger access time, thereby keeping the number of token passes constant at all packet sizes. On the other hand, if packet size is small such that time required to transmit is smaller than fixed timer, channel remains idle during the remaining period. Comparator based approach, in this case, keeps channel access time smaller and improves overall utilization of wireless channel as evident from Fig. 4. This makes the channel based approach robust against different packet sizes, packet formats and requirements at each WI (as in heterogeneous systems). B. Network Performance To evaluate network performance, we compare the average packet delay of comparator based controller with that of timer based controller. Fig. 6 shows decrease in average latency using comparator based controller for different benchmarks. From the figure, it can be observed that comparator based approach has low average latency as compared to that of timer based WNoC, though both have same hardware topology. On average, proposed approach reduces latency by 9% as compared to timer based approach. The improvements in packet latency are primarily achieved due to the efficient allocation of channel Fig. 6. Decrease in Average Packet Latency and Energy Consumption using Comparator based Controller C. Energy Saving Fig. 6 shows average packet energy savings using comparator based WNoC as compared to timer based WNoC. In both implementations, power gating is employed for WIs to save energy. As can be observed from the figure, comparator based WNoC reduces packet energy consumption by 9%, on average as compared to the timer based approach. Even though both approaches employ power gating, comparator based approach controls the WIs in accordance with their load, thereby achieving better utilization of WIs. This directly impacts the energy consumption of packets transmitted over wireless links, leading to further decrease in WI energy with comparator based approach as compared to timer based approach. D. Overheads In this section, we discuss the overheads of comparator based controller for channel allocation in WNoC. The comparator circuit requires ns to detect a valid signal in the channel once the antenna starts receiving the data and hence it adds a delay overhead of 1 system clock cycle for each transmission. The comparator along with the pattern matching circuit in the controller consumes a total power of 300 µw. The power gating switch consumes 3.16 µw power. The WI, including transmitter and receiver in total has a power consumption of 32 mw. The power gating operation saves up to 68.23% of the leakage power in WIs during sleep mode. Hence, the proposed controller adds a power overhead of 0.77% as compared to the timer based approach, while reducing the number of token passes by 53% and improving channel utilization by 9%. The total area requirement of a regular wormhole based router and WI is mm 2 and 0.16 mm 2 respectively. The comparator based controller has an area requirement of µm 2, while power gating switch consumes 100 µm 2 area. Hence, the proposed approach adds negligible area overhead, while achieving considerable improvements in channel allocation and token passing in WIs. V. CONCLUSION In this work, we propose a comparator based controller to perform allocation of wireless channel to different WIs in a WNoC topology. It also power gates the WIs, when they are not actively involved in communication to save energy. The proposed approach uses a comparator attached to the antenna and modifications to header flit of packet transmitted over wireless link to control channel allocation to WIs. It also controls channel access time in accordance with input load to improve wireless utilization and reduce number of token passes. Using the proposed approach, the channel utilization improves by 9% and number of token passes are reduced by 53% as compared to timer based token passing approaches for WNoCs.

5 REFERENCES [1] L. Benini and G. De Micheli, "Networks on chips: a new SoC paradigm," in Computer, vol. 35, no. 1, pp , Jan [2] Hyung Gyu Lee, Naehyuck Chang, Umit Y. Ogras, and Radu Marculescu On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches. ACM Trans. Des. Autom. Electron. Syst. 12, 3, Article 23 (May 2008), 20 pages. [3] S. Deb, et al., "Design of an Energy-Efficient CMOS-Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects," in Computers, IEEE Transactions on, vol.62, no.12, pp , Dec [4] D. DiTomaso,et al., iwise: Inter-router Wireless Scalable Express Channels for Network-on-Chip (NoCs) Architectures, IEEE Symposium on High Performance Interconnects, pp , Aug, [5] C. Wang,et al., A Wireless Network-on-Chip Design for Multicore Platforms, 19th International EuromicroConference on Parallel, Distributed and Network-Based Processing, [6] H. K. Mondal, S. H. Gade, M. S. Shamim, S. Deb and A. Ganguly, "Interference-Aware Wireless Network-on-Chip Architecture Using Directional Antennas," in IEEE Transactions on Multi-Scale Computing Systems, vol. 3, no. 3, pp , July-Sept [7] Md Shahriar Shamim, Naseef Mansoor, Aman Samaiyar, Amlan Ganguly, Sujay Deb, and Shobha Sunndar Ram Energy-efficient wireless network-on-chip architecture with log-periodic on-chip antennas. In Proceedings of the 24th edition of the great lakes symposium on VLSI (GLSVLSI '14). ACM, New York, NY, USA, [8] Dan Zhao, Yi Wang, and Hongyi Wu Dual-channel binarycountdown medium access control in wireless network-on-chip. In Proceedings of the 2nd international conference on Nano-Networks (Nano-Net '07). ICST (Institute for Computer Sciences, Social- Informatics and Telecommunications Engineering), ICST, Brussels, Belgium, Belgium,, Article 11, 5 pages. [9] A. Ganguly, K. Chang, S. Deb, P. P. Pande, B. Belzer and C. Teuscher, "Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems," in IEEE Transactions on Computers, vol. 60, no. 10, pp , Oct [10] N. Mansoor, M. P. Yuvaraj and A. Ganguly, "A robust medium access mechanism for millimeter-wave Wireless Network-on-Chip architecture," 2013 IEEE International SOC Conference, Erlangen, 2013, pp [11] H. K. Mondal, S. H. Gade, S. Kaushik and S. Deb, "Adaptive Multi- Voltage Scaling with Utilization Prediction for Energy-Efficient Wireless NoC," in IEEE Transactions on Sustainable Computing, vol. 2, no. 4, pp , Oct.-Dec [12] M. Palesi, M. Collotta, A. Mineo, V. Catania, "An Efficient Radio Access Control Mechanism for Wireless Network-On-Chip Architectures," in Journal of Low Power Electronics and Applications, vol. 5, no. 2, pp , [13] S. H. Gade and S. Deb, "HyWin: Hybrid Wireless NoC with Sandboxed Sub-Networks for CPU/GPU Architectures," in IEEE Transactions on Computers, vol. 66, no. 7, pp , July [14] H. K. Mondal and S. Deb, "An energy efficient wireless Network-on-Chip using power-gated transceivers," th IEEE International Systemon-Chip Conference (SOCC), Las Vegas, NV, 2014, pp [15] H. K. Mondal, S. H. Gade, R. Kishore, S. Kaushik and S. Deb, "Power efficient router architecture for wireless Network-on-Chip," th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016, pp [16] H. K. Mondal, S. H. Gade, R. Kishore and S. Deb, "Adaptive multivoltage scaling in wireless NoC for high performance low power applications," 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2016, pp [17] Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, and Davide Patti Cycle-Accurate Network on Chip Simulation with Noxim. ACM Transactions on Modeling and Computer Simulation. Volume 27 Issue 1, November [18] S. Che et al., "Rodinia: A benchmark suite for heterogeneous computing," 2009 IEEE International Symposium on Workload Characterization (IISWC), Austin, TX, 2009, pp [19] J. Power, J. Hestness, M. S. Orr, M. D. Hill and D. A. Wood, "gem5-gpu: A Heterogeneous CPU-GPU Simulator," in IEEE Computer Architecture Letters, vol. 14, no. 1, pp , Jan.-June