Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip

Size: px
Start display at page:

Download "Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip"

Transcription

1 Trade Offs in the Design of a Router with Both Guaranteed and BestEffort Services for Networks on Chip E. Rijpkema, K. Goossens, A. R dulescu, J. Dielissen, J. van Meerbergen, P. Wielage, and E. Waterlander

2 why NetworksonChip problems observed for SoC design deep sub micron design complexity wire cost increasing # of IP blocks timing closure increasing dynamism decouple computation from communication application presentation session transport network data link physical application demands network independent services network dependent hardware technology IP IP IP R R R router network

3 why NetworksonChip problems observed for SoC design deep sub micron design complexity key: decouple computation from communication application presentation session transport network data link physical application demands network independent services network dependent hardware technology IP IP IP R R R router network 3

4 outline services combined router architecture guaranteed throughput router architecture besteffort router architecture router prototype conclusions 4

5 services I we need a network that is predictable cost effective requirements application demands guarantees services efficiency hardware technology constraints build guarantees on top of guarantees efficient network is efficient at every layer 5

6 services II timeless guarantees guaranteed data integrity guaranteed data delivery guaranteed inorder delivery time related guarantees (over bounded time interval) guaranteed throughput guaranteed latency besteffort service (BE) guaranteed throughput service (GT) 6

7 guarantees vs. besteffort GT requires dimensioning for guaranteed throughput BE requires dimensioning for average throughput r wc r wc 3 4 guaranteed throughput (bounded interval) ravg time time time guaranteed delivery combination is beneficial 7

8 BE & GT combined architecture conceptually, two disjoint routers a router with GT service class a router with BE service class BE router r wc programming GT router 3 4 priority/arbitration to obtain an efficient combination routers must have similar architectures 8

9 buffering strategy output queuing highest cost highest performance N N input queuing lowest cost lowest performance N X N virtual output queuing moderate cost high performance N X N preferred solution 9

10 contention links in network are shared resources contention occurs when multiple data request same link at same time GT and BE resolve contention differently 0

11 guaranteed throughput to guarantee latency or bandwidth over finite interval cannot drop data must bound contention ratebased scheduling has high buffer costs (deep fifos/output queuing) deadlinebased scheduling even higher buffer costs (deep priority queues) contentionfree routing low buffer costs (shallow fifos)

12 contentionfree routing I scheduling packet injection in network to avoid contention in space: disjoint paths as in pure circuit switching in time: timedivision multiplexing as with a statically scheduled bus in time and space: our solution

13 contentionfree routing II divide time in slots block block block 3 time slot a block is amount of data that fits in a slot block entering router in slot n enters next in slot n+ n n+ n+3 n+ matches with input queuing N X 3 N

14 contentionfree routing III routers have tables that store contention resolution & routing information allow distributed programming S S S S small blocks Æ low buffering cost small slots Æ low latency Æ throughput guarantee on smaller period 4

15 besteffort architecture to ensure high resource utilization statistical multiplexing packetswitching but implement BE service class packetswitching network flow control (routing mode) contention resolution 5

16 packets and flits packet = header + payload H payload packet might be transmitted in smaller parts called flits flit flit flit 3 flit 4 flits divide time in iterations and must be scheduled flit flit flit 3 flit 4 time smaller flit size Æ higher scheduling rate Æ lower latency Æ less storage 6

17 network flow control (routing mode) performance/cost network flow control store and forward routing first receive whole packet then transmit whole packet virtual cutthrough routing send flit immediately if next router can receive entire packet wormhole routing send flit immediately if next router can receive that flit per router latency storage packet packet flit packet flit flit 7

18 contention resolution queuing at input Æ set paths from inputs to outputs router has switch bipartite graph matching 3 X 3 algorithm must be fair have low complexity (to schedule at flit rate) approximation of maximal matching 8

19 combining GT and BE links must be shared by GT and BE traffic grain size of interleaving must match block size = flit size smallest value for this is given by implementation minimize scheduler latency Æ L maximize data path speed Æ F flit size = block size = F L 9

20 router prototype snapshot of current prototype router: control input queuing arity 5 3 bits wide words 8 flits deep BE queues 56 slots 0.5 mm CMOS 500 MHz data path 66 MHz control path flit size is 3 words throughput per link: 500MHz 3bits = 6Gb/s 0

21 conclusions for NoCs, guaranteed services are essential demonstrated the useful combination of: BE service class Æ timeless guarantees GT service class Æ BE + time related guarantees made tradeoffs to come to efficient combined router proved feasibility with router prototype

22 router prototype snapshot of current prototype router: 5 input and 5 output ports (arity 5) 0.5 mm CMOS 500 MHz data path, 66 MHz control path flit size of 3 words of 3 bits 500x3 = 6 Gb/s throughput per link 56 slots & 5x flit fifos for guaranteedthroughput traffic 6x8 flit fifos for besteffort traffic

23 control control 3

Flow Control can be viewed as a problem of

Flow Control can be viewed as a problem of NOC Flow Control 1 Flow Control Flow Control determines how the resources of a network, such as channel bandwidth and buffer capacity are allocated to packets traversing a network Goal is to use resources

More information

A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip

A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip A Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless -on-chip Tobias Bjerregaard and Jens Sparsø Informatics and Mathematical Modelling Technical University of Denmark (DTU),

More information

Connection-oriented Multicasting in Wormhole-switched Networks on Chip

Connection-oriented Multicasting in Wormhole-switched Networks on Chip Connection-oriented Multicasting in Wormhole-switched Networks on Chip Zhonghai Lu, Bei Yin and Axel Jantsch Laboratory of Electronics and Computer Systems Royal Institute of Technology, Sweden fzhonghai,axelg@imit.kth.se,

More information

Generic Architecture. EECS 122: Introduction to Computer Networks Switch and Router Architectures. Shared Memory (1 st Generation) Today s Lecture

Generic Architecture. EECS 122: Introduction to Computer Networks Switch and Router Architectures. Shared Memory (1 st Generation) Today s Lecture Generic Architecture EECS : Introduction to Computer Networks Switch and Router Architectures Computer Science Division Department of Electrical Engineering and Computer Sciences University of California,

More information

Chapter 6 Queuing Disciplines. Networking CS 3470, Section 1

Chapter 6 Queuing Disciplines. Networking CS 3470, Section 1 Chapter 6 Queuing Disciplines Networking CS 3470, Section 1 Flow control vs Congestion control Flow control involves preventing senders from overrunning the capacity of the receivers Congestion control

More information

EECS 122: Introduction to Computer Networks Switch and Router Architectures. Today s Lecture

EECS 122: Introduction to Computer Networks Switch and Router Architectures. Today s Lecture EECS : Introduction to Computer Networks Switch and Router Architectures Computer Science Division Department of Electrical Engineering and Computer Sciences University of California, Berkeley Berkeley,

More information

Quality-of-Service for a High-Radix Switch

Quality-of-Service for a High-Radix Switch Quality-of-Service for a High-Radix Switch Nilmini Abeyratne, Supreet Jeloka, Yiping Kang, David Blaauw, Ronald G. Dreslinski, Reetuparna Das, and Trevor Mudge University of Michigan 51 st DAC 06/05/2014

More information

CSE398: Network Systems Design

CSE398: Network Systems Design CSE398: Network Systems Design Instructor: Dr. Liang Cheng Department of Computer Science and Engineering P.C. Rossin College of Engineering & Applied Science Lehigh University March 14, 2005 Outline Classification

More information

An Analysis of Blocking vs Non-Blocking Flow Control in On-Chip Networks

An Analysis of Blocking vs Non-Blocking Flow Control in On-Chip Networks An Analysis of Blocking vs Non-Blocking Flow Control in On-Chip Networks ABSTRACT High end System-on-Chip (SoC) architectures consist of tens of processing engines. These processing engines have varied

More information

Queuing. Congestion Control and Resource Allocation. Resource Allocation Evaluation Criteria. Resource allocation Drop disciplines Queuing disciplines

Queuing. Congestion Control and Resource Allocation. Resource Allocation Evaluation Criteria. Resource allocation Drop disciplines Queuing disciplines Resource allocation Drop disciplines Queuing disciplines Queuing 1 Congestion Control and Resource Allocation Handle congestion if and when it happens TCP Congestion Control Allocate resources to avoid

More information

Deadlock-free XY-YX router for on-chip interconnection network

Deadlock-free XY-YX router for on-chip interconnection network LETTER IEICE Electronics Express, Vol.10, No.20, 1 5 Deadlock-free XY-YX router for on-chip interconnection network Yeong Seob Jeong and Seung Eun Lee a) Dept of Electronic Engineering Seoul National Univ

More information

OASIS NoC Architecture Design in Verilog HDL Technical Report: TR OASIS

OASIS NoC Architecture Design in Verilog HDL Technical Report: TR OASIS OASIS NoC Architecture Design in Verilog HDL Technical Report: TR-062010-OASIS Written by Kenichi Mori ASL-Ben Abdallah Group Graduate School of Computer Science and Engineering The University of Aizu

More information

Cross Clock-Domain TDM Virtual Circuits for Networks on Chips

Cross Clock-Domain TDM Virtual Circuits for Networks on Chips Cross Clock-Domain TDM Virtual Circuits for Networks on Chips Zhonghai Lu Dept. of Electronic Systems School for Information and Communication Technology KTH - Royal Institute of Technology, Stockholm

More information

Module 17: "Interconnection Networks" Lecture 37: "Introduction to Routers" Interconnection Networks. Fundamentals. Latency and bandwidth

Module 17: Interconnection Networks Lecture 37: Introduction to Routers Interconnection Networks. Fundamentals. Latency and bandwidth Interconnection Networks Fundamentals Latency and bandwidth Router architecture Coherence protocol and routing [From Chapter 10 of Culler, Singh, Gupta] file:///e /parallel_com_arch/lecture37/37_1.htm[6/13/2012

More information

Efficient Throughput-Guarantees for Latency-Sensitive Networks-On-Chip

Efficient Throughput-Guarantees for Latency-Sensitive Networks-On-Chip ASP-DAC 2010 20 Jan 2010 Session 6C Efficient Throughput-Guarantees for Latency-Sensitive Networks-On-Chip Jonas Diemer, Rolf Ernst TU Braunschweig, Germany diemer@ida.ing.tu-bs.de Michael Kauschke Intel,

More information

Outline. Computer Communication and Networks. The Network Core. Components of the Internet. The Network Core Packet Switching Circuit Switching

Outline. Computer Communication and Networks. The Network Core. Components of the Internet. The Network Core Packet Switching Circuit Switching Outline Computer Communication and Networks 1 Department of Computer Science & Information Technology University of Balochistan Lecture 03 1/26 2/26 Two major components The mesh of packet switches and

More information

SoC Design Lecture 13: NoC (Network-on-Chip) Department of Computer Engineering Sharif University of Technology

SoC Design Lecture 13: NoC (Network-on-Chip) Department of Computer Engineering Sharif University of Technology SoC Design Lecture 13: NoC (Network-on-Chip) Department of Computer Engineering Sharif University of Technology Outline SoC Interconnect NoC Introduction NoC layers Typical NoC Router NoC Issues Switching

More information

Multicomputer distributed system LECTURE 8

Multicomputer distributed system LECTURE 8 Multicomputer distributed system LECTURE 8 DR. SAMMAN H. AMEEN 1 Wide area network (WAN); A WAN connects a large number of computers that are spread over large geographic distances. It can span sites in

More information

Real Time NoC Based Pipelined Architectonics With Efficient TDM Schema

Real Time NoC Based Pipelined Architectonics With Efficient TDM Schema Real Time NoC Based Pipelined Architectonics With Efficient TDM Schema [1] Laila A, [2] Ajeesh R V [1] PG Student [VLSI & ES] [2] Assistant professor, Department of ECE, TKM Institute of Technology, Kollam

More information

A Predictable Communication Scheme for Embedded Multiprocessor Systems

A Predictable Communication Scheme for Embedded Multiprocessor Systems A Predictable Communication Scheme for Embedded Multiprocessor Systems Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici Ecole Polytechnique Fédérale de Lausanne (EPFL) Lausanne, Switzerland Email:

More information

Improving Routing Efficiency for Network-on-Chip through Contention-Aware Input Selection

Improving Routing Efficiency for Network-on-Chip through Contention-Aware Input Selection Improving Routing Efficiency for Network-on-Chip through Contention-Aware Input Selection Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz School of Electronics and Computer Science University of Southampton

More information

Overview Computer Networking What is QoS? Queuing discipline and scheduling. Traffic Enforcement. Integrated services

Overview Computer Networking What is QoS? Queuing discipline and scheduling. Traffic Enforcement. Integrated services Overview 15-441 15-441 Computer Networking 15-641 Lecture 19 Queue Management and Quality of Service Peter Steenkiste Fall 2016 www.cs.cmu.edu/~prs/15-441-f16 What is QoS? Queuing discipline and scheduling

More information

Ultra-Fast NoC Emulation on a Single FPGA

Ultra-Fast NoC Emulation on a Single FPGA The 25 th International Conference on Field-Programmable Logic and Applications (FPL 2015) September 3, 2015 Ultra-Fast NoC Emulation on a Single FPGA Thiem Van Chu, Shimpei Sato, and Kenji Kise Tokyo

More information

CHAPTER 6 FPGA IMPLEMENTATION OF ARBITERS ALGORITHM FOR NETWORK-ON-CHIP

CHAPTER 6 FPGA IMPLEMENTATION OF ARBITERS ALGORITHM FOR NETWORK-ON-CHIP 133 CHAPTER 6 FPGA IMPLEMENTATION OF ARBITERS ALGORITHM FOR NETWORK-ON-CHIP 6.1 INTRODUCTION As the era of a billion transistors on a one chip approaches, a lot of Processing Elements (PEs) could be located

More information

FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow

FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow Abstract: High-level synthesis (HLS) of data-parallel input languages, such as the Compute Unified Device Architecture

More information

A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip

A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip Tobias Bjerregaard and Jens Sparsø Technical University of Denmark (DTU) Informatics and Mathematical Modelling

More information

Performance Analysis of Routing Algorithms

Performance Analysis of Routing Algorithms International Journal Scientific & Engineering Research Volume 3, Issue 12, December-2012 1 Performance Analysis Routing Algorithms Mr. Lokesh M. Heda Shri Ramdeobaba, College Engineering and Management,

More information

Real-Time Mixed-Criticality Wormhole Networks

Real-Time Mixed-Criticality Wormhole Networks eal-time Mixed-Criticality Wormhole Networks Leandro Soares Indrusiak eal-time Systems Group Department of Computer Science University of York United Kingdom eal-time Systems Group 1 Outline Wormhole Networks

More information

FPGA based Design of Low Power Reconfigurable Router for Network on Chip (NoC)

FPGA based Design of Low Power Reconfigurable Router for Network on Chip (NoC) FPGA based Design of Low Power Reconfigurable Router for Network on Chip (NoC) D.Udhayasheela, pg student [Communication system],dept.ofece,,as-salam engineering and technology, N.MageshwariAssistant Professor

More information

Basic Switch Organization

Basic Switch Organization NOC Routing 1 Basic Switch Organization 2 Basic Switch Organization Link Controller Used for coordinating the flow of messages across the physical link of two adjacent switches 3 Basic Switch Organization

More information

Lecture 3: Flow-Control

Lecture 3: Flow-Control High-Performance On-Chip Interconnects for Emerging SoCs http://tusharkrishna.ece.gatech.edu/teaching/nocs_acaces17/ ACACES Summer School 2017 Lecture 3: Flow-Control Tushar Krishna Assistant Professor

More information

Communication Services for Networks on Chip

Communication Services for Networks on Chip SAMOS, II(), 275 299 (2002) Communication Services for Networks on Chip Andrei Rădulescu and Kees Goossens Philips Research Laboratories, Eindhoven, The Netherlands Email: andrei.radulescu kees.goossens@philips.com

More information

Networks-on-Chip Router: Configuration and Implementation

Networks-on-Chip Router: Configuration and Implementation Networks-on-Chip : Configuration and Implementation Wen-Chung Tsai, Kuo-Chih Chu * 2 1 Department of Information and Communication Engineering, Chaoyang University of Technology, Taichung 413, Taiwan,

More information

ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology

ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology 1 ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology Mikkel B. Stensgaard and Jens Sparsø Technical University of Denmark Technical University of Denmark Outline 2 Motivation ReNoC Basic

More information

Computer Networks. ENGG st Semester, 2010 Hayden Kwok-Hay So

Computer Networks. ENGG st Semester, 2010 Hayden Kwok-Hay So Computer Networks ENGG1015 1 st Semester, 2010 Hayden Kwok-Hay So Where are we in the semester? High Level Applications Systems Digital Logic Image & Video Processing Computer & Embedded Systems Computer

More information

Study of Network on Chip resources allocation for QoS Management

Study of Network on Chip resources allocation for QoS Management Journal of Computer Science 2 (10): 770-774, 2006 ISSN 1549-3636 2006 Science Publications Study of Network on Chip resources allocation for QoS Management Abdelhamid HELALI, Adel SOUDANI, Jamila BHAR

More information

NOC DESIGN DECISIONS FOR EACH OSI LAYER

NOC DESIGN DECISIONS FOR EACH OSI LAYER Letter No.V-34564,Reg.533/2007-2008 INDIAN JOURNAL OF RESEARCH(2012)6, ANVIKSHIKI ISSN 0973-9777 Advance Access publication 20 July. 2012 NOC DESIGN DECISIONS FOR EACH OSI LAYER CHANDRA SHEKHAR Research

More information

Basic Low Level Concepts

Basic Low Level Concepts Course Outline Basic Low Level Concepts Case Studies Operation through multiple switches: Topologies & Routing v Direct, indirect, regular, irregular Formal models and analysis for deadlock and livelock

More information

Toward a Reliable Data Transport Architecture for Optical Burst-Switched Networks

Toward a Reliable Data Transport Architecture for Optical Burst-Switched Networks Toward a Reliable Data Transport Architecture for Optical Burst-Switched Networks Dr. Vinod Vokkarane Assistant Professor, Computer and Information Science Co-Director, Advanced Computer Networks Lab University

More information

Future Gigascale MCSoCs Applications: Computation & Communication Orthogonalization

Future Gigascale MCSoCs Applications: Computation & Communication Orthogonalization Basic Network-on-Chip (BANC) interconnection for Future Gigascale MCSoCs Applications: Computation & Communication Orthogonalization Abderazek Ben Abdallah, Masahiro Sowa Graduate School of Information

More information

Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in on-chip Networks

Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in on-chip Networks Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in on-chip Networks Andreas Lankes¹, Soeren Sonntag², Helmut Reinig³, Thomas Wild¹, Andreas Herkersdorf¹

More information

Lecture 24: Interconnection Networks. Topics: topologies, routing, deadlocks, flow control

Lecture 24: Interconnection Networks. Topics: topologies, routing, deadlocks, flow control Lecture 24: Interconnection Networks Topics: topologies, routing, deadlocks, flow control 1 Topology Examples Grid Torus Hypercube Criteria Bus Ring 2Dtorus 6-cube Fully connected Performance Bisection

More information

Evaluation of NOC Using Tightly Coupled Router Architecture

Evaluation of NOC Using Tightly Coupled Router Architecture IOSR Journal of Computer Engineering (IOSR-JCE) e-issn: 2278-0661,p-ISSN: 2278-8727, Volume 18, Issue 1, Ver. II (Jan Feb. 2016), PP 01-05 www.iosrjournals.org Evaluation of NOC Using Tightly Coupled Router

More information

Flit Synchronous Aelite Network on Chip. Mahesh Balaji Subburaman

Flit Synchronous Aelite Network on Chip. Mahesh Balaji Subburaman Flit Synchronous Aelite Network on Chip Examensarbete utfört i Elektroniksystem vid Tekniska högskolan i Linköping av Mahesh Balaji Subburaman LiTH - ISY - EX -- 08 / 4198 -- SE Linköping 2008 Flit Synchronous

More information

Fault Tolerant and Secure Architectures for On Chip Networks With Emerging Interconnect Technologies. Mohsin Y Ahmed Conlan Wesson

Fault Tolerant and Secure Architectures for On Chip Networks With Emerging Interconnect Technologies. Mohsin Y Ahmed Conlan Wesson Fault Tolerant and Secure Architectures for On Chip Networks With Emerging Interconnect Technologies Mohsin Y Ahmed Conlan Wesson Overview NoC: Future generation of many core processor on a single chip

More information

SoC Design. Prof. Dr. Christophe Bobda Institut für Informatik Lehrstuhl für Technische Informatik

SoC Design. Prof. Dr. Christophe Bobda Institut für Informatik Lehrstuhl für Technische Informatik SoC Design Prof. Dr. Christophe Bobda Institut für Informatik Lehrstuhl für Technische Informatik Chapter 5 On-Chip Communication Outline 1. Introduction 2. Shared media 3. Switched media 4. Network on

More information

The Network Layer and Routers

The Network Layer and Routers The Network Layer and Routers Daniel Zappala CS 460 Computer Networking Brigham Young University 2/18 Network Layer deliver packets from sending host to receiving host must be on every host, router in

More information

Lecture 7: Flow Control - I

Lecture 7: Flow Control - I ECE 8823 A / CS 8803 - ICN Interconnection Networks Spring 2017 http://tusharkrishna.ece.gatech.edu/teaching/icn_s17/ Lecture 7: Flow Control - I Tushar Krishna Assistant Professor School of Electrical

More information

Fast, Accurate and Detailed NoC Simulations

Fast, Accurate and Detailed NoC Simulations Fast, Accurate and Detailed NoC Simulations Pascal T. Wolkotte and Philip K.F. Hölzenspies and Gerard J.M. Smit University of Twente, Department of EEMCS P.O. Box 217, 75 AE Enschede, The Netherlands P.T.Wolkotte@utwente.nl

More information

Network on Chip Architecture: An Overview

Network on Chip Architecture: An Overview Network on Chip Architecture: An Overview Md Shahriar Shamim & Naseef Mansoor 12/5/2014 1 Overview Introduction Multi core chip Challenges Network on Chip Architecture Regular Topology Irregular Topology

More information

Introduction: Two motivating examples for the analytical approach

Introduction: Two motivating examples for the analytical approach Introduction: Two motivating examples for the analytical approach Hongwei Zhang http://www.cs.wayne.edu/~hzhang Acknowledgement: this lecture is partially based on the slides of Dr. D. Manjunath Outline

More information

Lecture 16: On-Chip Networks. Topics: Cache networks, NoC basics

Lecture 16: On-Chip Networks. Topics: Cache networks, NoC basics Lecture 16: On-Chip Networks Topics: Cache networks, NoC basics 1 Traditional Networks Huh et al. ICS 05, Beckmann MICRO 04 Example designs for contiguous L2 cache regions 2 Explorations for Optimality

More information

Design of network adapter compatible OCP for high-throughput NOC

Design of network adapter compatible OCP for high-throughput NOC Applied Mechanics and Materials Vols. 313-314 (2013) pp 1341-1346 Online available since 2013/Mar/25 at www.scientific.net (2013) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/amm.313-314.1341

More information

Network on Chip Architectures BY JAGAN MURALIDHARAN NIRAJ VASUDEVAN

Network on Chip Architectures BY JAGAN MURALIDHARAN NIRAJ VASUDEVAN Network on Chip Architectures BY JAGAN MURALIDHARAN NIRAJ VASUDEVAN Multi Core Chips No more single processor systems High computational power requirements Increasing clock frequency increases power dissipation

More information

CAD System Lab Graduate Institute of Electronics Engineering National Taiwan University Taipei, Taiwan, ROC

CAD System Lab Graduate Institute of Electronics Engineering National Taiwan University Taipei, Taiwan, ROC QoS Aware BiNoC Architecture Shih-Hsin Lo, Ying-Cherng Lan, Hsin-Hsien Hsien Yeh, Wen-Chung Tsai, Yu-Hen Hu, and Sao-Jie Chen Ying-Cherng Lan CAD System Lab Graduate Institute of Electronics Engineering

More information

Cost-Performance Trade-offs in Networks on Chip: A Simulation-Based Approach

Cost-Performance Trade-offs in Networks on Chip: A Simulation-Based Approach Cost-Performance Trade-offs in Networks on Chip: A Simulation-Based Approach Santiago Gonzalez Pestana, Edwin ijpkema, Andrei ădulescu, Kees Goossens and Om Prakash Gangwal Philips esearch Laboratories,

More information

A closer look at network structure:

A closer look at network structure: T1: Introduction 1.1 What is computer network? Examples of computer network The Internet Network structure: edge and core 1.2 Why computer networks 1.3 The way networks work 1.4 Performance metrics: Delay,

More information

Network layer (addendum) Slides adapted from material by Nick McKeown and Kevin Lai

Network layer (addendum) Slides adapted from material by Nick McKeown and Kevin Lai Network layer (addendum) Slides adapted from material by Nick McKeown and Kevin Lai Routers.. A router consists - A set of input interfaces at which packets arrive - A set of output interfaces from which

More information

EE 122: Router Design

EE 122: Router Design Routers EE 22: Router Design Kevin Lai September 25, 2002.. A router consists - A set of input interfaces at which packets arrive - A set of output interfaces from which packets depart - Some form of interconnect

More information

A Reconfigurable Crossbar Switch with Adaptive Bandwidth Control for Networks-on

A Reconfigurable Crossbar Switch with Adaptive Bandwidth Control for Networks-on A Reconfigurable Crossbar Switch with Adaptive Bandwidth Control for Networks-on on-chip Donghyun Kim, Kangmin Lee, Se-joong Lee and Hoi-Jun Yoo Semiconductor System Laboratory, Dept. of EECS, Korea Advanced

More information

Re-Examining Conventional Wisdom for Networks-on-Chip in the Context of FPGAs

Re-Examining Conventional Wisdom for Networks-on-Chip in the Context of FPGAs This work was funded by NSF. We thank Xilinx for their FPGA and tool donations. We thank Bluespec for their tool donations. Re-Examining Conventional Wisdom for Networks-on-Chip in the Context of FPGAs

More information

Router Architectures

Router Architectures Router Architectures Venkat Padmanabhan Microsoft Research 13 April 2001 Venkat Padmanabhan 1 Outline Router architecture overview 50 Gbps multi-gigabit router (Partridge et al.) Technology trends Venkat

More information

NoC Test-Chip Project: Working Document

NoC Test-Chip Project: Working Document NoC Test-Chip Project: Working Document Michele Petracca, Omar Ahmad, Young Jin Yoon, Frank Zovko, Luca Carloni and Kenneth Shepard I. INTRODUCTION This document describes the low-power high-performance

More information

Routing of guaranteed throughput traffic in a network-on-chip

Routing of guaranteed throughput traffic in a network-on-chip Routing of guaranteed throughput traffic in a network-on-chip Nikolay Kavaldjiev, Gerard J. M. Smit, Pascal T. Wolkotte, Pierre G. Jansen Department of EEMCS, University of Twente, the Netherlands {n.k.kavaldjiev,

More information

048866: Packet Switch Architectures

048866: Packet Switch Architectures 048866: Packet Switch Architectures Output-Queued Switches Deterministic Queueing Analysis Fairness and Delay Guarantees Dr. Isaac Keslassy Electrical Engineering, Technion isaac@ee.technion.ac.il http://comnet.technion.ac.il/~isaac/

More information

Lecture 21. Reminders: Homework 6 due today, Programming Project 4 due on Thursday Questions? Current event: BGP router glitch on Nov.

Lecture 21. Reminders: Homework 6 due today, Programming Project 4 due on Thursday Questions? Current event: BGP router glitch on Nov. Lecture 21 Reminders: Homework 6 due today, Programming Project 4 due on Thursday Questions? Current event: BGP router glitch on Nov. 7 http://money.cnn.com/2011/11/07/technology/juniper_internet_outage/

More information

A Single Chip Shared Memory Switch with Twelve 10Gb Ethernet Ports

A Single Chip Shared Memory Switch with Twelve 10Gb Ethernet Ports A Single Chip Shared Memory Switch with Twelve 10Gb Ethernet Ports Takeshi Shimizu, Yukihiro Nakagawa, Sridhar Pathi, Yasushi Umezawa, Takashi Miyoshi, Yoichi Koyanagi, Takeshi Horie, Akira Hattori Hot

More information

SONA: An On-Chip Network for Scalable Interconnection of AMBA-Based IPs*

SONA: An On-Chip Network for Scalable Interconnection of AMBA-Based IPs* SONA: An On-Chip Network for Scalable Interconnection of AMBA-Based IPs* Eui Bong Jung 1, Han Wook Cho 1, Neungsoo Park 2, and Yong Ho Song 1 1 College of Information and Communications, Hanyang University,

More information

Mohammad Hossein Manshaei 1393

Mohammad Hossein Manshaei 1393 Mohammad Hossein Manshaei manshaei@gmail.com 1393 Voice and Video over IP Slides derived from those available on the Web site of the book Computer Networking, by Kurose and Ross, PEARSON 2 Multimedia networking:

More information

Lecture 12: Interconnection Networks. Topics: dimension/arity, routing, deadlock, flow control

Lecture 12: Interconnection Networks. Topics: dimension/arity, routing, deadlock, flow control Lecture 12: Interconnection Networks Topics: dimension/arity, routing, deadlock, flow control 1 Interconnection Networks Recall: fully connected network, arrays/rings, meshes/tori, trees, butterflies,

More information

Introduction to Real-Time Communications. Real-Time and Embedded Systems (M) Lecture 15

Introduction to Real-Time Communications. Real-Time and Embedded Systems (M) Lecture 15 Introduction to Real-Time Communications Real-Time and Embedded Systems (M) Lecture 15 Lecture Outline Modelling real-time communications Traffic and network models Properties of networks Throughput, delay

More information

Fitting the Router Characteristics in NoCs to Meet QoS Requirements

Fitting the Router Characteristics in NoCs to Meet QoS Requirements Fitting the Router Characteristics in NoCs to Meet QoS Requirements Edgard de Faria Corrêa Superintendência de Informática - UFRN edgard@info.ufrn.br Leonardo A.de P. e Silva lapys@inf.ufrgs.br Flávio

More information

A Survey on Asynchronous and Synchronous Network on Chip

A Survey on Asynchronous and Synchronous Network on Chip ISSN : 2230-7109 (Online) ISSN : 2230-9543 (Print) A Survey on Asynchronous and Synchronous on Chip 1 C. Chitra, 2 S. Prabakaran, 3 R. Prabakaran 1,2 Anna University of Technology, Tiruchirappalli, Tamilnadu,

More information

POLYMORPHIC ON-CHIP NETWORKS

POLYMORPHIC ON-CHIP NETWORKS POLYMORPHIC ON-CHIP NETWORKS Martha Mercaldi Kim, John D. Davis*, Mark Oskin, Todd Austin** University of Washington *Microsoft Research, Silicon Valley ** University of Michigan On-Chip Network Selection

More information

QoS Services with Dynamic Packet State

QoS Services with Dynamic Packet State QoS Services with Dynamic Packet State Ion Stoica Carnegie Mellon University (joint work with Hui Zhang and Scott Shenker) Today s Internet Service: best-effort datagram delivery Architecture: stateless

More information

On Packet Switched Networks for On-Chip Communication

On Packet Switched Networks for On-Chip Communication On Packet Switched Networks for On-Chip Communication Embedded Systems Group Department of Electronics and Computer Engineering School of Engineering, Jönköping University Jönköping 1 Outline : Part 1

More information

Network Control and Signalling

Network Control and Signalling Network Control and Signalling 1. Introduction 2. Fundamentals and design principles 3. Network architecture and topology 4. Network control and signalling 5. Network components 5.1 links 5.2 switches

More information

Lecture 18: Communication Models and Architectures: Interconnection Networks

Lecture 18: Communication Models and Architectures: Interconnection Networks Design & Co-design of Embedded Systems Lecture 18: Communication Models and Architectures: Interconnection Networks Sharif University of Technology Computer Engineering g Dept. Winter-Spring 2008 Mehdi

More information

Routing, Routers, Switching Fabrics

Routing, Routers, Switching Fabrics Routing, Routers, Switching Fabrics Outline Link state routing Link weights Router Design / Switching Fabrics CS 640 1 Link State Routing Summary One of the oldest algorithm for routing Finds SP by developing

More information

CS 552 Computer Networks

CS 552 Computer Networks CS 55 Computer Networks IP forwarding Fall 00 Rich Martin (Slides from D. Culler and N. McKeown) Position Paper Goals: Practice writing to convince others Research an interesting topic related to networking.

More information

Network Calculus: A Comparison

Network Calculus: A Comparison Time-Division Multiplexing vs Network Calculus: A Comparison Wolfgang Puffitsch, Rasmus Bo Sørensen, Martin Schoeberl RTNS 15, Lille, France Motivation Modern multiprocessors use networks-on-chip Congestion

More information

Real-Time Protocol (RTP)

Real-Time Protocol (RTP) Real-Time Protocol (RTP) Provides standard packet format for real-time application Typically runs over UDP Specifies header fields below Payload Type: 7 bits, providing 128 possible different types of

More information

Parallel Computing 39 (2013) Contents lists available at SciVerse ScienceDirect. Parallel Computing

Parallel Computing 39 (2013) Contents lists available at SciVerse ScienceDirect. Parallel Computing Parallel Computing 39 (2013) 424 441 Contents lists available at SciVerse ScienceDirect Parallel Computing journal homepage: www.elsevier.com/locate/parco A hardware/software platform for QoS bridging

More information

QoS MIB Implementation

QoS MIB Implementation APPENDIXB This appendix provides information about QoS-based features that are implemented on the Cisco Carrier Routing System line cards and what tables and objects in the QoS MIB support these QoS features.

More information

Thomas Moscibroda Microsoft Research. Onur Mutlu CMU

Thomas Moscibroda Microsoft Research. Onur Mutlu CMU Thomas Moscibroda Microsoft Research Onur Mutlu CMU CPU+L1 CPU+L1 CPU+L1 CPU+L1 Multi-core Chip Cache -Bank Cache -Bank Cache -Bank Cache -Bank CPU+L1 CPU+L1 CPU+L1 CPU+L1 Accelerator, etc Cache -Bank

More information

Overview. Lecture 22 Queue Management and Quality of Service (QoS) Queuing Disciplines. Typical Internet Queuing. FIFO + Drop tail Problems

Overview. Lecture 22 Queue Management and Quality of Service (QoS) Queuing Disciplines. Typical Internet Queuing. FIFO + Drop tail Problems Lecture 22 Queue Management and Quality of Service (QoS) Overview Queue management & RED Fair queuing Khaled Harras School of Computer Science niversity 15 441 Computer Networks Based on slides from previous

More information

Interconnection Networks

Interconnection Networks Lecture 17: Interconnection Networks Parallel Computer Architecture and Programming A comment on web site comments It is okay to make a comment on a slide/topic that has already been commented on. In fact

More information

Interconnection Networks: Topology. Prof. Natalie Enright Jerger

Interconnection Networks: Topology. Prof. Natalie Enright Jerger Interconnection Networks: Topology Prof. Natalie Enright Jerger Topology Overview Definition: determines arrangement of channels and nodes in network Analogous to road map Often first step in network design

More information

A Survey of Techniques for Power Aware On-Chip Networks.

A Survey of Techniques for Power Aware On-Chip Networks. A Survey of Techniques for Power Aware On-Chip Networks. Samir Chopra Ji Young Park May 2, 2005 1. Introduction On-chip networks have been proposed as a solution for challenges from process technology

More information

A common issue that affects the QoS of packetized audio is jitter. Voice data requires a constant packet interarrival rate at receivers to convert

A common issue that affects the QoS of packetized audio is jitter. Voice data requires a constant packet interarrival rate at receivers to convert A common issue that affects the QoS of packetized audio is jitter. Voice data requires a constant packet interarrival rate at receivers to convert data into a proper analog signal for playback. The variations

More information

Optical Packet Switching

Optical Packet Switching Optical Packet Switching DEISNet Gruppo Reti di Telecomunicazioni http://deisnet.deis.unibo.it WDM Optical Network Legacy Networks Edge Systems WDM Links λ 1 λ 2 λ 3 λ 4 Core Nodes 2 1 Wavelength Routing

More information

ECE 697J Advanced Topics in Computer Networks

ECE 697J Advanced Topics in Computer Networks ECE 697J Advanced Topics in Computer Networks Switching Fabrics 10/02/03 Tilman Wolf 1 Router Data Path Last class: Single CPU is not fast enough for processing packets Multiple advanced processors in

More information

OpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel

OpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel OpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel Hyoukjun Kwon and Tushar Krishna Georgia Institute of Technology Synergy Lab (http://synergy.ece.gatech.edu) hyoukjun@gatech.edu April

More information

KiloCore: A 32 nm 1000-Processor Array

KiloCore: A 32 nm 1000-Processor Array KiloCore: A 32 nm 1000-Processor Array Brent Bohnenstiehl, Aaron Stillmaker, Jon Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo, Bevan Baas University of California, Davis VLSI Computation

More information

Priority Traffic CSCD 433/533. Advanced Networks Spring Lecture 21 Congestion Control and Queuing Strategies

Priority Traffic CSCD 433/533. Advanced Networks Spring Lecture 21 Congestion Control and Queuing Strategies CSCD 433/533 Priority Traffic Advanced Networks Spring 2016 Lecture 21 Congestion Control and Queuing Strategies 1 Topics Congestion Control and Resource Allocation Flows Types of Mechanisms Evaluation

More information

Master Course Computer Networks IN2097

Master Course Computer Networks IN2097 Chair for Network Architectures and Services Prof. Carle Department for Computer Science TU München Chair for Network Architectures and Services Prof. Carle Department for Computer Science TU München Master

More information

Lecture 13: Interconnection Networks. Topics: lots of background, recent innovations for power and performance

Lecture 13: Interconnection Networks. Topics: lots of background, recent innovations for power and performance Lecture 13: Interconnection Networks Topics: lots of background, recent innovations for power and performance 1 Interconnection Networks Recall: fully connected network, arrays/rings, meshes/tori, trees,

More information

NoC Simulation in Heterogeneous Architectures for PGAS Programming Model

NoC Simulation in Heterogeneous Architectures for PGAS Programming Model NoC Simulation in Heterogeneous Architectures for PGAS Programming Model Sascha Roloff, Andreas Weichslgartner, Frank Hannig, Jürgen Teich University of Erlangen-Nuremberg, Germany Jan Heißwolf Karlsruhe

More information

Design and Implementation of Lookup Table in Multicast Supported Router

Design and Implementation of Lookup Table in Multicast Supported Router 2011 International Conference on Computer Science and Information Technology (ICCSIT 2011) IPCSIT vol. 51 (2012) (2012) IACSIT Press, Singapore DOI: 10.7763/IPCSIT.2012.V51. 119 Design and Implementation

More information

Network Support for Multimedia

Network Support for Multimedia Network Support for Multimedia Daniel Zappala CS 460 Computer Networking Brigham Young University Network Support for Multimedia 2/33 make the best of best effort use application-level techniques use CDNs

More information