ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
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1 1 ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology Mikkel B. Stensgaard and Jens Sparsø Technical University of Denmark Technical University of Denmark
2 Outline 2 Motivation ReNoC Basic Concepts Physical Architecture Logical Topology Generalization Evaluation Conclusion
3 Motivation 3 System-on-Chips Increasing... Transistor count and complexity Increasing... Development time Increasing... Test time Increasing... Production costs Pushes towards a general SoC platform
4 General SoC Platform 4 FPGA like platform for SoC Pre-tested Large volumes Shorter time-to-market Domain specific SoC platforms No single platform can be used for everything Typical IP-Blocks RAMs, CPUs, IOs, FPGAs Other coarse grained blocks Communication infrastructure Flexible NoC
5 Flexible NoC for Platform chip 5 Challenge Flexibility Support a wide range of communication scenarios QoS and other advanced features Energy and area efficient Current Solution: Packet-switched NoC General topology (typically 2D mesh) Only fraction of total capacity is ever used Large part of chip area and power Application specific topologies Much more power and area effective [Murali, Srinivasan] Only possible for a single application
6 Switching Methods 6 Packet-switching (Packets routed individually) - Routing, buffering and arbitration is needed + Links can be shared [Ætherial, Xpipes, and more] Physical circuit-switching (Physical point-to-point connections) + No routing, buffering and arbitration is needed - Links are dedicated (No sharing) [ An energy-efficient reconfigurable circuit-switched network-on-chip, Wolkotte et al] Packet-switching Circuit-switching Size - + Energy - + Flexible + -
7 Reconfigurable NoC (ReNoC) 7 Topology can be configured by application Application specific topology Minimize amount of packet-switching Best from packet- and circuit-switching Energy efficiency from circuit-switching Flexibility from packet-switching
8 Reconfigurable NoC (ReNoC) 8 Topology can be configured by application Application specific topology Minimize amount of packet-switching Best from packet- and circuit-switching Energy efficiency from circuit-switching Flexibility from packet-switching Logical Physical
9 Physical Architecture 9 Links Network nodes Topology switch Router Can use any existing router Quality-of-Service Virtual Channels Clocked or Clockless Simple physical architecture:
10 Topology Switches 10 Inserted as a layer between routers and links Goal: Minimal area and energy overhead Infrequent configuration Non-full connectivity Example: Topology switch for 2D mesh 5 links/ip-block 5 router ports Full connectivity 10x10 switch
11 Topology Switches 11 Inserted as a layer between routers and links Goal: Minimal area and energy overhead Infrequent configuration Non-full connectivity Example: Topology switch for 2D mesh Router port corresponding link
12 Topology Switches 12 Inserted as a layer between routers and links Goal: Minimal area and energy overhead Infrequent configuration Non-full connectivity Example: Topology switch for 2D mesh Router port corresponding link Link Any other Link (Except itself) Link Router port
13 Implementation 13 Analogue to switch-boxes in FPGAs Efficient implementations Pass-gates, tristate buffers, or multiplexers Configured using Serial interface, separate network or network itself Example: Topology switch for 2D mesh 5, 4-input multiplexers!
14 Logical Topology 14 Application experience this as static topology Widely different topologies are possible Routers/links become a sharable resource Unused routers/links can be powerand clock-gated Logical links Router to Router IP-Block to IP-Block IP-Block to Router Local / long links
15 Generalization 15 Any Physical Topology Tree, Mesh, etc Heterogeneous Hierarchical Network Nodes Router Topology Switch Topology Switch + Router Links Uni- and bi-directional Local and non-local Router Less ports than number of links as it is a sharable resource
16 Evaluation 16 Demonstrate ReNoC Evaluate overhead of Topology Switches (Configuration is not considered) Physical architecture:
17 Application 17 Video Object Plane Decoder (VOPD) Application [ Mapping of MPEG-4 decoding on a flexible architecture platform, van der Tol and Jaspers] Task graph: (Bandwidth in Mbit/second)
18 Architectures 18 Static Mesh: 2D mesh topology without topology switches Used as reference ReNoC mesh: ReNoC architecture configured as 2D mesh Estimate overhead ReNoC specific: ReNoC architecture configured with application specific topology Estimate power savings ReNoC specific:
19 Implementation 19 Router Simple, Low power 100 MHz, single-cycle Source-routed, input buffered, 32 bit flits 2 Virtual Channels per input port (4 flits deep) Credit-based flow-control Topology Switch Multiplexer based Configuration by registers Technology 90nm, low-leakage cells,1 V Routers and topology switches were synthesized Power estimated using random-data at 20% utilization Link SPICE simulated [ A power and energy exploration of network-on-chip architectures,banerjee et al]
20 Area/ Energy figures 20 Module Area (mm 2 ) Enegy/packet (pj) Idle Power (uw) 5x5 Router 0, x5 Topology Switch 0,007 0,6-0,8 - Link Router vs. topology switch ~9 times larger ~45 times more energy / packet +Idle power
21 Results 21 ReNoC mesh vs. static mesh Area increase: 10% Power increase: 3% Architecture Area (mm 2 ) Power (mw) Static mesh 0,53 4,56 ReNoC mesh 0,58 4,69 ReNoC specific 0,58 2,02 ReNoC specific vs. static mesh Power decrease: 56% Topology switches use 5% of power (Note: Details can be found in article)
22 Discussion 22 Presentation focused on main ideas Additional issues include Configuration of topology switches Slowest logical link determines clock-frequency Clock-skew Few router ports were used in evaluation High-performance (pipelining) Routers with fewer ports might be a choice Ports becomes a sharable resource Smaller routers, but general 2D mesh not possible
23 Future Work 23 Automatic generation of Physical architectures Logical topologies Topology switch implementations Configuration methods Serial link Separate network Network itself
24 Conclusion 24 ReNoC enables logical topology to be configured Application Specific topologies Exploit knowledge of communication Best from packet- and circuit-switching Efficiency from circuit-switching Flexibility from packet-switching Enables general SoC platforms
25 Thank you 25 Thank you
26 Results, detailed 26
27 Characterization, detailed 27
28 Router 28
29 Router Breakdown 29
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