Real-Time Mixed-Criticality Wormhole Networks
|
|
|
- Malcolm Booth
- 5 years ago
- Views:
Transcription
1 eal-time Mixed-Criticality Wormhole Networks Leandro Soares Indrusiak eal-time Systems Group Department of Computer Science University of York United Kingdom eal-time Systems Group 1
2 Outline Wormhole Networks Networks-on-Chip eal-time Analysis Mixed-Criticality Analysis eal-time Systems Group 2
3 source: IBM, Intel Motivation Multiprocessor and multicore systems forced a shift towards communicationcentric design abundant computation resources shared communication media Leandro Soares Indrusiak Inter-processor communication point-to-point bus networks eal-time Systems Group 3
4 Networks key characteristics topology mesh, star, torus routing protocol deterministic, adaptive arbitration round-robin, priority preemptive, priority nonpreemptive, TDM buffering FIFO, SAFC, SAMQ, DAMQ, hot potato flow control protocol handshake, credit-based switching protocol circuit, store-and-forward, wormhole eal-time Systems Group 4
5 Networks key characteristics topology mesh, star, torus routing protocol deterministic, adaptive arbitration round-robin, priority preemptive, priority nonpreemptive, TDM buffering FIFO, SAFC, SAMQ, DAMQ, hot potato flow control protocol handshake, credit-based switching protocol circuit, store-and-forward, wormhole eal-time Systems Group 5
6 Circuit ing Terminal Terminal eal-time Systems Group 6
7 Circuit ing Terminal Terminal eal-time Systems Group 7
8 Circuit ing Terminal Terminal eal-time Systems Group 8
9 Circuit ing Terminal Terminal eal-time Systems Group 9
10 Circuit ing Terminal Terminal eal-time Systems Group 10
11 Circuit ing Terminal A segment of reserved path is idle for a significant period of time. Terminal eal-time Systems Group 11
12 Circuit ing Terminal A segment of reserved path is idle for a significant period of time. Terminal eal-time Systems Group 12
13 Circuit ing Terminal A segment of reserved path is idle for a significant period of time. Terminal eal-time Systems Group 13
14 Circuit ing Terminal A segment of reserved path is idle for a significant period of time. Terminal eal-time Systems Group 14
15 Circuit ing Terminal A segment of reserved path is idle for a significant period of time. Terminal eal-time Systems Group 15
16 Circuit ing Terminal A segment of reserved path is idle for a significant period of time. Terminal eal-time Systems Group 16
17 Circuit ing Terminal A segment of reserved path is idle for a significant period of time. Terminal eal-time Systems Group 17
18 Circuit ing Terminal A segment of reserved path is idle for a significant period of time. Terminal eal-time Systems Group 18
19 Circuit ing Terminal A segment of reserved path is idle for a significant period of time. Terminal eal-time Systems Group 19
20 Circuit switching Packets are forwarded through dedicated paths that are kept until the transmission is finished Contention can arise when establishing a path no further contention once path is established Temporary packet buffering in routers is not required Suitable to long and infrequent messages time to establish a path can be high eal-time Systems Group 20
21 SAF ing Terminal eal-time Systems Group 21
22 SAF ing Terminal eal-time Systems Group 22
23 SAF ing Terminal eal-time Systems Group 23
24 SAF ing Terminal eal-time Systems Group 24
25 SAF ing Terminal eal-time Systems Group 25
26 SAF ing Terminal eal-time Systems Group 26
27 SAF ing Terminal eal-time Systems Group 27
28 SAF ing Terminal eal-time Systems Group 28
29 SAF ing Terminal eal-time Systems Group 29
30 SAF ing Terminal eal-time Systems Group 30
31 SAF ing Terminal eal-time Systems Group 31
32 SAF ing Terminal eal-time Systems Group 32
33 SAF ing Terminal eal-time Systems Group 33
34 SAF ing SAF - Store And Forward outers can only forward a packet once it is completely received and stored packet acquires one link at a time outer input ports must have enough buffering space to temporarily store a complete packet eal-time Systems Group 34
35 Wormhole ing Terminal eal-time Systems Group 35
36 Wormhole ing Terminal eal-time Systems Group 36
37 Wormhole ing Terminal eal-time Systems Group 37
38 Wormhole ing Terminal eal-time Systems Group 38
39 Wormhole ing Terminal eal-time Systems Group 39
40 Wormhole ing Terminal eal-time Systems Group 40
41 Wormhole ing Terminal eal-time Systems Group 41
42 Wormhole switching Packet is routed and forwarded as soon the header flit has arrived payload flits follow header Input ports does not need to buffer a complete packet flits of a packet can be stored across multiple routers Trade-off between buffer overheads and network contention eal-time Systems Group 42
43 Wormhole Networks-on-Chip Small buffering overheads of wormhole networks was particularly attractive to a special class of resourceconstrained networks: Networks-on-Chip (NoCs) small buffers mean smaller area and lower energy dissipation eal-time Systems Group 43
44 Wormhole Networks-on-Chip outer Core Link eal-time Systems Group 44
45 Wormhole Networks-on-Chip Link eal-time Systems Group 45
46 Wormhole Networks-on-Chip arbitration data in data out data in data in routing & transmission control data out data out data in data out data in data out eal-time Systems Group 46
47 NoC parallelism and scalability CPU CPU I/O Multiple connections simultaneously AM CPU CPU eal-time Systems Group 47
48 NoC performance CPU CPU I/O task contention leads to latency variability link contention leads to latency variability AM CPU CPU eal-time Systems Group 48
49 Wormhole Networks-on-Chip eal-time Systems Group 49
50 Wormhole Networks-on-Chip eal-time Systems Group 50
51 Wormhole Networks-on-Chip eal-time Systems Group 51
52 Wormhole Networks-on-Chip eal-time Systems Group 52
53 Wormhole Networks-on-Chip eal-time Systems Group 53
54 Wormhole Networks-on-Chip eal-time Systems Group 54
55 Wormhole Networks-on-Chip packet is blocked eal-time Systems Group 55
56 Wormhole Networks-on-Chip eal-time Systems Group 56
57 Wormhole Networks-on-Chip eal-time Systems Group 57
58 Wormhole Networks-on-Chip new packet released eal-time Systems Group 58
59 Wormhole Networks-on-Chip eal-time Systems Group 59
60 Wormhole Networks-on-Chip eal-time Systems Group 60
61 Wormhole Networks-on-Chip eal-time Systems Group 61
62 Wormhole Networks-on-Chip eal-time Systems Group 62
63 Wormhole Networks-on-Chip Packets can acquire multiple links, making it hard to predict worst-case latency due to complex contention patterns Alternative: wormhole NoCs using virtual channels with priority preemptive arbitration eal-time Systems Group 63
64 Priority preemptive virtual channels Leandro Soares Indrusiak priority ID highest priority with remaining credit data_in credit_out routing & transmission control data_out credit_in eal-time Systems Group 64
65 Priority preemptive virtual channels Leandro Soares Indrusiak wormhole NoC with priority preemptive virtual channels eal-time Systems Group 65
66 Priority preemptive virtual channels Leandro Soares Indrusiak wormhole NoC with priority preemptive virtual channels eal-time Systems Group 66
67 Priority preemptive virtual channels Leandro Soares Indrusiak wormhole NoC with priority preemptive virtual channels high priority packet released eal-time Systems Group 67
68 Priority preemptive virtual channels Leandro Soares Indrusiak wormhole NoC with priority preemptive virtual channels eal-time Systems Group 68
69 Priority preemptive virtual channels Leandro Soares Indrusiak wormhole NoC with priority preemptive virtual channels eal-time Systems Group 69
70 Priority preemptive virtual channels first packet is preempted wormhole NoC with priority preemptive virtual channels eal-time Systems Group 70
71 Priority preemptive virtual channels Leandro Soares Indrusiak wormhole NoC with priority preemptive virtual channels eal-time Systems Group 71
72 Priority preemptive virtual channels Leandro Soares Indrusiak wormhole NoC with priority preemptive virtual channels eal-time Systems Group 72
73 Priority preemptive virtual channels Leandro Soares Indrusiak wormhole NoC with priority preemptive virtual channels eal-time Systems Group 73
74 Priority preemptive virtual channels Leandro Soares Indrusiak wormhole NoC with priority preemptive virtual channels eal-time Systems Group 74
75 Priority preemptive virtual channels Leandro Soares Indrusiak wormhole NoC with priority preemptive virtual channels eal-time Systems Group 75
76 Priority preemptive virtual channels Leandro Soares Indrusiak wormhole NoC with priority preemptive virtual channels eal-time Systems Group 76
77 Priority preemptive virtual channels Leandro Soares Indrusiak wormhole NoC with priority preemptive virtual channels eal-time Systems Group 77
78 Performance evaluation How to estimate performance figures for a particular application mapped to a Network-on-Chip? full system prototyping cores + NoC in FPGA, running OS + application extremely costly setup time, can only explore few design alternatives accurate system simulation cycle-accurate model of cores + NoC, running OS + application extremely long simulation time, can only explore few design alternatives approximately-timed system simulation approximately-timed model of cores + NoC, executing an abstract model of the OS + application analytical system performance models average or worst-case latency estimation for restricted application styles (periodic independent tasks, synchronous dataflow, etc.) eal-time Systems Group 78
79 Performance evaluation How to estimate performance figures for a particular application mapped to a Network-on-Chip? full system prototyping cores + NoC in FPGA, running OS + application extremely costly setup time, can only explore few design alternatives accurate system simulation cycle-accurate model of cores + NoC, running OS + application extremely long simulation time, can only explore few design alternatives approximately-timed system simulation approximately-timed model of cores + NoC, executing an abstract model of the OS + application analytical system performance models average or worst-case latency estimation for restricted application styles (periodic independent tasks, synchronous dataflow, etc.) eal-time Systems Group 79
80 End-to-End esponse Time Analysis (E2ETA) The worst-case end-to-end response time of a task is the longest time consumed between its release and the moment when the last packet it transmits arrives at the destination core It can be found by a specific composition of: worst case response time of tasks based on classical single processor schedulability analysis (Audsley et al., 1993) worst case latency of traffic flows based on the NoC schedulability analysis (Shi and Burns, 2008) It assumes that: the minimum inter-release time of each task (T) and its worst case computation time (C) are known the source task only starts transmitting packets after it finishes its execution system uses priority-preemptive arbitration L.S. Indrusiak, End-to-End Schedulability Tests for Multiprocessor Embedded Systems based on Networks-on-Chip with Priority-Preemptive Arbitration, Journal of Systems Architecture, v. 60, n. 7, Aug eal-time Systems Group 80
81 End-to-End esponse Time Analysis (E2ETA) Leandro Soares Indrusiak period (T) = deadline (D) response time of the task computation response time of the task communication L.S. Indrusiak, End-to-End Schedulability Tests for Multiprocessor Embedded Systems based on Networks-on-Chip with Priority-Preemptive Arbitration, Journal of Systems Architecture, v. 60, n. 7, Aug eal-time Systems Group 81
82 End-to-End esponse Time Analysis (E2ETA) Deadline (D) = Period of Task (T) End-to-end response time analysis: a task is schedulable if a packet flow is schedulable if Otherwise, system is unschedulable L.S. Indrusiak, End-to-End Schedulability Tests for Multiprocessor Embedded Systems based on Networks-on-Chip with Priority-Preemptive Arbitration, Journal of Systems Architecture, v. 60, n. 7, Aug eal-time Systems Group 82
83 End-to-End esponse Time Analysis (E2ETA) Leandro Soares Indrusiak precedence relationship must solve task s response time first, and add it as the release jitter of the flow s response time calculation eal-time Systems Group 83
84 End-to-End esponse Time Analysis (E2ETA) Leandro Soares Indrusiak recurrence relationships can be solved iteratively until convergence require safe initial value eal-time Systems Group 84
85 End-to-End esponse Time Analysis (E2ETA) Leandro Soares Indrusiak must identify interference sets, i.e. which tasks Task j (or flows Flow j ) can preempt a given task Task i (or flow Flow i ) eal-time Systems Group 85
86 End-to-End esponse Time Analysis (E2ETA) Complexity of E2ETA scales with size of NoC Leandro Soares Indrusiak complexity of application (# tasks and # flows) and of the allocation (amount of resource contention) Performance of E2ETA is orders of magnitude faster than the fastest available NoC simulation E2ETA has been further optimised and hardware-accelerated Y. Ma and L.S. Indrusiak, Hardware-accelerated esponse Time Analysis for Priority-Preemptive Networks-on-Chip, in Int Symposium on econfigurable Communication-centric Systems-on-Chip (ecosoc), eal-time Systems Group 86
87 Outline Wormhole Networks Networks-on-Chip eal-time Analysis Mixed-Criticality Analysis eal-time Systems Group 87
88 Outline Wormhole Networks Networks-on-Chip eal-time Analysis Mixed-Criticality Analysis rant time!! eal-time Systems Group 88
89 Outline Wormhole Networks Networks-on-Chip eal-time Analysis Mixed-Criticality Analysis eal-time Systems Group 89
90 Mixed-criticality packet communication in NoCs Packet flows of different levels of criticality can share the NoC infrastructure Initial work considers only two levels of criticality, and packet flows are assigned a criticality level at design time: HI-CIT or LO-CIT Packet flows are also assigned fixed priorities at design time HI-CIT packet flows make more conservative assumptions about the environment and therefore have more conservative upper bounds for their resource provisions however, it is expected that during normal operation mode their resource usage stays within the bounds obtained using less conservative assumptions used for LO-CIT packets eal-time Systems Group 90
91 Mixed-criticality packet communication in NoCs Possible sources of uncertainty packet length packet flow period C C C All packet flows must be schedulable under normal mode C C C untime monitoring detects when packets go beyond normal e.g. packets longer than expected, or injected more often than expected in normal mode C C C network interface eal-time Systems Group 91
92 Mixed-criticality packet communication in NoCs untime monitoring detects when packets go beyond normal if it is a LO-CIT packet exceeding its normal budget, reject it if it is a HI-CIT packet exceeding its normal budget, signal a mode change to the NoC, aiming to notify that a service degradation to LO-CIT packets is needed so that HI-CIT packets can still be scheduled despite of potential increase of interference due to overbudget packets C C C C C C C C mode change notification C eal-time Systems Group 92
93 Mixed-criticality packet communication in NoCs Two mode change propagation protocols C C C WPMC: mode change flag piggybacked on packets that pass through a router that has changed mode WPMC-FLOOD: mode change is flooded to the entire NoC C C C C C C A. Burns, J. Harbin, L. S. Indrusiak: A Wormhole NoC Protocol for Mixed Criticality Systems. TSS 2014: eal-time Systems Group 93
94 Mixed-criticality packet communication in NoCs Two mode change propagation protocols C C C WPMC: mode change flag piggybacked on packets that pass through a router that has changed mode WPMC-FLOOD: mode change is flooded to the entire NoC C C C C C C L. S. Indrusiak, J. Harbin, A. Burns: Average and Worst-Case Latency Improvements in Mixed-Criticality Wormhole Networks-on-Chip. ECTS eal-time Systems Group 94
95 Mixed-criticality packet communication in NoCs Two HI-CIT mode arbitration schemes C C C routers that change mode ignore arbitration requests of LO-CIT packets C C C routers that change mode arbitrate links in criticality order (HI-CIT then LO-CIT), and in priority order within the same criticality C C C A. Burns, J. Harbin, L. S. Indrusiak: A Wormhole NoC Protocol for Mixed Criticality Systems. TSS 2014: eal-time Systems Group 95
96 Mixed-criticality packet communication in NoCs Two HI-CIT mode arbitration schemes C C C routers that change mode ignore arbitration requests of LO-CIT packets C C C routers that change mode arbitrate links in criticality order (HI-CIT then LO-CIT), and in priority order within the same criticality C C C L. S. Indrusiak, J. Harbin, A. Burns: Average and Worst-Case Latency Improvements in Mixed-Criticality Wormhole Networks-on-Chip. ECTS eal-time Systems Group 96
97 Mixed-criticality packet communication in NoCs esponse Time Analysis formulations for each of the protocols were developed Evaluation with synthetic flowsets (against no criticality awareness and criticalitymonotonic arbitration) and cycle-accurate NoC simulation WPMC-FLOOD slightly better in general, significantly better in stress scenarios Less restrictive arbitration allows LO-CIT packets to flow when there are no HI-CIT packets or when they are blocked due to interferences A. Burns, J. Harbin, L. S. Indrusiak: A Wormhole NoC Protocol for Mixed Criticality Systems. TSS 2014: L. S. Indrusiak, J. Harbin, A. Burns: Average and Worst-Case Latency Improvements in Mixed-Criticality Wormhole Networks-on-Chip. ECTS eal-time Systems Group 97
98 Mixed-criticality packet communication in NoCs esponse Time Analysis formulations for each of the protocols were developed Evaluation with synthetic flowsets (against no criticality awareness and criticality-monotonic arbitration) and cycle-accurate NoC simulation WPMC-FLOOD slightly better in general, significantly better in stress scenarios Less restrictive arbitration allows LO-CIT packets to flow when there are no HI-CIT packets or when they are blocked due to interferences L. S. Indrusiak, J. Harbin, A. Burns: Average and Worst-Case Latency Improvements in Mixed-Criticality Wormhole Networks-on-Chip. ECTS eal-time Systems Group 98
99 Mixed-criticality packet communication in NoCs esponse Time Analysis formulations for each of the protocols were developed Evaluation with synthetic flowsets (against no criticality awareness and criticalitymonotonic arbitration) and cycle-accurate NoC simulation WPMC-FLOOD slightly better in general, significantly better in stress scenarios Less restrictive arbitration allows LO- CIT packets to flow when there are no HI-CIT packets or when they are blocked due to interferences L. S. Indrusiak, J. Harbin, A. Burns: Average and Worst-Case Latency Improvements in Mixed-Criticality Wormhole Networks-on-Chip. ECTS eal-time Systems Group 99
100 Open questions Leandro Soares Indrusiak How to detect that the network has returned to normal mode, so LO-CIT service and guarantees can be restored? Can we give reasonable guarantees in networks with non-preemptive arbitration? Can we optimise task allocation and packet routing? Benchmarks? eal-time Systems Group 100
101 eal-time Mixed-Criticality Wormhole Networks Leandro Soares Indrusiak, with contributions from: Alan Burns, ob Davis, Iain Bate, James Harbin Mixed Criticality Embedded Systems on Many-Core Platforms EPSC EP/K011626/1 Project MCCps - Mixed Criticality Cyber- Physical Systems EPSC EP/P003664/1 Project eal-time Systems Group 101
AirTight: A Resilient Wireless Communication Protocol for Mixed- Criticality Systems
AirTight: A Resilient Wireless Communication Protocol for Mixed- Criticality Systems Alan Burns, James Harbin, Leandro Indrusiak, Iain Bate, Robert Davis and David Griffin Real-Time Systems Research Group
BlueVisor: A Scalable Real-time Hardware Hypervisor for Many-core Embedded System
BlueVisor: A Scalable eal-time Hardware Hypervisor for Many-core Embedded System Zhe Jiang, Neil C Audsley, Pan Dong eal-time Systems Group Department of Computer Science University of York, United Kingdom
Efficient Throughput-Guarantees for Latency-Sensitive Networks-On-Chip
ASP-DAC 2010 20 Jan 2010 Session 6C Efficient Throughput-Guarantees for Latency-Sensitive Networks-On-Chip Jonas Diemer, Rolf Ernst TU Braunschweig, Germany diemer@ida.ing.tu-bs.de Michael Kauschke Intel,
Mapping of Real-time Applications on
Mapping of Real-time Applications on Network-on-Chip based MPSOCS Paris Mesidis Submitted for the degree of Master of Science (By Research) The University of York, December 2011 Abstract Mapping of real
Real-Time Communication Services for Networks on Chip. Zheng Shi
Real-Time Communication Services for Networks on Chip Zheng Shi Submitted for the degree of Doctor of Philosophy Computer Science The University of York November 2009 Abstract Networks-on-Chip (NoCs),
Flow Control can be viewed as a problem of
NOC Flow Control 1 Flow Control Flow Control determines how the resources of a network, such as channel bandwidth and buffer capacity are allocated to packets traversing a network Goal is to use resources
Efficient Latency Guarantees for Mixed-criticality Networks-on-Chip
Platzhalter für Bild, Bild auf Titelfolie hinter das Logo einsetzen Efficient Latency Guarantees for Mixed-criticality Networks-on-Chip Sebastian Tobuschat, Rolf Ernst IDA, TU Braunschweig, Germany 18.
FIST: A Fast, Lightweight, FPGA-Friendly Packet Latency Estimator for NoC Modeling in Full-System Simulations
FIST: A Fast, Lightweight, FPGA-Friendly Packet Latency Estimator for oc Modeling in Full-System Simulations Michael K. Papamichael, James C. Hoe, Onur Mutlu papamix@cs.cmu.edu, jhoe@ece.cmu.edu, onur@cmu.edu
Probabilistic Worst-Case Response-Time Analysis for the Controller Area Network
Probabilistic Worst-Case Response-Time Analysis for the Controller Area Network Thomas Nolte, Hans Hansson, and Christer Norström Mälardalen Real-Time Research Centre Department of Computer Engineering
Network on Chip Architecture: An Overview
Network on Chip Architecture: An Overview Md Shahriar Shamim & Naseef Mansoor 12/5/2014 1 Overview Introduction Multi core chip Challenges Network on Chip Architecture Regular Topology Irregular Topology
Thomas Moscibroda Microsoft Research. Onur Mutlu CMU
Thomas Moscibroda Microsoft Research Onur Mutlu CMU CPU+L1 CPU+L1 CPU+L1 CPU+L1 Multi-core Chip Cache -Bank Cache -Bank Cache -Bank Cache -Bank CPU+L1 CPU+L1 CPU+L1 CPU+L1 Accelerator, etc Cache -Bank
Achieving Lightweight Multicast in Asynchronous Networks-on-Chip Using Local Speculation
Achieving Lightweight Multicast in Asynchronous Networks-on-Chip Using Local Speculation Kshitij Bhardwaj Dept. of Computer Science Columbia University Steven M. Nowick 2016 ACM/IEEE Design Automation
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow Abstract: High-level synthesis (HLS) of data-parallel input languages, such as the Compute Unified Device Architecture
A VERIOG-HDL IMPLEMENTATION OF VIRTUAL CHANNELS IN A NETWORK-ON-CHIP ROUTER. A Thesis SUNGHO PARK
A VERIOG-HDL IMPLEMENTATION OF VIRTUAL CHANNELS IN A NETWORK-ON-CHIP ROUTER A Thesis by SUNGHO PARK Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements
OASIS NoC Architecture Design in Verilog HDL Technical Report: TR OASIS
OASIS NoC Architecture Design in Verilog HDL Technical Report: TR-062010-OASIS Written by Kenichi Mori ASL-Ben Abdallah Group Graduate School of Computer Science and Engineering The University of Aizu
Module 17: "Interconnection Networks" Lecture 37: "Introduction to Routers" Interconnection Networks. Fundamentals. Latency and bandwidth
Interconnection Networks Fundamentals Latency and bandwidth Router architecture Coherence protocol and routing [From Chapter 10 of Culler, Singh, Gupta] file:///e /parallel_com_arch/lecture37/37_1.htm[6/13/2012
Quest for High-Performance Bufferless NoCs with Single-Cycle Express Paths and Self-Learning Throttling
Quest for High-Performance Bufferless NoCs with Single-Cycle Express Paths and Self-Learning Throttling Bhavya K. Daya, Li-Shiuan Peh, Anantha P. Chandrakasan Dept. of Electrical Engineering and Computer
Lecture 18: Communication Models and Architectures: Interconnection Networks
Design & Co-design of Embedded Systems Lecture 18: Communication Models and Architectures: Interconnection Networks Sharif University of Technology Computer Engineering g Dept. Winter-Spring 2008 Mehdi
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
Trade Offs in the Design of a Router with Both Guaranteed and BestEffort Services for Networks on Chip E. Rijpkema, K. Goossens, A. R dulescu, J. Dielissen, J. van Meerbergen, P. Wielage, and E. Waterlander
Embedded Systems: Hardware Components (part II) Todor Stefanov
Embedded Systems: Hardware Components (part II) Todor Stefanov Leiden Embedded Research Center, Leiden Institute of Advanced Computer Science Leiden University, The Netherlands Outline Generic Embedded
NOC: Networks on Chip SoC Interconnection Structures
NOC: Networks on Chip SoC Interconnection Structures COE838: Systems-on-Chip Design http://www.ee.ryerson.ca/~courses/coe838/ Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering
Memory Architectures for NoC-Based Real-Time Mixed Criticality Systems
Memory Architectures for NoC-Based Real-Time Mixed Criticality Systems Neil Audsley Real-Time Systems Group Computer Science Department University of York York United Kingdom 2011-12 1 Overview Motivation:
A Thermal-aware Application specific Routing Algorithm for Network-on-chip Design
A Thermal-aware Application specific Routing Algorithm for Network-on-chip Design Zhi-Liang Qian and Chi-Ying Tsui VLSI Research Laboratory Department of Electronic and Computer Engineering The Hong Kong
Networks: Routing, Deadlock, Flow Control, Switch Design, Case Studies. Admin
Networks: Routing, Deadlock, Flow Control, Switch Design, Case Studies Alvin R. Lebeck CPS 220 Admin Homework #5 Due Dec 3 Projects Final (yes it will be cumulative) CPS 220 2 1 Review: Terms Network characterized
SoC Design Lecture 13: NoC (Network-on-Chip) Department of Computer Engineering Sharif University of Technology
SoC Design Lecture 13: NoC (Network-on-Chip) Department of Computer Engineering Sharif University of Technology Outline SoC Interconnect NoC Introduction NoC layers Typical NoC Router NoC Issues Switching
TDT Appendix E Interconnection Networks
TDT 4260 Appendix E Interconnection Networks Review Advantages of a snooping coherency protocol? Disadvantages of a snooping coherency protocol? Advantages of a directory coherency protocol? Disadvantages
Cross Clock-Domain TDM Virtual Circuits for Networks on Chips
Cross Clock-Domain TDM Virtual Circuits for Networks on Chips Zhonghai Lu Dept. of Electronic Systems School for Information and Communication Technology KTH - Royal Institute of Technology, Stockholm
OASIS Network-on-Chip Prototyping on FPGA
Master thesis of the University of Aizu, Feb. 20, 2012 OASIS Network-on-Chip Prototyping on FPGA m5141120, Kenichi Mori Supervised by Prof. Ben Abdallah Abderazek Adaptive Systems Laboratory, Master of
FPGA based Design of Low Power Reconfigurable Router for Network on Chip (NoC)
FPGA based Design of Low Power Reconfigurable Router for Network on Chip (NoC) D.Udhayasheela, pg student [Communication system],dept.ofece,,as-salam engineering and technology, N.MageshwariAssistant Professor
Interconnection Networks
Lecture 17: Interconnection Networks Parallel Computer Architecture and Programming A comment on web site comments It is okay to make a comment on a slide/topic that has already been commented on. In fact
Application-Platform Mapping in Multiprocessor Systems-on-Chip
Application-Platform Mapping in Multiprocessor Systems-on-Chip Leandro Soares Indrusiak lsi@cs.york.ac.uk http://www-users.cs.york.ac.uk/lsi CREDES Kick-off Meeting Tallinn - June 2009 Application-Platform
NoC Test-Chip Project: Working Document
NoC Test-Chip Project: Working Document Michele Petracca, Omar Ahmad, Young Jin Yoon, Frank Zovko, Luca Carloni and Kenneth Shepard I. INTRODUCTION This document describes the low-power high-performance
Improving Routing Efficiency for Network-on-Chip through Contention-Aware Input Selection
Improving Routing Efficiency for Network-on-Chip through Contention-Aware Input Selection Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz School of Electronics and Computer Science University of Southampton
MEMORY/RESOURCE MANAGEMENT IN MULTICORE SYSTEMS
MEMORY/RESOURCE MANAGEMENT IN MULTICORE SYSTEMS INSTRUCTOR: Dr. MUHAMMAD SHAABAN PRESENTED BY: MOHIT SATHAWANE AKSHAY YEMBARWAR WHAT IS MULTICORE SYSTEMS? Multi-core processor architecture means placing
Interconnection Networks: Flow Control. Prof. Natalie Enright Jerger
Interconnection Networks: Flow Control Prof. Natalie Enright Jerger Switching/Flow Control Overview Topology: determines connectivity of network Routing: determines paths through network Flow Control:
Design and Implementation of Low Complexity Router for 2D Mesh Topology using FPGA
Design and Implementation of Low Complexity Router for 2D Mesh Topology using FPGA Maheswari Murali * and Seetharaman Gopalakrishnan # * Assistant professor, J. J. College of Engineering and Technology,
Routing Algorithms, Process Model for Quality of Services (QoS) and Architectures for Two-Dimensional 4 4 Mesh Topology Network-on-Chip
Routing Algorithms, Process Model for Quality of Services (QoS) and Architectures for Two-Dimensional 4 4 Mesh Topology Network-on-Chip Nauman Jalil, Adnan Qureshi, Furqan Khan, and Sohaib Ayyaz Qazi Abstract
Routing Algorithm. How do I know where a packet should go? Topology does NOT determine routing (e.g., many paths through torus)
Routing Algorithm How do I know where a packet should go? Topology does NOT determine routing (e.g., many paths through torus) Many routing algorithms exist 1) Arithmetic 2) Source-based 3) Table lookup
Evaluation of NOC Using Tightly Coupled Router Architecture
IOSR Journal of Computer Engineering (IOSR-JCE) e-issn: 2278-0661,p-ISSN: 2278-8727, Volume 18, Issue 1, Ver. II (Jan Feb. 2016), PP 01-05 www.iosrjournals.org Evaluation of NOC Using Tightly Coupled Router
Lecture: Interconnection Networks
Lecture: Interconnection Networks Topics: Router microarchitecture, topologies Final exam next Tuesday: same rules as the first midterm 1 Packets/Flits A message is broken into multiple packets (each packet
OpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel
OpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel Hyoukjun Kwon and Tushar Krishna Georgia Institute of Technology Synergy Lab (http://synergy.ece.gatech.edu) hyoukjun@gatech.edu April
The Nostrum Network on Chip
The Nostrum Network on Chip 10 processors 10 processors Mikael Millberg, Erland Nilsson, Richard Thid, Johnny Öberg, Zhonghai Lu, Axel Jantsch Royal Institute of Technology, Stockholm November 24, 2004
Supporting Critical Modes in AirTight
Supporting Critical Modes in AirTight J. Harbin, D. Griffin, A. Burns, I. Bate, R.I. Davis and L.S. Indrusiak Department of Computer Science, University of York, UK. Abstract The AirTight protocol supports
Fast Flexible FPGA-Tuned Networks-on-Chip
This work was funded by NSF. We thank Xilinx for their FPGA and tool donations. We thank Bluespec for their tool donations. Fast Flexible FPGA-Tuned Networks-on-Chip Michael K. Papamichael, James C. Hoe
Lecture 24: Interconnection Networks. Topics: topologies, routing, deadlocks, flow control
Lecture 24: Interconnection Networks Topics: topologies, routing, deadlocks, flow control 1 Topology Examples Grid Torus Hypercube Criteria Bus Ring 2Dtorus 6-cube Fully connected Performance Bisection
The Design and Implementation of a Low-Latency On-Chip Network
The Design and Implementation of a Low-Latency On-Chip Network Robert Mullins 11 th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan 24-27 th, 2006, Yokohama, Japan. Introduction Current
Multimedia Systems 2011/2012
Multimedia Systems 2011/2012 System Architecture Prof. Dr. Paul Müller University of Kaiserslautern Department of Computer Science Integrated Communication Systems ICSY http://www.icsy.de Sitemap 2 Hardware
Low Cost Network on Chip Router Design for Torus Topology
IJCSNS International Journal of Computer Science and Network Security, VOL.17 No.5, May 2017 287 Low Cost Network on Chip Router Design for Torus Topology Bouraoui Chemli and Abdelkrim Zitouni Electronics
Real Time NoC Based Pipelined Architectonics With Efficient TDM Schema
Real Time NoC Based Pipelined Architectonics With Efficient TDM Schema [1] Laila A, [2] Ajeesh R V [1] PG Student [VLSI & ES] [2] Assistant professor, Department of ECE, TKM Institute of Technology, Kollam
STLAC: A Spatial and Temporal Locality-Aware Cache and Networkon-Chip
STLAC: A Spatial and Temporal Locality-Aware Cache and Networkon-Chip Codesign for Tiled Manycore Systems Mingyu Wang and Zhaolin Li Institute of Microelectronics, Tsinghua University, Beijing 100084,
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
1 ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology Mikkel B. Stensgaard and Jens Sparsø Technical University of Denmark Technical University of Denmark Outline 2 Motivation ReNoC Basic
Fault Tolerant and Secure Architectures for On Chip Networks With Emerging Interconnect Technologies. Mohsin Y Ahmed Conlan Wesson
Fault Tolerant and Secure Architectures for On Chip Networks With Emerging Interconnect Technologies Mohsin Y Ahmed Conlan Wesson Overview NoC: Future generation of many core processor on a single chip
Partitioned Fixed-Priority Scheduling of Parallel Tasks Without Preemptions
Partitioned Fixed-Priority Scheduling of Parallel Tasks Without Preemptions *, Alessandro Biondi *, Geoffrey Nelissen, and Giorgio Buttazzo * * ReTiS Lab, Scuola Superiore Sant Anna, Pisa, Italy CISTER,
Worst Case Analysis of DRAM Latency in Multi-Requestor Systems. Zheng Pei Wu Yogen Krish Rodolfo Pellizzoni
orst Case Analysis of DAM Latency in Multi-equestor Systems Zheng Pei u Yogen Krish odolfo Pellizzoni Multi-equestor Systems CPU CPU CPU Inter-connect DAM DMA I/O 1/26 Multi-equestor Systems CPU CPU CPU
PRIORITY BASED SWITCH ALLOCATOR IN ADAPTIVE PHYSICAL CHANNEL REGULATOR FOR ON CHIP INTERCONNECTS. A Thesis SONALI MAHAPATRA
PRIORITY BASED SWITCH ALLOCATOR IN ADAPTIVE PHYSICAL CHANNEL REGULATOR FOR ON CHIP INTERCONNECTS A Thesis by SONALI MAHAPATRA Submitted to the Office of Graduate and Professional Studies of Texas A&M University
Lecture: Interconnection Networks. Topics: TM wrap-up, routing, deadlock, flow control, virtual channels
Lecture: Interconnection Networks Topics: TM wrap-up, routing, deadlock, flow control, virtual channels 1 TM wrap-up Eager versioning: create a log of old values Handling problematic situations with a
Lecture 3: Flow-Control
High-Performance On-Chip Interconnects for Emerging SoCs http://tusharkrishna.ece.gatech.edu/teaching/nocs_acaces17/ ACACES Summer School 2017 Lecture 3: Flow-Control Tushar Krishna Assistant Professor
Basic Low Level Concepts
Course Outline Basic Low Level Concepts Case Studies Operation through multiple switches: Topologies & Routing v Direct, indirect, regular, irregular Formal models and analysis for deadlock and livelock
NoC Simulation in Heterogeneous Architectures for PGAS Programming Model
NoC Simulation in Heterogeneous Architectures for PGAS Programming Model Sascha Roloff, Andreas Weichslgartner, Frank Hannig, Jürgen Teich University of Erlangen-Nuremberg, Germany Jan Heißwolf Karlsruhe
Abstract. Paper organization
Allocation Approaches for Virtual Channel Flow Control Neeraj Parik, Ozen Deniz, Paul Kim, Zheng Li Department of Electrical Engineering Stanford University, CA Abstract s are one of the major resources
Lecture 7: Flow Control - I
ECE 8823 A / CS 8803 - ICN Interconnection Networks Spring 2017 http://tusharkrishna.ece.gatech.edu/teaching/icn_s17/ Lecture 7: Flow Control - I Tushar Krishna Assistant Professor School of Electrical
MPI Programming Techniques
MPI Programming Techniques Copyright (c) 2012 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any
On-Die Interconnects for next generation CMPs
On-Die Interconnects for next generation CMPs Partha Kundu Corporate Technology Group (MTL) Intel Corporation OCIN Workshop, Stanford University December 6, 2006 1 Multi- Transition Accelerating We notified
Deadlock-free XY-YX router for on-chip interconnection network
LETTER IEICE Electronics Express, Vol.10, No.20, 1 5 Deadlock-free XY-YX router for on-chip interconnection network Yeong Seob Jeong and Seung Eun Lee a) Dept of Electronic Engineering Seoul National Univ
DESIGN A APPLICATION OF NETWORK-ON-CHIP USING 8-PORT ROUTER
G MAHESH BABU, et al, Volume 2, Issue 7, PP:, SEPTEMBER 2014. DESIGN A APPLICATION OF NETWORK-ON-CHIP USING 8-PORT ROUTER G.Mahesh Babu 1*, Prof. Ch.Srinivasa Kumar 2* 1. II. M.Tech (VLSI), Dept of ECE,
CAD System Lab Graduate Institute of Electronics Engineering National Taiwan University Taipei, Taiwan, ROC
QoS Aware BiNoC Architecture Shih-Hsin Lo, Ying-Cherng Lan, Hsin-Hsien Hsien Yeh, Wen-Chung Tsai, Yu-Hen Hu, and Sao-Jie Chen Ying-Cherng Lan CAD System Lab Graduate Institute of Electronics Engineering
CHAPTER 6 FPGA IMPLEMENTATION OF ARBITERS ALGORITHM FOR NETWORK-ON-CHIP
133 CHAPTER 6 FPGA IMPLEMENTATION OF ARBITERS ALGORITHM FOR NETWORK-ON-CHIP 6.1 INTRODUCTION As the era of a billion transistors on a one chip approaches, a lot of Processing Elements (PEs) could be located
Dynamic Packet Fragmentation for Increased Virtual Channel Utilization in On-Chip Routers
Dynamic Packet Fragmentation for Increased Virtual Channel Utilization in On-Chip Routers Young Hoon Kang, Taek-Jun Kwon, and Jeff Draper {youngkan, tjkwon, draper}@isi.edu University of Southern California
Multiprocessor and Real- Time Scheduling. Chapter 10
Multiprocessor and Real- Time Scheduling Chapter 10 Classifications of Multiprocessor Loosely coupled multiprocessor each processor has its own memory and I/O channels Functionally specialized processors
Design of Synchronous NoC Router for System-on-Chip Communication and Implement in FPGA using VHDL
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology ISSN 2320 088X IJCSMC, Vol. 2, Issue.
Lecture 12: Interconnection Networks. Topics: communication latency, centralized and decentralized switches, routing, deadlocks (Appendix E)
Lecture 12: Interconnection Networks Topics: communication latency, centralized and decentralized switches, routing, deadlocks (Appendix E) 1 Topologies Internet topologies are not very regular they grew
POLYMORPHIC ON-CHIP NETWORKS
POLYMORPHIC ON-CHIP NETWORKS Martha Mercaldi Kim, John D. Davis*, Mark Oskin, Todd Austin** University of Washington *Microsoft Research, Silicon Valley ** University of Michigan On-Chip Network Selection
Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in on-chip Networks
Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in on-chip Networks Andreas Lankes¹, Soeren Sonntag², Helmut Reinig³, Thomas Wild¹, Andreas Herkersdorf¹
Ultra-Fast NoC Emulation on a Single FPGA
The 25 th International Conference on Field-Programmable Logic and Applications (FPL 2015) September 3, 2015 Ultra-Fast NoC Emulation on a Single FPGA Thiem Van Chu, Shimpei Sato, and Kenji Kise Tokyo
EECS 570. Lecture 19 Interconnects: Flow Control. Winter 2018 Subhankar Pal
Lecture 19 Interconnects: Flow Control Winter 2018 Subhankar Pal http://www.eecs.umich.edu/courses/eecs570/ Slides developed in part by Profs. Adve, Falsafi, Hill, Lebeck, Martin, Narayanasamy, Nowatzyk,
Lecture 9. Quality of Service in ad hoc wireless networks
Lecture 9 Quality of Service in ad hoc wireless networks Yevgeni Koucheryavy Department of Communications Engineering Tampere University of Technology yk@cs.tut.fi Lectured by Jakub Jakubiak QoS statement
Performance of Multihop Communications Using Logical Topologies on Optical Torus Networks
Performance of Multihop Communications Using Logical Topologies on Optical Torus Networks X. Yuan, R. Melhem and R. Gupta Department of Computer Science University of Pittsburgh Pittsburgh, PA 156 fxyuan,
Interconnection Networks: Topology. Prof. Natalie Enright Jerger
Interconnection Networks: Topology Prof. Natalie Enright Jerger Topology Overview Definition: determines arrangement of channels and nodes in network Analogous to road map Often first step in network design
OPERATING SYSTEMS CS3502 Spring Processor Scheduling. Chapter 5
OPERATING SYSTEMS CS3502 Spring 2018 Processor Scheduling Chapter 5 Goals of Processor Scheduling Scheduling is the sharing of the CPU among the processes in the ready queue The critical activities are:
High Performance Interconnect and NoC Router Design
High Performance Interconnect and NoC Router Design Brinda M M.E Student, Dept. of ECE (VLSI Design) K.Ramakrishnan College of Technology Samayapuram, Trichy 621 112 brinda18th@gmail.com Devipoonguzhali
What s An OS? Cyclic Executive. Interrupts. Advantages Simple implementation Low overhead Very predictable
What s An OS? Provides environment for executing programs Process abstraction for multitasking/concurrency scheduling Hardware abstraction layer (device drivers) File systems Communication Do we need an
Quality of Service (QoS)
Quality of Service (QoS) The Internet was originally designed for best-effort service without guarantee of predictable performance. Best-effort service is often sufficient for a traffic that is not sensitive
SMD149 - Operating Systems
SMD149 - Operating Systems Roland Parviainen November 3, 2005 1 / 45 Outline Overview 2 / 45 Process (tasks) are necessary for concurrency Instance of a program in execution Next invocation of the program
Hybrid On-chip Data Networks. Gilbert Hendry Keren Bergman. Lightwave Research Lab. Columbia University
Hybrid On-chip Data Networks Gilbert Hendry Keren Bergman Lightwave Research Lab Columbia University Chip-Scale Interconnection Networks Chip multi-processors create need for high performance interconnects
Concurrent activities in daily life. Real world exposed programs. Scheduling of programs. Tasks in engine system. Engine system
Real world exposed programs Programs written to interact with the real world, outside the computer Programs handle input and output of data in pace matching the real world processes Necessitates ability
IEEE Time-Sensitive Networking (TSN)
IEEE 802.1 Time-Sensitive Networking (TSN) Norman Finn, IEEE 802.1CB, IEEE 802.1CS Editor Huawei Technologies Co. Ltd norman.finn@mail01.huawei.com Geneva, 27 January, 2018 Before We Start This presentation
Re-Examining Conventional Wisdom for Networks-on-Chip in the Context of FPGAs
This work was funded by NSF. We thank Xilinx for their FPGA and tool donations. We thank Bluespec for their tool donations. Re-Examining Conventional Wisdom for Networks-on-Chip in the Context of FPGAs
On RTL to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design Exploration
On to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design Exploration Sven Alexander Horsinka, Rolf Meyer, Jan Wagner, Rainer Buchty and Mladen Berekovic TU Braunschweig,
Real-Time Internet of Things
Real-Time Internet of Things Chenyang Lu Cyber-Physical Systems Laboratory h7p://www.cse.wustl.edu/~lu/ Internet of Things Ø Convergence of q Miniaturized devices: integrate processor, sensors and radios.
ISSN Vol.03, Issue.02, March-2015, Pages:
ISSN 2322-0929 Vol.03, Issue.02, March-2015, Pages:0122-0126 www.ijvdcs.org Design and Simulation Five Port Router using Verilog HDL CH.KARTHIK 1, R.S.UMA SUSEELA 2 1 PG Scholar, Dept of VLSI, Gokaraju
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture xxx (23) xxx xxx www.elsevier.com/locate/sysarc QNoC: QoS architecture and design process for network on chip Evgeny Bolotin *, Israel Cidon, Ran Ginosar, Avinoam Kolodny
SoC Design. Prof. Dr. Christophe Bobda Institut für Informatik Lehrstuhl für Technische Informatik
SoC Design Prof. Dr. Christophe Bobda Institut für Informatik Lehrstuhl für Technische Informatik Chapter 5 On-Chip Communication Outline 1. Introduction 2. Shared media 3. Switched media 4. Network on
Real-Time Protocol (RTP)
Real-Time Protocol (RTP) Provides standard packet format for real-time application Typically runs over UDP Specifies header fields below Payload Type: 7 bits, providing 128 possible different types of
Prediction Router: Yet another low-latency on-chip router architecture
Prediction Router: Yet another low-latency on-chip router architecture Hiroki Matsutani Michihiro Koibuchi Hideharu Amano Tsutomu Yoshinaga (Keio Univ., Japan) (NII, Japan) (Keio Univ., Japan) (UEC, Japan)
Networks-on-Chip Router: Configuration and Implementation
Networks-on-Chip : Configuration and Implementation Wen-Chung Tsai, Kuo-Chih Chu * 2 1 Department of Information and Communication Engineering, Chaoyang University of Technology, Taichung 413, Taiwan,
A Simplified Executable Model to Evaluate Latency and Throughput of Networks-on-Chip
A Simplified Executable Model to Evaluate Latency and Throughput of Networks-on-Chip Leandro Möller Luciano Ost, Leandro Soares Indrusiak Sanna Määttä Fernando G. Moraes Manfred Glesner Jari Nurmi {ost,
CSE 123: Computer Networks Alex C. Snoeren. HW 2 due Thursday 10/21!
CSE 123: Computer Networks Alex C. Snoeren HW 2 due Thursday 10/21! Finishing up media access Contention-free methods (rings) Moving beyond one wire Link technologies have limits on physical distance Also
CS 153 Design of Operating Systems Winter 2016
CS 153 Design of Operating Systems Winter 2016 Lecture 12: Scheduling & Deadlock Priority Scheduling Priority Scheduling Choose next job based on priority» Airline checkin for first class passengers Can
4. Networks. in parallel computers. Advances in Computer Architecture
4. Networks in parallel computers Advances in Computer Architecture System architectures for parallel computers Control organization Single Instruction stream Multiple Data stream (SIMD) All processors
CPU Scheduling. The scheduling problem: When do we make decision? - Have K jobs ready to run - Have N 1 CPUs - Which jobs to assign to which CPU(s)
1/32 CPU Scheduling The scheduling problem: - Have K jobs ready to run - Have N 1 CPUs - Which jobs to assign to which CPU(s) When do we make decision? 2/32 CPU Scheduling Scheduling decisions may take