Future Gigascale MCSoCs Applications: Computation & Communication Orthogonalization

Transcription

1 Basic Network-on-Chip (BANC) interconnection for Future Gigascale MCSoCs Applications: Computation & Communication Orthogonalization Abderazek Ben Abdallah, Masahiro Sowa Graduate School of Information Systems DPL Laboratory The Univ. of Electro-communications Tokyo, Japan 1

2 MCSoCs introduction Deep sub-micron technologies enable the implementation of single chip integrating: processors Dedicated hardware components (cores) Multiple software programmable p Multicore are emerging as key sol lution for today s nanoelectronics problems MCSoCs are driven by: Wireless communication, distribut applications, etc. ted/broadband computing, Multimedia ITRSC predicted that an IC will have billion of transistors by

3 Global on-chip communication delay Moore s law provides exponential growth of resources Design does not become easier Deep submicron problems Wire vs. transistor speed, power, signal integrity Design productivity gap IP re-use, platforms Verification technologies 3

4 MCSoC Computation view: the rest of the story! sys_performance = f(com_type_performance, compiler_performance, comp_performance (1) com_type_performance = f(machine dependence, code_dependence) (2) code_dependence = f(application_t type, (3) underlying_hw_performance, RTOS_performance) + QoC, optimizations_effort) QoC = f(inst_generation_scheme, optimization_type) (4) our new approach: Improves the QoC > SW view No aggressive hardware techniques > HW view 4

5 The QueueCore processor * * * [abderazek06] B. A. Abderazek, T. Toshinaga, M. Sowa : ICPP 2006, Columbus, USA, August

6 Wire based communication problems They are unstructured and have parasitic capacitance and crosstalk to adjacent wires: Difficult to predict them early in the design process May differ significantly from one run of the router to the next. Solution: Full-swing static CMOS gates (or inverters) are employed The problem of the solution: High delay and high power dissipation [Lee2006] Long wires require repeaters at periodic intervals to keep their delay linear. Properly placing these repeaters is difficult and places additional constraints More complex with each successivee technology scaling Average wire on a typical chip is used less than 10% of the time [Dally2000] 6

7 The packet based communication approach (1) Resources (cores) use packets (not dedicated wires) to communicate to each other Each resource is placed in a square tile on the chip The clients communicate with each other via the network. 7

8 The packet based communication approach (2) Organization (structure) Wires electrical properties are optimized and well controlled. Low and predictable cross-talk, Reduce power dissipation Performance Sharing: When one client is idle, other clients continue to make use of the network resources. Modularity Defining a standard interface is much the same manner as a backplane bus.. 8

9 NoCs challenges On-chip networks design is different from conventional inter-chip design. Wires and pins are more abundant than in inter-chip networks Buffers space is less abundant (this talk focuses on this point only) What topologies are best to the huge wiring resources available on chip? What flow control schemes reduce buffer size and routing overhead? 9

10 Communication performance issues in NoC Communication Performance involves: Topology: How cores (nodes) and switches are interconnected Routing : How to determines the route from source to destination Switching strategy: How a message traverses the route Circuit, packet, store and forward, wormhole switching? Flow control: Schedules ( resource allocation) the traversal of the message. 10

11 BANC layers Application layer: application-to-application Session layer: process-to-process Network layer: resource-to-resource Data link layer: switch-to-switch and switch-to-resource Physical layer: switch-to-switch and switch-to-resource 11

12 Low level Higher level number of bits per link (channel dimension) number of links no pipelining data link packet = Physical packet data link clock = Physical clock single packet input buffer no error correction network layer packet = link layer packet XY address routing input Buffer 12

13 Stack layers and the switch in BANC 13

14 Interconnection of a tile in BANC The Network Layer is implemented by the network interface (NI) The adapter is needed to connect the core (resource) to the network 14

15 Packet format in BANC 15

16 BANC switch basic interconnection 16

17 BANC features Here, we want to analyze the buffer size design only. We described the BANC in TCL and used ns-2 from Berkley BANC Features: 5x5 mesh grid (50 components) Duplex connection link (simultaneous transfer in both ways) Adjustable delay and bandwidth A FIFO at each input port Droptail scheme for buffer overflow RNG is used to select X and Y coordinate randomly 17

18 Effect of buffer size on drop probability 1. The packet drop probability decreases when the buffer size increases. 2. For higher traffic rates (>=120Mb/s), it is not significant that the drop probability decreases with the buffer size increase 18

19 Effect of communication load and drop probability 1. The drop probability increases as the communication load increases over communication load. 2. Increasing buffer size cannot provide significant compensation to the increasing of drop probability. 3. The drop probability is more sensitive to the communication load that the buffer size. 19

20 Packet delay and communication load over buffer sizes 1. The packet delay is < 1 ms when communication load equals Buffer is little utilized when the communication load is low. 2. Packet delay is not sensitive to the communication load when there are some packets dropped. 20

21 Concluding remarks I. QueueCore is a good candidate for NoC resources II. III. BANC architecture Buffer For < ½ load, the drop probability is almost zero for buffer size of 8 packets in each switch The delay in Queue is an important part for delay in message Delay in message is more sensitive to buffer size than communication load The drop probability is more sensitive to the communication load than to buffer size. 21

22 Thank you. Questions? 22