FPX Architecture for a Dynamically Extensible Router
|
|
- Alexis Riley
- 6 years ago
- Views:
Transcription
1 FPX Architecture for a Dynamically Extensible Router Alex Chandra, Yuhua Chen, John Lockwood, Sarang Dharmapurikar, Wenjing Tang, David Taylor, Jon Turner
2 Dynamically Extensible Router Control Processor Field Programmable Port Ext. Switch Fabric FPX FPX FPX FPX SDRAM 128 FPX MB FPX Field Programmable Port Extenders Line Card Line Card Line Card Line Card Reprogrammable Application Device Line Card SRAM 4 MB Network Interface Device Line Card 2 - Jonathan Turner - 6/19/2002
3 Special Packet Processing Control Processor Switch Fabric FPX FPX FPX FPX Smart Port Card MB Sys. FPGA FPX FPX North Bridge APIC Line Card Line Card Line Card Pentium Line Card Line Card Line Card Cache Jonathan Turner - 6/19/2002
4 Logical Port Architecture reassembly contexts FPX Packet Classification & Route Lookup active flow queues virtual output queues DQ Output Side Processing Packet Classification output queues RC PCU reassembly contexts FPX active flow queues plugins Input Side Processing PCU plugins 4 - Jonathan Turner - 6/19/2002
5 RAD Block Diagram SDRAM SDRAM from LC from SW Data Path Header Pointer ISAR Packet Storage Manager (includes free space list) Discard OSAR Pointer to LC to SW Header Proc. Classification and Route Lookup Queue Manager Control SRAM Register Set SRAM Route & Filter Updates Register Set Updates & Status DQ Status & Rate Control Control Cell Processor 5 - Jonathan Turner - 6/19/2002
6 Physical Configuration from LC to LC NID from SW to SW ISAR SDRAM Packet Storage Manager 1 Classification and Route Lookup Route & Filter Updates OSAR Register Set Updates & Status Discard Queue Manager DQ Status & Rate Control Packet Storage Manager 2 SDRAM Control Cell Processor SRAM SRAM 6 - Jonathan Turner - 6/19/2002
7 Classification and Route Lookup (CARL)! Three lookup engines.» route lookup for routing datagrams - best prefix» flow filters for multicast & reserved flows - exact» general filters (32) for management - exhaustive! Input processing.» parallel check of all three» return highest priority exclusive and highest priority non-exclusive» general filters have unique priority» all flow filters share single priority» ditto for routes 7 - Jonathan Turner - 6/19/2002 Input Demux Route Lookup Flow Filters General Filters headers bypass Result Proc. & Priority Resolution! Output processing.» exact match only! Route lookup & flow filters share off-chip SRAM! General filters processed on-chip
8 8 - Jonathan Turner - 6/19/2002 Exact Match Lookup! Exact match lookup table used for reserved flows.» includes LFS, signaled QOS flows and multicast» and, flows requiring processing by s» each of these flows has separate queue in QM» multicast flows have two queues (recycling multicast)» implemented using hashing packet src dst 6 5 simple hash on-chip SRAM tag+data tag+data tag+data -- tag+data ingress valid egress valid off-chip SRAM tag=[src,dst,sport, dport,proto] data includes 2 outputs+2 QIDs LFS rates packet,byte counters flags separate memory areas for ingress and egress packets
9 9 - Jonathan Turner - 6/19/2002 General Filter Match! General filter match considers full 5-tuple» prefix match on source and destination addresses» range match on source and destination ports» exact or wildcard match on protocol» each filter has a priority and may be exclusive or nonexclusive! Intended primarily for management filters.» firewall filters» class-based monitoring» class-based special processing! Implemented using parallel exhaustive search. filter memory matcher matcher matcher» limit of 32 filters matcher
10 Fast IP Lookup (Eatherton & Dittia) 01, address: , * * 0, , internal bit vector external bit vector! Multibit trie with clever data encoding.» small memory requirements (4-6 bytes per prefix typical)» small memory bandwidth, simple lookup yields fast lookup rates» updates have negligible impact on lookup performance! Avoid impact of external memory latency on throughput by interleaving several concurrent lookups.» 8 lookup engine config. uses about 6% of Virtex 2000E logic cells 10 - Jonathan Turner - 6/19/
11 Lookup Throughput & Latency Millions of lookups per second Worst-Case Avg. Lookup Latency Mae West Avg. Lookup Latency Mae West Througput Worst-Case Throughput linear throughput gain negligible latency increase Average Lookup Latency (ns) # of FIPL engines 11 - Jonathan Turner - 6/19/2002
12 Update Performance Millions of lookups per second reasonable update rates have little impact No updates 10K updates/sec 100K updates/sec 1 update every 10 µs # of FIPL engines 12 - Jonathan Turner - 6/19/2002
13 Queue Manager Logical View (QM) separate queues for each reserved flow to link link pkt. sched. res. flow queues datagram queues 64 hashed datagram queues for traffic isolation arriving packets pkt. sched. to from to output 0 res. flow queues VOQ pkt. sched. datagram queue to output 1 to output 8 separate queue for each flow DQ to switch separate queue set for each output Jonathan Turner - 6/19/2002
14 Distributed Queueing periodic queue length reports Control Processor Switch Fabric I O I O I O I O I O I O queue per output Sched. Sched. Sched. Sched. Sched. Sched. Routing Scheduler paces each queue Routing according Routing to backlog share Routing Routing Routing TI TI TI TI TI TI 14 - Jonathan Turner - 6/19/2002
15 Basic Distributed Queueing Algorithm! Goal: avoid switch congestion and output queue underflow.! Let B(i,j) be backlog at input i for output j, B(j) be backlog at output j.! Can avoid output-side switch congestion if rate(i,j) hi(i,j) = L j S B(i,j)/B(+,j)» where L j is external link rate at output j and S is switch speedup! Can avoid underflow at output j if rate(i,j) lo(i,j) = L j B(i,j)/(B(j) + B(+,j))» this can be achieved if lo(i,+) L i S for all i! Can avoid input-side switch congestion if rate(i,j) hi (i,j) = L i S lo(i,j)/lo(i,+)! Let rate(i,j) = min{ hi(i,j), hi (i,j) }.! Algorithm avoids congestion and for large enough S, avoids underflow.» what is the smallest value of S for which underflow cannot occur? 15 - Jonathan Turner - 6/19/2002
16 Stress Test can vary number of inputs and outputs used, and length of phases 16 - Jonathan Turner - 6/19/2002
17 Stress Test Simulation - Min Rates min rate sums speedup=1.5 critical rate +lo(1,5) +lo(1,4) +lo(1,3) lo(1,1) +lo(1,2) second first phase 0 1,000 2,000 3,000 4,000 5,000 6,000 7,000 8,000 time 17 - Jonathan Turner - 6/19/2002
18 allocated rate sums Stress Test - Actual Rates speedup=1.5 critical rate rate(1,1) first phase +rate(1,2) 0 1,000 2,000 3,000 4,000 5,000 6,000 7,000 8,000 time Under-use of input bandwidth +rate(1,3) second +rate(1,4) +rate(1,5) 18 - Jonathan Turner - 6/19/2002
19 Stress Test - Input Queue Lengths input queue lengths 1,000 speedup= input side 800 backlog for final output implies 700 underflow B(1,1) B(1,2) B(1,3) B(1,4) B(1,5) 0 1,000 2,000 3,000 4,000 5,000 6,000 7,000 8,000 time 19 - Jonathan Turner - 6/19/2002
20 Stress Test - Output Queue Lengths output queue length 2,500 speedup=1.5 2,250 persistent output 2,000 side backlog caused by earlier dip in 1,750 forwarding rate 1,500 1,250 B(1) 1, B(2) B(4) 250 B(3) B(5) 0 0 1,000 2,000 3,000 4,000 5,000 6,000 7,000 8,000 time 20 - Jonathan Turner - 6/19/2002
21 21 - Jonathan Turner - 6/19/2002 Resource Usage Estimates! Key resources in Xilinx FPGAs» flip flops - 38,400» lookup tables (LUTs) - 38,400 n each can implement any 4 input Boolean function» block RAMs (4 Kbits each) Number % of total flops LUTs RAMs flops LUTs RAMs CARL 2,217 4, % 12.2% 20.0% CCP 1,156 1, % 4.2% 1.9% FIFOs % 0.7% 6.3% ISAR 4,000 5, % 14.1% 17.5% OSAR 2,000 3, % 7.8% 15.0% PSM (both) 4,722 4, % 10.8% 12.5% QM version 1,2 13,258 12, % 31.5% 16.9% Total 27,486 31, % 81.3% 90.0% Resource Count 38,400 38, % Usage 72% 81% 90%
22 Comparison of available FPGAs on FPXs XCV2000e-6 Signal Delay (ns) XCV1000e-7 5 flops in opposite corners flops in adjacent cells/clbs LUTs in Datapath (FFs in corners) 22 - Jonathan Turner - 6/19/2002
23 Summary! Single XCV2000 FPGA can do IP packet processing for gigabit link.» would be simple if just did route lookup and fifo queues» using SDRAMs effectively is hard n significant overheads - dependent on sequences of operations» packet classification & general queueing adds complexity n intelligent packet discarding greatly expands required memory bandwidth» achieving wire-speed operation under worst-case conditions is challenging! Expect to complete first version this fall.! Complete version by middle of Jonathan Turner - 6/19/2002
Users Guide: Fast IP Lookup (FIPL) in the FPX
Users Guide: Fast IP Lookup (FIPL) in the FPX Gigabit Kits Workshop /22 FIPL System Design Each FIPL Engine performs a longest matching prefix lookup on a single 32-bit IPv4 destination address FIPL Engine
More informationWUCS-TM-02-?? September 13, 2002
Field-programmable Port extender (FPX) Support for the Multi-Service Router (MSR) Version 1.0 David E. Taylor, Sarang Dharmapurikar, John W. Lockwood, Jonathan S. Turner, Yuhua Chen, Alex Chandra, Wen-Jing
More informationWUCS-TM-02-?? September 23, 2005
Field-programmable Port extender (FPX) Support for the Network Services Platform (NSP) Version 1.0 Alex Chandra, Yuhua Chen, John DeHart, Sarang Dharmapurikar, Fred Kuhns, John W. Lockwood, Wen-Jing Tang,
More informationUsing the Open Network Lab
Using the Open Network Lab Jon Turner Applied Research Laboratory Computer Science and Engineering Department http://www.arl.wustl.edu/arl 2 - Jonathan Turner 1/31/2006 Motivation What is ONL?» remotely
More informationField-programmable Port Extender (FPX) August 2001 Workshop. John Lockwood, Assistant Professor
Field-programmable Port Extender (FPX) August 2001 Workshop John Lockwood, Lockwood@arl.wustl.edu Assistant Professor Washington University Department of Computer Science Applied Research Lab 1 Brookings
More informationDesign and Evaluation of a High-Performance Dynamically Extensible Router
Design and Evaluation of a High-Performance Dynamically Extensible Router Fred Kuhns, John DeHart, Anshul Kantawala, Ralph Keller, John Lockwood, Prashanth Pappu, David Richard, David Taylor, Jyoti Parwatikar,
More informationDesign of a High Performance Dynamically Extensible Router
Design of a High Performance Dynamically Extensible Router Fred Kuhns, John DeHart, Anshul Kantawala, Ralph Keller, John Lockwood, Prashanth Pappu, David Richards, David Taylor, Jyoti Parwatikar, Ed Spitznagel,
More informationDemonstration of a High Performance Active Router DARPA Demo - 9/24/99
Demonstration of a High Performance Active Router DARPA Demo - 9/24/99 Dan Decasper, John DeHart, Ralph Keller, Jonathan Turner, Sumi Choi and Tilman Wolf University, Applied Research Lab http://www.arl.wustl.edu/arl/
More informationPARALLEL ALGORITHMS FOR IP SWITCHERS/ROUTERS
THE UNIVERSITY OF NAIROBI DEPARTMENT OF ELECTRICAL AND INFORMATION ENGINEERING FINAL YEAR PROJECT. PROJECT NO. 60 PARALLEL ALGORITHMS FOR IP SWITCHERS/ROUTERS OMARI JAPHETH N. F17/2157/2004 SUPERVISOR:
More informationTopics for Today. Network Layer. Readings. Introduction Addressing Address Resolution. Sections 5.1,
Topics for Today Network Layer Introduction Addressing Address Resolution Readings Sections 5.1, 5.6.1-5.6.2 1 Network Layer: Introduction A network-wide concern! Transport layer Between two end hosts
More informationDecision Forest: A Scalable Architecture for Flexible Flow Matching on FPGA
Decision Forest: A Scalable Architecture for Flexible Flow Matching on FPGA Weirong Jiang, Viktor K. Prasanna University of Southern California Norio Yamagaki NEC Corporation September 1, 2010 Outline
More informationEfficient Packet Classification for Network Intrusion Detection using FPGA
Efficient Packet Classification for Network Intrusion Detection using FPGA ABSTRACT Haoyu Song Department of CSE Washington University St. Louis, USA hs@arl.wustl.edu FPGA technology has become widely
More informationEECS 122: Introduction to Computer Networks Switch and Router Architectures. Today s Lecture
EECS : Introduction to Computer Networks Switch and Router Architectures Computer Science Division Department of Electrical Engineering and Computer Sciences University of California, Berkeley Berkeley,
More informationGeneric Architecture. EECS 122: Introduction to Computer Networks Switch and Router Architectures. Shared Memory (1 st Generation) Today s Lecture
Generic Architecture EECS : Introduction to Computer Networks Switch and Router Architectures Computer Science Division Department of Electrical Engineering and Computer Sciences University of California,
More informationThe Network Layer and Routers
The Network Layer and Routers Daniel Zappala CS 460 Computer Networking Brigham Young University 2/18 Network Layer deliver packets from sending host to receiving host must be on every host, router in
More informationFirst Gigabit Kits Workshop
First Gigabit Kits Workshop July 12-13, 1999 Jonathan Turner Washington University Computer Science Department http://www.arl.wustl.edu/gigabitkits/kits.html Jonathan Turner 11/8/99 1 Agenda Monday, July
More informationProtocol Wrappers for Layered Network Packet Processing in Reconfigurable Hardware
Protocol Wrappers for Layered Network Packet Processing in Reconfigurable Hardware Florian Braun John Lockwood Marcel Waldvogel University of Stuttgart Washington University in St. Louis IBM Zurich Research
More informationScheduling Data Flows using DRR
CS/CoE 535 Acceleration of Networking Algorithms in Reconfigurable Hardware Prof. Lockwood : Fall 2001 http://www.arl.wustl.edu/~lockwood/class/cs535/ Scheduling Data Flows using DRR http://www.ccrc.wustl.edu/~praveen
More informationTCP-Splitter: Design, Implementation and Operation
Washington University in St. Louis Washington University Open Scholarship All Computer Science and Engineering Research Computer Science and Engineering Report Number: WUCSE-2003-14 2003-03-18 TCP-Splitter:
More informationRouters Technologies & Evolution for High-Speed Networks
Routers Technologies & Evolution for High-Speed Networks C. Pham Université de Pau et des Pays de l Adour http://www.univ-pau.fr/~cpham Congduc.Pham@univ-pau.fr Router Evolution slides from Nick McKeown,
More informationPacket Switch Architectures Part 2
Packet Switch Architectures Part Adopted from: Sigcomm 99 Tutorial, by Nick McKeown and Balaji Prabhakar, Stanford University Slides used with permission from authors. 999-000. All rights reserved by authors.
More informationRouter Architectures
Router Architectures Venkat Padmanabhan Microsoft Research 13 April 2001 Venkat Padmanabhan 1 Outline Router architecture overview 50 Gbps multi-gigabit router (Partridge et al.) Technology trends Venkat
More informationMulti-gigabit Switching and Routing
Multi-gigabit Switching and Routing Gignet 97 Europe: June 12, 1997. Nick McKeown Assistant Professor of Electrical Engineering and Computer Science nickm@ee.stanford.edu http://ee.stanford.edu/~nickm
More informationSwitch and Router Design. Packet Processing Examples. Packet Processing Examples. Packet Processing Rate 12/14/2011
// Bottlenecks Memory, memory, 88 - Switch and Router Design Dr. David Hay Ross 8b dhay@cs.huji.ac.il Source: Nick Mckeown, Isaac Keslassy Packet Processing Examples Address Lookup (IP/Ethernet) Where
More informationMaster Course Computer Networks IN2097
Chair for Network Architectures and Services Prof. Carle Department for Computer Science TU München Chair for Network Architectures and Services Prof. Carle Department for Computer Science TU München Master
More informationLast Lecture: Network Layer
Last Lecture: Network Layer 1. Design goals and issues 2. Basic Routing Algorithms & Protocols 3. Addressing, Fragmentation and reassembly 4. Internet Routing Protocols and Inter-networking 5. Router design
More informationNetFPGA Hardware Architecture
NetFPGA Hardware Architecture Jeffrey Shafer Some slides adapted from Stanford NetFPGA tutorials NetFPGA http://netfpga.org 2 NetFPGA Components Virtex-II Pro 5 FPGA 53,136 logic cells 4,176 Kbit block
More informationDesign of a Weighted Fair Queueing Cell Scheduler for ATM Networks
Design of a Weighted Fair Queueing Cell Scheduler for ATM Networks Yuhua Chen Jonathan S. Turner Department of Electrical Engineering Department of Computer Science Washington University Washington University
More informationMULTI-PLANE MULTI-STAGE BUFFERED SWITCH
CHAPTER 13 MULTI-PLANE MULTI-STAGE BUFFERED SWITCH To keep pace with Internet traffic growth, researchers have been continually exploring new switch architectures with new electronic and optical device
More informationHWP2 Application level query routing HWP1 Each peer knows about every other beacon B1 B3
HWP2 Application level query routing HWP1 Each peer knows about every other beacon B2 B1 B3 B4 B5 B6 11-Feb-02 Computer Networks 1 HWP2 Query routing searchget(searchkey, hopcount) Rget(host, port, key)
More informationThe Network Processor Revolution
The Network Processor Revolution Fast Pattern Matching and Routing at OC-48 David Kramer Senior Design/Architect Market Segments Optical Mux Optical Core DWDM Ring OC 192 to OC 768 Optical Mux Carrier
More informationCisco Series Internet Router Architecture: Packet Switching
Cisco 12000 Series Internet Router Architecture: Packet Switching Document ID: 47320 Contents Introduction Prerequisites Requirements Components Used Conventions Background Information Packet Switching:
More informationNetwork Processors. Nevin Heintze Agere Systems
Network Processors Nevin Heintze Agere Systems Network Processors What are the packaging challenges for NPs? Caveat: I know very little about packaging. Network Processors What are the packaging challenges
More informationHomework 1 Solutions:
Homework 1 Solutions: If we expand the square in the statistic, we get three terms that have to be summed for each i: (ExpectedFrequency[i]), (2ObservedFrequency[i]) and (ObservedFrequency[i])2 / Expected
More informationInternet Worm and Virus Protection for Very High-Speed Networks
Internet Worm and Virus Protection for Very High-Speed Networks John W. Lockwood Professor of Computer Science and Engineering lockwood@arl.wustl.edu http://www.arl.wustl.edu/~lockwood Research Sponsor:
More informationImplementation of an Open Multi-Service Router
Implementation of an Open Multi-Service Router Fred Kuhns, John DeHart, Ralph Keller, John Lockwood, Prashanth Pappu, Jyoti Parwatikar, Ed Spitznagel, David Richards, David Taylor, Jon Turner and Ken Wong
More informationMaster Course Computer Networks IN2097
Chair for Network Architectures and Services Prof. Carle Department for Computer Science TU München Master Course Computer Networks IN2097 Prof. Dr.-Ing. Georg Carle Christian Grothoff, Ph.D. Chair for
More informationP51: High Performance Networking
P51: High Performance Networking Lecture 6: Programmable network devices Dr Noa Zilberman noa.zilberman@cl.cam.ac.uk Lent 2017/18 High Throughput Interfaces Performance Limitations So far we discussed
More informationEE 122: Router Design
Routers EE 22: Router Design Kevin Lai September 25, 2002.. A router consists - A set of input interfaces at which packets arrive - A set of output interfaces from which packets depart - Some form of interconnect
More informationLecture 16: Router Design
Lecture 16: Router Design CSE 123: Computer Networks Alex C. Snoeren Eample courtesy Mike Freedman Lecture 16 Overview End-to-end lookup and forwarding example Router internals Buffering Scheduling 2 Example:
More informationConfiguration Commands. Generic Commands. description XRS Quality of Service Guide Page 125
Configuration Commands Generic Commands description Syntax description description-string no description Context config>qos>shared-queue config>qos>network-queue config>qos>network config>qos>network>ingress>ipv6-criteria>entry
More informationCisco IOS Switching Paths Overview
This chapter describes switching paths that can be configured on Cisco IOS devices. It contains the following sections: Basic Router Platform Architecture and Processes Basic Switching Paths Features That
More informationDesign, Simulation and FPGA Implementation of a Novel Router for Bulk Flow TCP in Optical IP Networks
Design, Simulation and FPGA Implementation a Novel Router for Bulk Flow TCP in Optical IP Networks V. Parthasarathy, P. Anandakumar, V. Rajamani Abstract - Architecture a novel optical router is designed
More informationIP Address Lookup and Packet Classification Algorithms
IP Address Lookup and Packet Classification Algorithms Zhen Xu, Jeff Nie, Xuehong Sun, and Yiqiang Q. Zhao School of Mathematics and Statistics, Carleton University Outline 1. Background 2. Two IP Address
More informationSample Routers and Switches. High Capacity Router Cisco CRS-1 up to 46 Tb/s thruput. Routers in a Network. Router Design
outer Design outers in a Network Overview of Generic outer Architecture Input-d Switches (outers) IP Look-up Algorithms Packet Classification Algorithms Sample outers and Switches Cisco 46 outer up to
More informationTowards High-performance Flow-level level Packet Processing on Multi-core Network Processors
Towards High-performance Flow-level level Packet Processing on Multi-core Network Processors Yaxuan Qi (presenter), Bo Xu, Fei He, Baohua Yang, Jianming Yu and Jun Li ANCS 2007, Orlando, USA Outline Introduction
More informationNetwork Interface Architecture and Prototyping for Chip and Cluster Multiprocessors
University of Crete School of Sciences & Engineering Computer Science Department Master Thesis by Michael Papamichael Network Interface Architecture and Prototyping for Chip and Cluster Multiprocessors
More informationDesign and Implementation of a Shared Memory Switch Fabric
6'th International Symposium on Telecommunications (IST'2012) Design and Implementation of a Shared Memory Switch Fabric Mina Ejlali M.ejlalikamorin@ec.iut.ac.ir Mohammad Ali Montazeri Montazeri@cc.iut.ac.ir
More informationTraditional network management methods have typically
Advanced Configuration for the Dell PowerConnect 5316M Blade Server Chassis Switch By Surendra Bhat Saurabh Mallik Enterprises can take advantage of advanced configuration options for the Dell PowerConnect
More informationCS 5114 Network Programming Languages Data Plane. Nate Foster Cornell University Spring 2013
CS 5114 Network Programming Languages Data Plane http://www.flickr.com/photos/rofi/2097239111/ Nate Foster Cornell University Spring 2013 Based on lecture notes by Jennifer Rexford and Michael Freedman
More informationFrugal IP Lookup Based on a Parallel Search
Frugal IP Lookup Based on a Parallel Search Zoran Čiča and Aleksandra Smiljanić School of Electrical Engineering, Belgrade University, Serbia Email: cicasyl@etf.rs, aleksandra@etf.rs Abstract Lookup function
More informationPerformance Evaluation of Myrinet-based Network Router
Performance Evaluation of Myrinet-based Network Router Information and Communications University 2001. 1. 16 Chansu Yu, Younghee Lee, Ben Lee Contents Suez : Cluster-based Router Suez Implementation Implementation
More informationCSCI-1680 Link Layer Wrap-Up Rodrigo Fonseca
CSCI-1680 Link Layer Wrap-Up Rodrigo Fonseca Based partly on lecture notes by David Mazières, Phil Levis, John Jannotti Today: Link Layer (cont.) Framing Reliability Error correction Sliding window Medium
More informationRouter Design: Table Lookups and Packet Scheduling EECS 122: Lecture 13
Router Design: Table Lookups and Packet Scheduling EECS 122: Lecture 13 Department of Electrical Engineering and Computer Sciences University of California Berkeley Review: Switch Architectures Input Queued
More informationOverview. Implementing Gigabit Routers with NetFPGA. Basic Architectural Components of an IP Router. Per-packet processing in an IP Router
Overview Implementing Gigabit Routers with NetFPGA Prof. Sasu Tarkoma The NetFPGA is a low-cost platform for teaching networking hardware and router design, and a tool for networking researchers. The NetFPGA
More informationLecture 16: Network Layer Overview, Internet Protocol
Lecture 16: Network Layer Overview, Internet Protocol COMP 332, Spring 2018 Victoria Manfredi Acknowledgements: materials adapted from Computer Networking: A Top Down Approach 7 th edition: 1996-2016,
More informationLecture 3: Packet Forwarding
Lecture 3: Packet Forwarding CSE 222A: Computer Communication Networks Alex C. Snoeren Thanks: Mike Freedman & Amin Vahdat Lecture 3 Overview Paper reviews Packet Forwarding IP Addressing Subnetting/CIDR
More informationHardware Assisted Recursive Packet Classification Module for IPv6 etworks ABSTRACT
Hardware Assisted Recursive Packet Classification Module for IPv6 etworks Shivvasangari Subramani [shivva1@umbc.edu] Department of Computer Science and Electrical Engineering University of Maryland Baltimore
More informationThe Washington University Smart Port Card
The Washington University Smart Port Card John DeHart Washington University jdd@arl.wustl.edu http://www.arl.wustl.edu/~jdd 1 SPC Personnel Dave Richard - Overall Hardware Design Dave Taylor - System FPGA
More informationIntroduction to Routers and LAN Switches
Introduction to Routers and LAN Switches Session 3048_05_2001_c1 2001, Cisco Systems, Inc. All rights reserved. 3 Prerequisites OSI Model Networking Fundamentals 3048_05_2001_c1 2001, Cisco Systems, Inc.
More informationA Framework for Rule Processing in Reconfigurable Network Systems
A Framework for Rule Processing in Reconfigurable Network Systems Michael Attig and John Lockwood Washington University in Saint Louis Applied Research Laboratory Department of Computer Science and Engineering
More informationHash-Based String Matching Algorithm For Network Intrusion Prevention systems (NIPS)
Hash-Based String Matching Algorithm For Network Intrusion Prevention systems (NIPS) VINOD. O & B. M. SAGAR ISE Department, R.V.College of Engineering, Bangalore-560059, INDIA Email Id :vinod.goutham@gmail.com,sagar.bm@gmail.com
More informationQueuing Disciplines. Order of Packet Transmission and Dropping. Laboratory. Objective. Overview
Laboratory 2 Queuing Disciplines Order of Packet Transmission and Dropping Objective The objective of this lab is to examine the effect of different queuing disciplines on packet delivery and delay for
More informationNetwork layer (addendum) Slides adapted from material by Nick McKeown and Kevin Lai
Network layer (addendum) Slides adapted from material by Nick McKeown and Kevin Lai Routers.. A router consists - A set of input interfaces at which packets arrive - A set of output interfaces from which
More informationCOMP211 Chapter 4 Network Layer: The Data Plane
COMP211 Chapter 4 Network Layer: The Data Plane All material copyright 1996-2016 J.F Kurose and K.W. Ross, All Rights Reserved Computer Networking: A Top Down Approach 7 th edition Jim Kurose, Keith Ross
More informationUrgency Based Scheduler Scalability - How many Queues?!
Urgency Based Scheduler Scalability - How many Queues?! Johannes Specht johannes.specht AT uni-due.de Univ. of Duisburg-Essen Soheil Samii soheil.samii AT gm.com General Motors 22.05.2015 IEEE 802.1 Time
More informationA Scalable, Cache-Based Queue Management Subsystem for Network Processors
A Scalable, Cache-Based Queue Management Subsystem for Network Processors Sailesh Kumar and Patrick Crowley Applied Research Laboratory Department of Computer Science and Engineering Washington University
More informationArista EOS Central Drop Counters
Arista EOS Central Drop Counters eos.arista.com /eos-4-15-3f/drop-counters/ With this feature, user can fetch various internal hardware info from each switch and isolate the switch or fabric card or SerDes
More informationEECS150 - Digital Design Lecture 17 Memory 2
EECS150 - Digital Design Lecture 17 Memory 2 October 22, 2002 John Wawrzynek Fall 2002 EECS150 Lec17-mem2 Page 1 SDRAM Recap General Characteristics Optimized for high density and therefore low cost/bit
More informationCSCI Computer Networks
CSCI-1680 - Computer Networks Link Layer III: LAN & Switching Chen Avin Based partly on lecture notes by David Mazières, Phil Levis, John Jannotti, Peterson & Davie, Rodrigo Fonseca Today: Link Layer (cont.)
More informationRouting, Routers, Switching Fabrics
Routing, Routers, Switching Fabrics Outline Link state routing Link weights Router Design / Switching Fabrics CS 640 1 Link State Routing Summary One of the oldest algorithm for routing Finds SP by developing
More informationImproving QOS in IP Networks. Principles for QOS Guarantees
Improving QOS in IP Networks Thus far: making the best of best effort Future: next generation Internet with QoS guarantees RSVP: signaling for resource reservations Differentiated Services: differential
More informationThis document provides an overview of buffer tuning based on current platforms, and gives general information about the show buffers command.
Contents Introduction Prerequisites Requirements Components Used Conventions General Overview Low-End Platforms (Cisco 1600, 2500, and 4000 Series Routers) High-End Platforms (Route Processors, Switch
More informationHigh-Speed Network Processors. EZchip Presentation - 1
High-Speed Network Processors EZchip Presentation - 1 NP-1c Interfaces Switch Fabric 10GE / N x1ge or Switch Fabric or Lookup Tables Counters SDRAM/FCRAM 64 x166/175mhz SRAM DDR NBT CSIX c XGMII HiGig
More informationChapter 4 Network Layer: The Data Plane
Chapter 4 Network Layer: The Data Plane Chapter 4: outline 4.1 Overview of Network layer data plane control plane 4.2 What s inside a router 4.3 IP: Internet Protocol datagram format fragmentation IPv4
More informationLecture 24: Scheduling and QoS
Lecture 24: Scheduling and QoS CSE 123: Computer Networks Alex C. Snoeren HW 4 due Wednesday Lecture 24 Overview Scheduling (Weighted) Fair Queuing Quality of Service basics Integrated Services Differentiated
More informationGrowth of the Internet Network capacity: A scarce resource Good Service
IP Route Lookups 1 Introduction Growth of the Internet Network capacity: A scarce resource Good Service Large-bandwidth links -> Readily handled (Fiber optic links) High router data throughput -> Readily
More informationQuality of Service (QoS)
Quality of Service (QoS) The Internet was originally designed for best-effort service without guarantee of predictable performance. Best-effort service is often sufficient for a traffic that is not sensitive
More informationBasic FPGA Architectures. Actel FPGAs. PLD Technologies: Antifuse. 3 Digital Systems Implementation Programmable Logic Devices
3 Digital Systems Implementation Programmable Logic Devices Basic FPGA Architectures Why Programmable Logic Devices (PLDs)? Low cost, low risk way of implementing digital circuits as application specific
More informationControl and Configuration Software for a Reconfigurable Networking Hardware Platform
1 Control and Configuration Software for a Reconfigurable Networking Hardware Platform Todd S. Sproull, John W. Lockwood, David E. Taylor Applied Research Laboratory Washington University Saint Louis,
More informationResearch paper Measured Capacity of an Ethernet: Myths and Reality
Research paper Measured apacity of an Ethernet: Myths and Reality Theoretical work seems to suggest that Ethernet works saturate at 7%. Realistic networks can offer higher throughputs Lessons learnt Don
More informationA distributed architecture of IP routers
A distributed architecture of IP routers Tasho Shukerski, Vladimir Lazarov, Ivan Kanev Abstract: The paper discusses the problems relevant to the design of IP (Internet Protocol) routers or Layer3 switches
More informationExperimental Evaluation of a Coarse-Grained Switch Scheduler
Experimental Evaluation of a Coarse-Grained Switch Scheduler Charlie Wiseman Washington University Jon Turner Washington University Ken Wong Washington University Brandon Heller Washington University wiseman@wustl.edu
More informationOptimizing Memory Bandwidth of a Multi-Channel Packet Buffer
Optimizing Memory Bandwidth of a Multi-Channel Packet Buffer Sarang Dharmapurikar Sailesh Kumar John Lockwood Patrick Crowley Dept. of Computer Science and Engg. Washington University in St. Louis, USA.
More informationImplementation of Boundary Cutting Algorithm Using Packet Classification
Implementation of Boundary Cutting Algorithm Using Packet Classification Dasari Mallesh M.Tech Student Department of CSE Vignana Bharathi Institute of Technology, Hyderabad. ABSTRACT: Decision-tree-based
More informationNetworking hierarchy Internet architecture
Networking hierarchy Internet architecture Physical layer lasers, fibers, RF, antennas, modulation, demodulation Datalink layer Ethernet, SONET Network layer IP Transport layer TCP, UDP LANs (ACES building)
More informationNetwork Layer Enhancements
Network Layer Enhancements EECS 122: Lecture 14 Department of Electrical Engineering and Computer Sciences University of California Berkeley Today We have studied the network layer mechanisms that enable
More informationTable of Contents. Cisco Buffer Tuning for all Cisco Routers
Table of Contents Buffer Tuning for all Cisco Routers...1 Interactive: This document offers customized analysis of your Cisco device...1 Introduction...1 Prerequisites...1 Requirements...1 Components Used...1
More informationSwitching and Forwarding - continued
Fall 9/7 CptS/EE 555 Fall 9/7 CptS/EE 555 4 Housekeeping Look at select system call See homework solutions on the Lecture Notes web page for answer to the probability difficulties we (I) had last time
More informationCisco Nexus 9500 Series Switches Buffer and Queuing Architecture
White Paper Cisco Nexus 9500 Series Switches Buffer and Queuing Architecture White Paper December 2014 2014 Cisco and/or its affiliates. All rights reserved. This document is Cisco Public Information.
More informationScalable Packet Classification on FPGA
Scalable Packet Classification on FPGA 1 Deepak K. Thakkar, 2 Dr. B. S. Agarkar 1 Student, 2 Professor 1 Electronics and Telecommunication Engineering, 1 Sanjivani college of Engineering, Kopargaon, India.
More informationPUSHING THE LIMITS, A PERSPECTIVE ON ROUTER ARCHITECTURE CHALLENGES
PUSHING THE LIMITS, A PERSPECTIVE ON ROUTER ARCHITECTURE CHALLENGES Greg Hankins APRICOT 2012 2012 Brocade Communications Systems, Inc. 2012/02/28 Lookup Capacity and Forwarding
More informationIntroduction CHAPTER 1
1 CHAPTER 1 Introduction The Internet is comprised of a mesh of routers interconnected by links. Communication among nodes on the Internet (routers and end-hosts) takes place using the Internet Protocol,
More informationLecture 13. Quality of Service II CM0256
Lecture 13 Quality of Service II CM0256 Types of QoS Best Effort Services Integrated Services -- resource reservation network resources are assigned according to the application QoS request and subject
More informationQuality of Service. Understanding Quality of Service
The following sections describe support for features on the Cisco ASR 920 Series Router. Understanding, page 1 Configuring, page 2 Global QoS Limitations, page 2 Classification, page 3 Marking, page 6
More informationCSE 473 Introduction to Computer Networks. Exam 1. Your name: 9/26/2013
CSE 473 Introduction to Computer Networks Jon Turner Exam 1 Your name: 9/26/2013 1. (10 points). A user in Chicago, connected to the internet via a 100 Mb/s (b=bits) connection retrieves a 250 KB (B=bytes)
More informationFPgrep and FPsed: Packet Payload Processors for Managing the Flow of Digital Content on Local Area Networks and the Internet
Washington University in St. Louis Washington University Open Scholarship All Computer Science and Engineering Research Computer Science and Engineering Report Number: WUCSE-2003-56 2003-07-29 FPgrep and
More informationFPGA Based Packet Classification Using Multi-Pipeline Architecture
International Journal of Wireless Communications and Mobile Computing 2015; 3(3): 27-32 Published online May 8, 2015 (http://www.sciencepublishinggroup.com/j/wcmc) doi: 10.11648/j.wcmc.20150303.11 ISSN:
More informationDesign of a Flexible Open Platform for High Performance Active Networks
Design of a Flexible pen Platform for High Performance Active Networks Sumi Choi, Dan Decasper, John Dehart, Ralph Keller John Lockwood, Jonathan Turner and Tilman Wolf fsyc1, dan, jdd, keller, lockwood,
More informationChapter 1. Introduction
Chapter 1 Introduction In a packet-switched network, packets are buffered when they cannot be processed or transmitted at the rate they arrive. There are three main reasons that a router, with generic
More information