Demonstration of a High Performance Active Router DARPA Demo - 9/24/99
|
|
|
- Norma Atkinson
- 5 years ago
- Views:
Transcription
1 Demonstration of a High Performance Active Router DARPA Demo - 9/24/99 Dan Decasper, John DeHart, Ralph Keller, Jonathan Turner, Sumi Choi and Tilman Wolf University, Applied Research Lab (best viewed in presentation mode) 1
2 Motivation Technology advances adding new functionality to internet routers.» logic capabilities growing much faster than IO» packet classification, per flow queueing becoming common» single chip packet processing engines with 16 processors now becoming available Application-specific processing in routers could become routine.» active networking is one way to exploit trend» alternative model signalling and resource reservation packet classification and flow-specific routing Key challenge is application software. Need better experimental platforms for researchers. 2
3 Towards an Open Internet Router Modular components.» ability to swap components - both hardware and software routing, signalling, management software address lookup and packet classification queueing and packet scheduling» open, documented and straightforward interfaces Dynamic insertion of application-specific processing.» active networking model and others High performance.» gigabit links and scalability to large numbers of ports» packet processing rates of at least a million/second per link» application-specific processing on large fraction of traffic» need credible demonstrations to influence commercial practice 3
4 Active Router Hardware LCs AN Processing Element CP s IPPs Pentium NB Cache APIC MB Sys. FPGA Switch Control Processor OPPs global s coordination LCs & control routing protocols build routing tables and other information needed by SPCs first level code server reprogrammable for active processing Input Port Processor VCI VCI OUT 4
5 Cell Processing CP LCs s IPPs OPPs s LCs 3 Switch
6 Packet Processing CP LCs s IPPs OPPs s LCs Switch Pentium Cache NB APIC Sys. FPGA Pentium Cache NB Sys. FPGA APIC 6
7 Principal Data Flows Through PE Kernel IP Packets Packet Classification and Routing Packet + Flow Id IPv4/6 Header Processing Plain Packets Active Packets Kernel Plugins Driver SAPF Packet Active Function Dispatcher Selector/ Dispatcher Packet Scheduler Driver Std. proc. for plain IP packets.» classification & routing, header processing, output queueing» streamlined processing of SAPF packets using pre-established state 7 Resource Controller Active packets move through configured kernel plugins.» active function dispatcher passes packets to instances of plugin objects» instantiates objects or triggers download of plugin class, as needed
8 System Level Software Organization Active Code DB Code Server Code Server Plugin Requestor Plugin DB Plugin DB Controller Policy Rules Policy Controller Active Plugin Loader Key DB Security Gateway Kernel Control Processor Routing & Signalling ANN Manager ANTS Java VM anetd Switch Fabric Plugin Requestor Security & Policy Controller Processing Elements Plugin Requestor Security & Policy Controller Active Plugin Loader Kernel... Active Plugin Loader Kernel 8
9 Physical Configuration Optoelectronics Connectors Main Circuit Board O Fiber jumper to front panel Processor Module I O I O I O SE I SE SE I O SE I Transmission Coder & Decoder APIC System FPGA O I O I O 9
10 Active Congestion Control for Based on wavelet-based encoding method (Wave)» up to hundreds of distinct frequency subbands (33)» low frequencies: general image definition» high frequencies: image details Active Wave plugin» detects congestion» discards packets in high frequency subbands first Better performance than layered multicast» requires large number of multicast groups» reacts too slowly to congestion ( several seconds) 10
11 Wave Scaling bytes (33) bytes (30) bytes (27) 9265 bytes (24) 7042 bytes (21) 4819 bytes (18) 2617 bytes (15) 2006 bytes (12) 1393 bytes (9) 793 bytes (6) 447 bytes (3) 227 bytes (1) 11
12 Logical Demonstration Configuration Display 1 P Display 2 Display 3 Source Source 1 Source 2 Cross Traffic Sink Code Server Key Server 12
13 Performance (light cross traffic) Original Plain Queueing Active Queueing MPEG video player required for playback. 13
14 Performance (heavy cross traffic) Original Plain Queueing Active Queueing MPEG video player required for playback. 14
15 Demo Instrumentation (simplified) no loss high frequency subbands plain queueing low frequency subbands grey level shows amount of data received white: nothing received black: everything received active dropping time 15
16 Demonstration Start Display 1 Display 2 Display 3 Source Source 1 Source 2 Cross Traffic Sink Code Server Key Server 16
17 Light - Plain Queueing Display 1 Display 2 Display 3 Source Source 1 Source 2 Cross Traffic Sink Code Server Key Server 17
18 Light - Plain Queueing First Display (no cross traffic) Second Display (with cross traffic) Third Display (with cross traffic) 18
19 Heavy - Plain Queueing Display 1 Display 2 Display 3 Source Source 1 Source 2 Cross Traffic Sink Code Server Key Server 19
20 Heavy - Plain Queueing First Display (no cross traffic) Second Display (light cross traffic) Third Display (heavy cross traffic) 20
21 Light - Active Queueing Display 1 P Display 2 Display 3 Source Source 1 Source 2 Cross Traffic Sink Code Server Key Server 21
22 Light - Active Queueing First Display (no cross traffic) Second Display (with cross traffic) Third Display (with cross traffic) 22
23 Heavy - Active Queueing Display 1 P Display 2 Display 3 Source Source 1 Source 2 Cross Traffic Sink Code Server Key Server 23
24 Heavy - Active Queueing First Display (no cross traffic) Second Display (light cross traffic) Third Display (heavy cross traffic) 24
25 Bursty - Plain Queueing Display 1 Display 2 Display 3 Source Source 1 Source 2 Cross Traffic Sink 2.4 MB bursts, 2 second idle time Code Server Key Server 25
26 Bursty - Plain Queueing First Display (no cross traffic) Second Display (with cross traffic) Third Display (with cross traffic) 26
27 Bursty - Active Queueing Display 1 P Display 2 Display 3 Source Source 1 Source 2 Cross Traffic Sink 2.4 MB bursts, 2 second idle time Code Server Key Server 27
28 Bursty - Active Queueing First Display (no cross traffic) Second Display (with cross traffic) Third Display (with cross traffic) 28
29 Credits Sumi Choi Ed Spitznagel Ralph Keller Dan Decasper Dave Taylor Dave Richard John Dehart Tilman Wolf 29
Design of a Flexible Open Platform for High Performance Active Networks
Design of a Flexible pen Platform for High Performance Active Networks Sumi Choi, Dan Decasper, John Dehart, Ralph Keller John Lockwood, Jonathan Turner and Tilman Wolf fsyc1, dan, jdd, keller, lockwood,
ANN. A Scalable, High Performance Active Network Node. Dan Decasper.
ANN A Scalable, High Performance Active Network Node Dan Decasper dan@arl.wustl.edu Applied Research Laboratory (ARL), Washington University, St.Louis Computer Engineering and Network Laboratory (TIK),
First Gigabit Kits Workshop
First Gigabit Kits Workshop July 12-13, 1999 Jonathan Turner Washington University Computer Science Department http://www.arl.wustl.edu/gigabitkits/kits.html Jonathan Turner 11/8/99 1 Agenda Monday, July
A Scalable High-Performance Active Network Node
A Scalable High-Performance Active Network Node D. Decasper, B. Plattner ETH Zurich G. Parulkar, S. Choi, J. DeHart, T. Wolf Washington U Presented by Jacky Chu Motivation Apply Active Network over gigabits
FPX Architecture for a Dynamically Extensible Router
FPX Architecture for a Dynamically Extensible Router Alex Chandra, Yuhua Chen, John Lockwood, Sarang Dharmapurikar, Wenjing Tang, David Taylor, Jon Turner http://www.arl.wustl.edu/arl Dynamically Extensible
The Washington University Smart Port Card
The Washington University Smart Port Card John DeHart Washington University jdd@arl.wustl.edu http://www.arl.wustl.edu/~jdd 1 SPC Personnel Dave Richard - Overall Hardware Design Dave Taylor - System FPGA
Design and Evaluation of a High-Performance Dynamically Extensible Router
Design and Evaluation of a High-Performance Dynamically Extensible Router Fred Kuhns, John DeHart, Anshul Kantawala, Ralph Keller, John Lockwood, Prashanth Pappu, David Richard, David Taylor, Jyoti Parwatikar,
Design of a High Performance Dynamically Extensible Router
Design of a High Performance Dynamically Extensible Router Fred Kuhns, John DeHart, Anshul Kantawala, Ralph Keller, John Lockwood, Prashanth Pappu, David Richards, David Taylor, Jyoti Parwatikar, Ed Spitznagel,
SPC and Crossbow. John DeHart Acknowledgements
SPC and Crossbow John DeHart jdd@arl.wustl.edu January 10, 2001 WUGS Kits Workshop Washington 1 Acknowledgements Special Thanks to: Sumi Choi Anshul Kantawala Fred Kuhns Samphel Norden Jyoti Parwatikar
A Platform for High Performance Overlay Hosting Services
A Platform for High Performance Overlay Hosting Services Jon Turner with Patrick Crowley, John DeHart, Brandon Heller, Fred Kuhns, Sailesh Kumar, John Lockwood, Jing Lu, Mike Wilson, Charlie Wiseman and
ECE 697J Advanced Topics in Computer Networks
ECE 697J Advanced Topics in Computer Networks Switching Fabrics 10/02/03 Tilman Wolf 1 Router Data Path Last class: Single CPU is not fast enough for processing packets Multiple advanced processors in
Users Guide: Fast IP Lookup (FIPL) in the FPX
Users Guide: Fast IP Lookup (FIPL) in the FPX Gigabit Kits Workshop /22 FIPL System Design Each FIPL Engine performs a longest matching prefix lookup on a single 32-bit IPv4 destination address FIPL Engine
Design Issues for High Performance Active Routers
Design Issues for High Performance Active Routers Tilman Wolf, Jonathan Turner fwolf,jstg@arl.wustl.edu Abstract Active networking is a general approach to incorporating general-purpose computational capabilities
BROADBAND PACKET SWITCHING TECHNOLOGIES
BROADBAND PACKET SWITCHING TECHNOLOGIES A Practical Guide to ATM Switches and IP Routers H. JONATHAN CHAO CHEUK H. LAM EMI OKI A Wiley-lnterscience Publication JOHN WILEY & SONS, INC. New York / Chichester
Tags for High Performance Active Networks. Tilman Wolf 1, Dan Decasper 1, Christian Tschudin 2. Applied Research Laboratory
Tags for High Performance Active Networks Tilman Wolf 1, Dan Decasper 1, Christian Tschudin 2 1 fwolf, dang@arl.wustl.edu Applied Research Laboratory Washington University, St. Louis, MO, USA 2 tschudin@docs.uu.se
Using the Open Network Lab
Using the Open Network Lab Jon Turner Applied Research Laboratory Computer Science and Engineering Department http://www.arl.wustl.edu/arl 2 - Jonathan Turner 1/31/2006 Motivation What is ONL?» remotely
Quality of Service (QoS)
Quality of Service (QoS) The Internet was originally designed for best-effort service without guarantee of predictable performance. Best-effort service is often sufficient for a traffic that is not sensitive
The router architecture consists of two major components: Routing Engine. 100-Mbps link. Packet Forwarding Engine
Chapter 4 The router architecture consists of two major components: Packet Forwarding Engine Performs Layer 2 and Layer 3 packet switching, route lookups, and packet forwarding. Routing Engine Provides
Design Issues for High Performance Active Routers
Design Issues for High Performance Active Routers Tilman Wolf, Jonathan S. Turner WUCS-99-19 June 11, 1999 Department of Computer Science Washington University Campus Box 1045 One Brookings Drive St. Louis,
Implementation of an Open Multi-Service Router
Implementation of an Open Multi-Service Router Fred Kuhns, John DeHart, Ralph Keller, John Lockwood, Prashanth Pappu, Jyoti Parwatikar, Ed Spitznagel, David Richards, David Taylor, Jon Turner and Ken Wong
Router Architectures
Router Architectures Venkat Padmanabhan Microsoft Research 13 April 2001 Venkat Padmanabhan 1 Outline Router architecture overview 50 Gbps multi-gigabit router (Partridge et al.) Technology trends Venkat
Router Construction. Workstation-Based. Switching Hardware Design Goals throughput (depends on traffic model) scalability (a function of n) Outline
Router Construction Outline Switched Fabrics IP Routers Tag Switching Spring 2002 CS 461 1 Workstation-Based Aggregate bandwidth 1/2 of the I/O bus bandwidth capacity shared among all hosts connected to
Field-programmable Port Extender (FPX) August 2001 Workshop. John Lockwood, Assistant Professor
Field-programmable Port Extender (FPX) August 2001 Workshop John Lockwood, Lockwood@arl.wustl.edu Assistant Professor Washington University Department of Computer Science Applied Research Lab 1 Brookings
Marking Traffic CHAPTER
CHAPTER 7 To service the growing numbers of customers and their needs, service provider networks have become more complex and often include both Layer 2 and Layer 3 network devices. With this continued
Smart Port Card (SPC) William Eatherton Toshiya Aramaki Edward Spitznagel Guru Parulkar Applied Research Lab Washington University in St.
Smart Port Card (SPC) William Eatherton Toshiya Aramaki Edward Spitznagel Guru Parulkar Applied Research Lab William N. Eatherton 1 Design Goals For several Gigabit Switch related projects, a processing
SEVER INSTITUTE OF TECHNOLOGY DOCTOR OF SCIENCE DEGREE DISSERTATION ACCEPTANCE. (To be the first page of each copy of the dissertation)
SEVER INSTITUTE OF TECHNOLOGY DOCTOR OF SCIENCE DEGREE DISSERTATION ACCEPTANCE (To be the first page of each copy of the dissertation) DATE: May 3, 2002 STUDENT S NAME: Tilman Wolf This student s dissertation,
CS/EE 577 Final Exam December 17, 1996
CS/EE 577 Final Exam December 17, 1996 This is a closed book exam. 1. (8 points) The virtual path/circuit table shown below is of the type introduced in the first section of the lecture notes. A copy of
Network Management & Monitoring Network Delay
Network Management & Monitoring Network Delay These materials are licensed under the Creative Commons Attribution-Noncommercial 3.0 Unported license (http://creativecommons.org/licenses/by-nc/3.0/) End-to-end
Keywords -- Programmable router, reconfigurable hardware, active networking, port processor. I. INTRODUCTION
Dynamic Hardware s (DHP): Exploiting Reconfigurable Hardware for High-Performance Programmable Routers David E. Taylor, Jonathan S. Turner, John W. Lockwood det3@arl.wustl.edu, jst@cs.wustl.edu, lockwood@arl.wustl.edu
Real-Time Protocol (RTP)
Real-Time Protocol (RTP) Provides standard packet format for real-time application Typically runs over UDP Specifies header fields below Payload Type: 7 bits, providing 128 possible different types of
Extensible Network Security Services on Software Programmable Router OS. David Yau, Prem Gopalan, Seung Chul Han, Feng Liang
Extensible Network Security Services on Software Programmable Router OS David Yau, Prem Gopalan, Seung Chul Han, Feng Liang System Software and Architecture Lab Department of Computer Sciences Purdue University
Sample Routers and Switches. High Capacity Router Cisco CRS-1 up to 46 Tb/s thruput. Routers in a Network. Router Design
outer Design outers in a Network Overview of Generic outer Architecture Input-d Switches (outers) IP Look-up Algorithms Packet Classification Algorithms Sample outers and Switches Cisco 46 outer up to
A Preferred Service Architecture for Payload Data Flows. Ray Gilstrap, Thom Stone, Ken Freeman
A Preferred Service Architecture for Payload Data Flows Ray Gilstrap, Thom Stone, Ken Freeman NASA Research and Engineering Network NASA Advanced Supercomputing Division NASA Ames Research Center Outline
The Network Layer and Routers
The Network Layer and Routers Daniel Zappala CS 460 Computer Networking Brigham Young University 2/18 Network Layer deliver packets from sending host to receiving host must be on every host, router in
Cisco Series Internet Router Architecture: Packet Switching
Cisco 12000 Series Internet Router Architecture: Packet Switching Document ID: 47320 Contents Introduction Prerequisites Requirements Components Used Conventions Background Information Packet Switching:
Cell Switching (ATM) Commonly transmitted over SONET other physical layers possible. Variable vs Fixed-Length Packets
Cell Switching (ATM) Connection-oriented packet-switched network Used in both WAN and LAN settings Signaling (connection setup) Protocol: Q2931 Specified by ATM forum Packets are called cells 5-byte header
Multiprotocol Label Switching
This module describes and how to configure it on Cisco switches. Restrictions for, page 1 Information about, page 1 How to Configure, page 3 Verifying Configuration, page 6 Restrictions for (MPLS) fragmentation
CHAPTER 3 EFFECTIVE ADMISSION CONTROL MECHANISM IN WIRELESS MESH NETWORKS
28 CHAPTER 3 EFFECTIVE ADMISSION CONTROL MECHANISM IN WIRELESS MESH NETWORKS Introduction Measurement-based scheme, that constantly monitors the network, will incorporate the current network state in the
A distributed architecture of IP routers
A distributed architecture of IP routers Tasho Shukerski, Vladimir Lazarov, Ivan Kanev Abstract: The paper discusses the problems relevant to the design of IP (Internet Protocol) routers or Layer3 switches
Configuring Multiprotocol Label Switching (MPLS)
Configuring Multiprotocol Label Switching (MPLS) Multiprotocol Label Switching, page 1 Finding Feature Information, page 1 Information about Multiprotocol Label Switching, page 1 How to Configure Multiprotocol
Advanced Computer Networks
Advanced Computer Networks QoS in IP networks Prof. Andrzej Duda duda@imag.fr Contents QoS principles Traffic shaping leaky bucket token bucket Scheduling FIFO Fair queueing RED IntServ DiffServ http://duda.imag.fr
Class-based Traffic Aggregation In Optical Packet Switched WDM Networks
Class-based Traffic Aggregation In Optical Packet Switched WDM Networks, Dimitra Simeonidou Photonic Network Research Center Department of Electronic Systems Engineering University of Essex Funded by EPSRC
Understanding Cisco Express Forwarding
Understanding Cisco Express Forwarding Document ID: 47321 Contents Introduction Prerequisites Requirements Components Used Conventions Overview CEF Operations Updating the GRP's Routing Tables Packet Forwarding
Dynamic Flow Switching A New Communication Service for ATM Networks
Appears in Proceedings of Infocom, March 1998, Copyright held by IEEE. Dynamic Flow Switching A New Communication Service for ATM Networks Qiyong Bian, Kohei Shiomoto, Jonathan Turner {bian,shiomoto,jst}@cs.wustl.edu
A Smart Port Card Tutorial --- Hardware
A Smart Port Card Tutorial --- Hardware John DeHart Washington University jdd@arl.wustl.edu http://www.arl.wustl.edu/~jdd 1 References: New Links from Kits References Page Intel Embedded Module: Data Sheet
Chapter 8. Operating System Support. Yonsei University
Chapter 8 Operating System Support Contents Operating System Overview Scheduling Memory Management Pentium II and PowerPC Memory Management 8-2 OS Objectives & Functions OS is a program that Manages the
Design of a Weighted Fair Queueing Cell Scheduler for ATM Networks
Design of a Weighted Fair Queueing Cell Scheduler for ATM Networks Yuhua Chen Jonathan S. Turner Department of Electrical Engineering Department of Computer Science Washington University Washington University
Chapter 5. The Network Layer
Chapter 5 The Network Layer Congestion Control Algorithms General Principles of Congestion Control Congestion Prevention Policies Congestion Control in Virtual-Circuit Subnets Congestion Control in Datagram
WASHINGTON UNIVERSITY SEVER INSTITUTE OF TECHNOLOGY DEPARTMENT OF ELECTRICAL ENGINEERING DYNAMIC QUEUE MANAGEMENT FOR NETWORK QUALITY-OF-SERVICE
WASHINGTON UNIVERSITY SEVER INSTITUTE OF TECHNOLOGY DEPARTMENT OF ELECTRICAL ENGINEERING DYNAMIC QUEUE MANAGEMENT FOR NETWORK QUALITYOFSERVICE by YUHUA CHEN Prepared under the direction of Professor Jonathan
Protocol Processing on the FPX
Field-programmable Port Extender (FPX) January 2002 Workshop Protocol Processing on the FPX John Lockwood, Lockwood@arl.wustl.edu Assistant Professor Washington University Department of Computer Science
Cisco Nexus 9500 Series Switches Buffer and Queuing Architecture
White Paper Cisco Nexus 9500 Series Switches Buffer and Queuing Architecture White Paper December 2014 2014 Cisco and/or its affiliates. All rights reserved. This document is Cisco Public Information.
Real-Time Applications. Delay-adaptive: applications that can adjust their playback point (delay or advance over time).
Real-Time Applications Tolerant: can tolerate occasional loss of data. Intolerant: cannot tolerate such losses. Delay-adaptive: applications that can adjust their playback point (delay or advance over
Chapter 5. The Network Layer. Network Layer Design Isues. Store-and-Forward Packet Switching 10/7/2010. Implementation of Connectionless Service
Network Layer Design Isues Chapter 5 The Network Layer Store-and-Forward Packet Switching Services Provided to the Transport Layer Implementation of Connectionless Service Implementation of Connection-Oriented
Chapter 5. The Network Layer
Chapter 5 The Network Layer 1 Network Layer Design Isues Store-and-Forward Packet Switching Services Provided to the Transport Layer Implementation of Connectionless Service Implementation of Connection-Oriented
Chapter 5. The Network Layer. CEN Chapter 5 1
Chapter 5 The Network Layer CEN 445 - Chapter 5 1 Network Layer Design Isues Store-and-Forward Packet Switching Services Provided to the Transport Layer Implementation of Connectionless Service Implementation
MIT International Journal of Electrical and Instrumentation Engineering Vol. 3, No. 1, Jan. 2013, pp
MIT International Journal of Electrical and Instrumentation Engineering Vol. 3, No. 1, Jan. 2013, pp. 15 20 15 MPLS and NGN Networks: The Future Aspects for Railways Communication System Alok Pandey E,
Tag Switching. Background. Tag-Switching Architecture. Forwarding Component CHAPTER
CHAPTER 23 Tag Switching Background Rapid changes in the type (and quantity) of traffic handled by the Internet and the explosion in the number of Internet users is putting an unprecedented strain on the
Network Management & Monitoring
Network Management & Monitoring Network Delay These materials are licensed under the Creative Commons Attribution-Noncommercial 3.0 Unported license (http://creativecommons.org/licenses/by-nc/3.0/) End-to-end
G Robert Grimm New York University
G22.3250-001 Receiver Livelock Robert Grimm New York University Altogether Now: The Three Questions What is the problem? What is new or different? What are the contributions and limitations? Motivation
A Convergence Architecture for GRID Computing and Programmable Networks
A Convergence Architecture for GRID Computing and Programmable Networks Christian Bachmeir, Peter Tabery, Dimitar Marinov, Georgi Nachev, and Jörg Eberspächer Munich University of Technology, Institute
CS 5114 Network Programming Languages Data Plane. Nate Foster Cornell University Spring 2013
CS 5114 Network Programming Languages Data Plane http://www.flickr.com/photos/rofi/2097239111/ Nate Foster Cornell University Spring 2013 Based on lecture notes by Jennifer Rexford and Michael Freedman
Terabit Burst Switching Progress Report (12/97-2/98)
Terabit Burst Switching Progress Report (12/97-2/98) Jonathan S. Turner jst@cs.wustl.edu WUCS-98-16 June 10, 1998 Department of Computer Science Campus Box 1045 Washington University One Brookings Drive
IV. PACKET SWITCH ARCHITECTURES
IV. PACKET SWITCH ARCHITECTURES (a) General Concept - as packet arrives at switch, destination (and possibly source) field in packet header is used as index into routing tables specifying next switch in
A closer look at network structure:
T1: Introduction 1.1 What is computer network? Examples of computer network The Internet Network structure: edge and core 1.2 Why computer networks 1.3 The way networks work 1.4 Performance metrics: Delay,
RPT: Re-architecting Loss Protection for Content-Aware Networks
RPT: Re-architecting Loss Protection for Content-Aware Networks Dongsu Han, Ashok Anand ǂ, Aditya Akella ǂ, and Srinivasan Seshan Carnegie Mellon University ǂ University of Wisconsin-Madison Motivation:
Chapter 4. Routers with Tiny Buffers: Experiments. 4.1 Testbed experiments Setup
Chapter 4 Routers with Tiny Buffers: Experiments This chapter describes two sets of experiments with tiny buffers in networks: one in a testbed and the other in a real network over the Internet2 1 backbone.
Resource Control and Reservation
1 Resource Control and Reservation Resource Control and Reservation policing: hold sources to committed resources scheduling: isolate flows, guarantees resource reservation: establish flows 2 Usage parameter
RSVP 1. Resource Control and Reservation
RSVP 1 Resource Control and Reservation RSVP 2 Resource Control and Reservation policing: hold sources to committed resources scheduling: isolate flows, guarantees resource reservation: establish flows
ADVANCED COMPUTER NETWORKS
ADVANCED COMPUTER NETWORKS Congestion Control and Avoidance 1 Lecture-6 Instructor : Mazhar Hussain CONGESTION CONTROL When one part of the subnet (e.g. one or more routers in an area) becomes overloaded,
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
1 ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology Mikkel B. Stensgaard and Jens Sparsø Technical University of Denmark Technical University of Denmark Outline 2 Motivation ReNoC Basic
Managed IP Services from Dial Access to Gigabit Routers
Managed IP Services from Dial Access to Gigabit Routers Technical barriers and Future trends for IP Differentiated Services Grenville Armitage, PhD Member of Technical Staff High Speed Networks Research,
Operating System Support
William Stallings Computer Organization and Architecture 10 th Edition Edited by Dr. George Lazik + Chapter 8 Operating System Support Application programming interface Application binary interface Instruction
Lesson 3 Network technologies - Controlling
Lesson 3 Network technologies - Controlling Objectives : Network control or traffic engineering is one of the important techniques in the network. Understanding QoS control, traffic engineering and OAM
Computer Networks. Routing
Computer Networks Routing Topics Link State Routing (Continued) Hierarchical Routing Broadcast Routing Sending distinct packets Flooding Multi-destination routing Using spanning tree Reverse path forwarding
IP Packet Switching. Goals of Todayʼs Lecture. Simple Network: Nodes and a Link. Connectivity Links and nodes Circuit switching Packet switching
IP Packet Switching CS 375: Computer Networks Dr. Thomas C. Bressoud Goals of Todayʼs Lecture Connectivity Links and nodes Circuit switching Packet switching IP service model Best-effort packet delivery
Experimental Evaluation of a Coarse-Grained Switch Scheduler
Experimental Evaluation of a Coarse-Grained Switch Scheduler Charlie Wiseman Washington University Jon Turner Washington University Ken Wong Washington University Brandon Heller Washington University wiseman@wustl.edu
Basics (cont.) Characteristics of data communication technologies OSI-Model
48 Basics (cont.) Characteristics of data communication technologies OSI-Model Topologies Packet switching / Circuit switching Medium Access Control (MAC) mechanisms Coding Quality of Service (QoS) 49
Configuring QoS CHAPTER
CHAPTER 37 This chapter describes how to configure quality of service (QoS) by using automatic QoS (auto-qos) commands or by using standard QoS commands on the Catalyst 3750-E or 3560-E switch. With QoS,
signal-to-noise ratio (PSNR), 2
u m " The Integration in Optics, Mechanics, and Electronics of Digital Versatile Disc Systems (1/3) ---(IV) Digital Video and Audio Signal Processing ƒf NSC87-2218-E-009-036 86 8 1 --- 87 7 31 p m o This
ASIX Multi-Port Embedded Ethernet Product Introduction
ASIX Multi-Port Embedded Ethernet Revision 1.1 Mar. 20th, 2008 1 Revision History Revision Date Description 1.0 2008/3/7 Initial release 1.1 2008/3/20 1. Change the document name to ASIX Multi-Port Embedded
Configuring QoS CHAPTER
CHAPTER 36 This chapter describes how to configure quality of service (QoS) by using automatic QoS (auto-qos) commands or by using standard QoS commands on the Catalyst 3750 switch. With QoS, you can provide
Outline. A Professional Company in Software-Defined Networking (SDN) Copyright , EstiNet Technologies Inc. All Rights Reserved..
Physical Layer Outline Signal Propagation Media The Calculation of Signal Delivery Time The Evaluation of End-to-end Delay Signal Encoding and Modulation Wired Signal s Encoding, Decoding and Decoding
The Internetworking Problem. Internetworking. A Translation-based Solution
Cloud Cloud Cloud 1 The Internetworking Problem Internetworking Two nodes communicating across a network of networks How to transport packets through this heterogeneous mass? A B The Internetworking Problem
Open Network Laboratory
Open Network Laboratory Raj Jain Raj Jain Washington University in Saint Louis Saint Louis, MO 63130 Jain@wustl.edu Audio/Video recordings of this lecture are available on-line at: http://www.cse.wustl.edu/~jain/cse473-11/
Networking for Data Acquisition Systems. Fabrice Le Goff - 14/02/ ISOTDAQ
Networking for Data Acquisition Systems Fabrice Le Goff - 14/02/2018 - ISOTDAQ Outline Generalities The OSI Model Ethernet and Local Area Networks IP and Routing TCP, UDP and Transport Efficiency Networking
CMSC 611: Advanced. Interconnection Networks
CMSC 611: Advanced Computer Architecture Interconnection Networks Interconnection Networks Massively parallel processor networks (MPP) Thousands of nodes Short distance (
CSE 473 Introduction to Computer Networks. Midterm Exam Review
CSE 473 Introduction to Computer Networks Midterm Exam Review John DeHart 10/12/2015 1. (10 points). A user in Chicago, connected to the internet via a 100 Mb/s (b=bits) connection retrieves a 250 KB (B=bytes)
Toward a Reliable Data Transport Architecture for Optical Burst-Switched Networks
Toward a Reliable Data Transport Architecture for Optical Burst-Switched Networks Dr. Vinod Vokkarane Assistant Professor, Computer and Information Science Co-Director, Advanced Computer Networks Lab University
WUCS-TM-02-?? September 23, 2005
Field-programmable Port extender (FPX) Support for the Network Services Platform (NSP) Version 1.0 Alex Chandra, Yuhua Chen, John DeHart, Sarang Dharmapurikar, Fred Kuhns, John W. Lockwood, Wen-Jing Tang,
Multimedia Networking
CMPT765/408 08-1 Multimedia Networking 1 Overview Multimedia Networking The note is mainly based on Chapter 7, Computer Networking, A Top-Down Approach Featuring the Internet (4th edition), by J.F. Kurose
CS High Speed Networks. Dr.G.A.Sathish Kumar Professor EC
CS2060 - High Speed Networks Dr.G.A.Sathish Kumar Professor EC UNIT V PROTOCOLS FOR QOS SUPPORT UNIT V PROTOCOLS FOR QOS SUPPORT RSVP Goals & Characteristics RSVP operations, Protocol Mechanisms Multi
Overview. TCP & router queuing Computer Networking. TCP details. Workloads. TCP Performance. TCP Performance. Lecture 10 TCP & Routers
Overview 15-441 Computer Networking TCP & router queuing Lecture 10 TCP & Routers TCP details Workloads Lecture 10: 09-30-2002 2 TCP Performance TCP Performance Can TCP saturate a link? Congestion control
because all web objects are not cacheable [3]. Data compression algorithms are applied on the information content of the web object.
![because all web objects are not cacheable [3]. Data compression algorithms are applied on the information content of the web object.](/thumbs/96/129240796.jpg "because all web objects are not cacheable [3]. Data compression algorithms are applied on the information content of the web object.")
Development of an Optimization Algorithm for Internet Data Traffic Syed Misbahuddin and Tariq Ibn Aziz Department of Computer Science and Software Engineering Hail Community College King Fahd University
ETSF05/ETSF10 Internet Protocols. Routing on the Internet
ETSF05/ETSF10 Internet Protocols Routing on the Internet Circuit switched routing ETSF05/ETSF10 - Internet Protocols 2 Routing in Packet Switching Networks Key design issue for (packet) switched networks
Lecture 3: Packet Forwarding
Lecture 3: Packet Forwarding CSE 222A: Computer Communication Networks Alex C. Snoeren Thanks: Mike Freedman & Amin Vahdat Lecture 3 Overview Paper reviews Packet Forwarding IP Addressing Subnetting/CIDR
Global Interface Commands on the Cisco ASR 9000 Series Router
Global Interface Commands on the Cisco ASR 9000 Series Router This module provides global command line interface (CLI) commands for configuring interfaces on the Cisco ASR 9000 Series Aggregation Services
WUCS-TM-02-?? September 13, 2002
Field-programmable Port extender (FPX) Support for the Multi-Service Router (MSR) Version 1.0 David E. Taylor, Sarang Dharmapurikar, John W. Lockwood, Jonathan S. Turner, Yuhua Chen, Alex Chandra, Wen-Jing
Design Space Exploration of Network Processor Architectures
Design Space Exploration of Network Processor Architectures ECE 697J December 3 rd, 2002 ECE 697J 1 Introduction Network processor architectures have many choices Number of processors Size of memory Type
CHAPTER 3 WIRELESS MEASUREMENT INSTRUMENT
CHAPTER 3 WIRELESS MEASUREMET ISTRUMET This chapter gives a functional description of the WMI hardware and software for implementation in IVDS. A detailed technical description is not given, but is provided
Module 6 STILL IMAGE COMPRESSION STANDARDS
Module 6 STILL IMAGE COMPRESSION STANDARDS Lesson 19 JPEG-2000 Error Resiliency Instructional Objectives At the end of this lesson, the students should be able to: 1. Name two different types of lossy