Design-Rule-Aware Congestion Model with Explicit Modeling of Vias and Local Pin Access Paths

Transcription

1 Qi ZD, Cai YC, Zhou Q. Design-rule-aware congestion model with explicit modeling of vias and local pin access paths. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 30(3): May DOI /s Design-Rule-Aware Congestion Model with Explicit Modeling of Vias and Local Pin Access Paths Zhong-Dong Qi ( ý), Student Member, IEEE, Yi-Ci Cai ( ), Senior Member, CCF, IEEE, and Qiang Zhou ( Ö), Senior Member, CCF, ACM, IEEE Department of Computer Science and Technology, Tsinghua University, Beijing , China qzd11@mails.tsinghua.edu.cn; {caiyc, zhouqiang}@mail.tsinghua.edu.cn Received March 31, 2014; revised October 14, Abstract As technology advances, there is a considerable gap between the congestion model used in global routing and the routing resource consumption in detailed routing. The new factors contributing to congestion include local pin access paths, vias, and various design rules. In this paper, we propose a practical congestion model with measurement of the impact of design rules, and resources consumed by vias and local pin access paths. The model is compatible with path search algorithms commonly used in global routing. Validated by full-flow routing, this congestion model correlates better with real resource consumption situation in detailed routing, compared with previous work. It leads to better solution quality and shorter runtime of detailed routing when it is used in the layer assignment phase of global routing stage. Keywords congestion modeling, design rule, global routing 1 Introduction In back-end VLSI design, routing is one of the most important and difficult phases, which constructs physical geometries of interconnections on chip. It determines several crucial metrics such as timing, power, and yield of designs. Due to high problem complexity, routing generally consists of two stages, namely global routing (GR) and detailed routing (DR). Global routing plans the coarse paths of interconnections with the estimation of routing resources. Guided by global routing results, detailed routing searches detailed paths and generates real wires and vias for interconnections. During global routing, the multi-layer routing region is tessellated into rectangular global routing cells (a.k.a. gcells), and a 3D routing grid graph G = (V,E) is built based on the tessellation, as illustrated in Fig.1. In the grid graph, each vertex v V represents a gcell, while each edge e E connecting two vertices represents the region between two corresponding gcells. To guide path search in global routing, the quantity of routing resources on each edge e is measured as the capacity of e, denoted by c(e). The quantity of routing resources consumed by routing paths on each edge e is estimated as the demand of e, denoted by d(e). The capacity of an edge is measured by the number of available routing tracks crossing the boundary of two adjacent gcells, while the number of wire segments crossing gcell boundary is used to calculate edge demand. This congestion model is adopted in major global routers, e.g., [1-5]. We call this model as traditional routing congestion model. Gcell (a) Gcell Boundary Edge Fig.1. Grid graph used in global routing. (a) Region tessellation. (b) Routing grid graph. (b) Regular Paper This work was supported by the National Natural Science Foundation of China under Grant No A preliminary version of the paper was published in the Proceedings of CAD/Graphics Springer Science + Business Media, LLC & Science Press, China

2 Zhong-Dong Qi et al.: Congestion Model in Global Routing 615 To make guidance of global routing paths be accurate in detailed routing, a congestion model which seeks to accurately measure detailed routability should be used in global routing. However, as technology advances, the traditional congestion model is not capable to capture various factors in detailed routing resource consumption. In modern technology, standard cells become smaller and denser. The number of pins intra a gcell becomes larger. The local access paths to pins consume significant resources on lower metal layers, e.g., Metal2 and Metal3. However, resource consumption of pin access paths is ignored in the traditional congestion model. Starting from 90nm technology node, varying width and thickness metal layers are available in VLSI designs. The varying metal widths and thicknesses introduce fat vias into interconnections, which consume more resources than normal vias. In addition, since the routing layer number also increases with successive technology nodes, more stacked vias are formed in multi-layer interconnections, whose resource consumption cannot be ignored any longer. Due to sub-resolution lithography, chemicalmechanical polishing(cmp) and yield enhancement requirements, the number of design rules becomes larger in successive technology nodes. For example, a polygon with area less than a certain value violates the minimum area rule. A polygon too close to the end of another polygon violates the end-of-line spacing rule. The design rules greatly affect the quantity of routing resources consumed by stacked vias and small connections. The traditional congestion model does not take above factors into account and underestimates routing resource consumption. An inaccurate congestion model would mislead global router path search. Using the model, a global routing path could be unroutable in the detailed routing stage, causing costly path rerouting in dense detailed routing grid. Further, all predictions (such as wirelength, via count and timing) made by the global router could be impractical. In recent years, some pioneer studies have been developed, attempting to reduce the inconsistency between GR congestion model and DR resource consumption situation. Hsu et al. [6] proposed concepts of via capacity and via overflow to address the congestion modeling gap between GR and DR, with emphasis on stacked vias. However, as the technology node becomes even smaller, this model is not practical and outdated. After that, in work of Taghavi et al. [7], pin geometries and density were used to measure detailed routing difficulty and guide routability-driven placement. Wei et al. [8] used pin density factor to calculate resources consumed by pin access paths on lower metal layers. The resource consumption of pin access paths contributes to edge demand in global routing grid graph. Most recently, Shojaei et al. [9] proposed a method of nonuniformly resizing gcell dimensions to reduce local net number, and used vertex capacity and demand to measure resources consumed by local nets. The above studies improved the accuracy of congestion modeling in global routing or routability estimation during placement. However, none of them model fat vias and related design rules. In addition, resource consumption of vias and pin access paths has not been measured in a unified model yet. To capture real detailed routing congestion factors including fat vias, stacked vias, pin access paths, and related design rules in global routing stage, we propose a practical congestion model in global routing. Using a concept of pass-through capacity and demand, intragcell congestion caused by vias and small connections can be captured, with modeling of related design rules. To show the effectiveness of more accurate congestion modeling, we implement a layer assignment algorithm using the proposed congestion model. With fullflow routing, the experimental results demonstrate that using the proposed model, the global router can guide detailed router to achieve smaller number of design rule violations, shorter runtime, and better wirelength and via count, compared with the pin blockage factor model in previous work. Our contributions are as follows. We propose a concept of pass-through capacity and demand to model intra-gcell congestion. Major design rules which influence routing resource consumption, such as width-length-dependent spacing, minimum area and end-of-line spacing, are analyzed and modeled. Vias and local nets are modeled. We also extend local nets modeling to local pin access paths modeling using regression technique. Application of the model in layer assignment is presented. Experiments using two academic global routers and a commercial detailed router validate the effectiveness of this model. The rest of the paper is organized as follows. Section 2 analyzes major design rules and their impact on routing resource consumption. Section 3 describes the

3 616 J. Comput. Sci. & Technol., May 2015, Vol.30, No.3 details of the proposed congestion model, while Section 4 presents the model s compatibility with existing global routing algorithms and application in layer assignment. Experimental validation is given in Section 5 followed by conclusions in Section 6. Minimum Area. This rule specifies the minimum metal arearequiredforapolygononalayer. Eachpolygon must have an area that is greater than or equal to a minimum value. This rule is often triggered by short wires and stack via enclosures. 2 Design Rules Impact on Resource Consumption h s h Design rules forbid certain features or patterns in layout and restrict path search in detailed routing. This increases the quantity of resources consumed by routes in detailed routing. However, many rules are seldom triggered in practical designs, and some rules do not affect resource consumption in detailed routing significantly. We list some most influential design rules as follows. Width-Length-Dependent Spacing. In sub-90nm technologies, the spacing value between objects of different nets depends on both width and parallel run length of two objects. An example of width-length-dependent spacing is shown in Fig.2. The objects with minimum width of this layer do not require extra spacing. Objects with wider width and longer parallel run length require larger spacing. During routing, only small portion of nets are assigned larger width to improve timing performance and signal integrity. These nets require larger spacing from neighboring nets. s1 w 1 w 2 w 3 l 1 s 2 l 2 Fig.2. Illustration of width-length-dependent spacing rule. A larger width w 1 and a parallel run length l 1 need larger spacing s 1. Minimum Enclosure. A via has enclosures on both metal layers it connects. In technology library, the via enclosure is specified with a minimum size. End-of-Line Spacing (EOL Spacing). It indicates that a polygon edge which is shorter than certain length requires spacing greater than or equal to a spacing value beyond the end-of-line within some distance, which is depicted in Fig.3. This rule is often triggered by via enclosures and small wires. Area MinArea (a) w Endofline w within h Fig.3. Illustration of (a) minimum area rule and (b) end-of-line spacing rule. Some rules which do not significantly affect detailed routing resource consumption are: Minimum Step. It specifies minimum step size, or shortest edge length, for a polygon. Minimum Cut. Fat metal wires require more than one via cut to connect. This rule specifies the number of cuts a via must have when it is on a wide wire or pin whose width is greater than a certain value. Other design rules which do not affect resource consumption much include the minimum enclosed area rule, the cut layer spacing rule, the minimum enclosure edge rule, etc. 3 Practical Congestion Model 3.1 Congestion Model with Local Congestion Modeling To enhance the correlation between GR and DR, the congestion model used in GR should capture real DR congestion factors. Therefore, we consider actual resource consumption in sub-90nm design technologies. For example, in a typical 65nm technology node, there are three kinds of different width and thickness metal layers, namely 1X, 2X and 4X metals. Varying metal width and spacing over the layers make per-layer congestion modeling necessary. As shown in Fig.4(a), in a partial global routing gridgraph, thereisanet pathconsistingoffiveviasand two wire segments. In the traditional congestion model, only Metal5 (M5) and Metal6 (M6) wire segments contribute to routing congestion. However, when the path is detailedly routed (shown in Fig.4(b)), it consumes more resources due to stacked vias, fat vias and related design rules. (b)

4 Zhong-Dong Qi et al.: Congestion Model in Global Routing 617 M6 M5 M4 M3 M2 M1 (a) M6 M5 M4 M3 M2 M1 Fig.4. Partial routes created in global routing and detailed routing stages. Metal layers from Metal1 (M1) to Metal4 (M4) are 1X layers, while Metal5 and Metal6 are 2X. (a) Partial global route from Metal1 pin to Metal6. (b) Corresponding detailed route with three stacked vias and one fat via. Fat vias are introduced into interconnections by varying width metal layers. A fat via connects two metal layers with different widths, i.e., a thinner metal layer and a thicker one. In Fig.4(b), the via connecting Metal4 and Metal5 is a fat via. According to the fat via s minimum enclosure specification, the enclosure on thinner metal layer is wider than the minimal width on this layer. To avoid violating the minimum spacing rule, the two adjacent tracks of this enclosure are not available for wires to pass through. In Fig.5(b), A, B and C are all fat via enclosures. As marked by dashed lines, the two tracks adjacent to C are not available for wires to cross the gcell. (b) A More stacked vias are in interconnections as the number of metal layers increases. In smaller technology nodes, a stacked via consumes more routing resources due to the requirement of more design rules. To avoid violating the minimum area rule, a stacked via enclosure on metal layer is extended to increase area. According to the EOL-spacing rule, the enclosure forbids a neighboring wire or via enclosure to place close to it. Via enclosuresaand B in Fig.5(b) areexamples, which are enlarged to avoid violating the minimum area rule. There are a number of local pin access paths including local nets inside gcells. They consume significant quantities of resources on lower metal layers, especially Metal2 and Metal3. This is illustrated in Fig.5, where highlighted routes are local pin access paths. Table 1 lists the local net number in DAC 2012 benchmarks, using two different gcell sizes. Small GCell denotes gcell size of 9 9, while Large GCell 32 40, in unit of routing pitch. Nets and L-Nets represent the number of nets and local nets respectively, while Ratio the ratio of local net number to total net number. Local nets can be up to 11% and 38% of all nets using two different gcell sizes, respectively. Table 1. Local Net Number and Ratio Using Different GCell Sizes Testcase Net (k) Small GCell Large GCell L-Net (k) Ratio L-Net (k) Ratio superblue superblue superblue superblue superblue superblue superblue superblue superblue Average (a) Fig.5. Detailed routing results in a gcell on (a) Metal2 and (b) Metal5. This design has 1X layers from Metal1 to Metal5, and 2X layer Metal6. The highlighted geometries are routing objects of local pin access paths. C (b) B If the resource consumption of pin access paths is ignored in global routing, too many segments would be planned on lower routing layers. Detailed routing would face difficulty and multiple design rule violations would be formed. Fig.6 shows the markers of design rule violations (including layout versus schematic violations, e.g., opens and shorts) in partial layout of a 45nm design if local pin access paths are not modeled in global routing. We can see that ignoring pin access paths during global routing would cause serious issue in detailed routing, especially in regions with dense pins. The local connections are also constrained by design rules like minimum area and EOL spacing. As shown in Fig.5(a) and Fig.5(b), many small connections exist on Metal2 and Metal3.

5 618 J. Comput. Sci. & Technol., May 2015, Vol.30, No.3 modeling of emerging design rules in sub-90nm technologies. Via78 Via67 Extra Detailed Routing Grid Point Consumed by a Fat Via Enclosure Fig.6. Design rule violations (marked by highlighted rectangles) in partial layout. From above, design rules, fat via enclosures, stacked via enclosures, and local pin access paths all contribute to intra-gcell congestion. Ignoring intra-gcell congestion could lead to serious routability issues. For example, a gcell with wire segment number equal to track number cannot have a via to pass through. And a gcell on low metal layers such as M2 or M3 would have local pin access paths. If the global router ignores these resource consumptions and assigns too many wire segments in one gcell, the detailed router would not be able to finish routing inside the gcell. To model detailed routing resource consumption during global routing, let us consider a more detailed example, as shown in Fig.7. This gcell contains 12 tracks, eight wire segments and two fat vias (one stacked and one non-stacked). For inter-gcell connections, it has 12 tracks connecting left and right neighboring gcells respectively. There are 7(6) wire segments connecting the gcell and the left(right) bin, showing inter-gcell congestion as 7/12 = 58% and 6/12 = 50%, on the left and the right side respectively. Measured by these values, the gcell is not congested. However, considering intra-gcell connections, the region is actually too congested to let an extra wire cross the gcell. From this case and those in Fig.5 and Fig.6, we can see that 1) local pin access paths and vias can cause serious routability problems in detailed routing if they are not treated carefully in global routing stage; 2) only inter-gcell congestion (edge congestion in routing grid graph) is not capable to measure real detailed routing congestion. To practically measure detailed routing congestion during global routing, the traditional congestion model lacks the information of intra-gcell congestion and Wire Segment Fig.7. Detailed routed gcell with two fat vias and eight wire segments. We propose a concept of pass-through capacity and demand to model intra-gcell congestion, which is embedded in the nodes of global routing grid graph. In the global routing grid graph, the edge capacity and demand are the same with those in the traditional congestion model to measure inter-gcell congestion. Motivated by the examples shown in Fig.5 and Fig.7, since edge capacity and demand only capture inter-gcell congestion and not intra-gcell congestion, we use pass-through capacity and demand in vertices to model intra-gcell congestion. Local pin access paths, stacked vias and fat vias, which contribute to intragcell congestion, are all inside gcells. As a result, it is natural to model intra-gcell congestion in global routing graph vertices which represent gcells. Let us consider two examples. The first one is a gcell with segment number exactly as available track number. If a via wants to pass through this gcell, placing the via inside the gcell is impossible. The second one is a gcell with some segments and via enclosures, as shown in Fig.7. If a segment wants to pass through this gcell, there is not enough room for it, considering the via enclosure size and spacing rule. Therefore, we use a concept of pass-through capacity and demand embedded in global routing graph vertices to model local congestion. In the 3D global routing grid graph, pass-through capacity and demand are used to represent intra-gcell congestion, while edge capacity and demand are used to measure inter-gcell congestion. The available passthrough capacity models the resource for a wire segment or via to pass through the corresponding gcell, as illustrated in Fig.8.

6 Zhong-Dong Qi et al.: Congestion Model in Global Routing 619 As shown in Fig.9, each node in the global routing grid graph has a value of how many wires can pass through the corresponding gcell. This value also measures the capability of placing small connections in the gcell. To measure congestion, as the edge congestion measurement in the traditional congestion model, a pass-through demand value is with each node. Gcell Via Segment Fig.8. Concept of pass-through demand/capacity. Pass-Through Capacity Edge Capacity X Metal Layer 2X Metal Layer 1X Metal Layer Fig.9. Pass-through capacity embedded in 3D global routing grid graph. Pass-through capacity represents the number of resources intra a gcell. It is calculated by the number of available routing tracks to let wires pass through the gcell. The pass-through demand is contributed by fat vias, stacked vias, local connections and wire segments. 3.2 Modeling of Design Rules, Vias, and Pin Access Paths Design Rules Modeling As presented in Section 2, the major rules affecting routing congestion are width-length-dependent spacing, minimum area, EOL-spacing, and minimum enclosure. These rules affect both inter-gcell congestion and intragcell congestion. Width-Length-Dependent Spacing. The spacing value is determined by the maximum width and the parallel run length of two routing objects. This rule is generally triggered by segments of nets with non-default routing rules (NDRs). NDR is the design rule specified with timing critical nets or special nets (e.g., clock) for the requirement of wider width or wider spacing. To model this, each segment contributes to both edge demand and pass-through demand to corresponding edges and vertices. For net segment S k with NDR r k (w k,s k ), where w k is the specified width and s k the specified spacing, the demand is calculated using the largest two parallel run lengths between the segment and other segments in the gcell, w k, and s k. We denote the largest two parallel run lengths with S k as S i and S j, while the routing pitch on this layer as p (which equals minimum width plus minimum spacing). The spacing values on two sides of S k are: s k,i = max{s k,spc[w k ][parlength(s k,s i )]}, s k,j = max{s k,spc[w k ][parlength(s k,s j )]}, where SPC is the 2D spacing table given in technology library. The demand is calculated as: d k = (w k +s k,i +s k,j )/p. Minimum Area, EOL-Spacing. These rules affect via enclosure and local pin access paths. We want to assign enough resources for each routing object. In detailed routing, a routing object is bloated to minimum area MinArea if its original area is smaller than MinArea. And a routing object with width less than value w needs extra spacing EOLSpace beyond its two line ends. As a result, the resource consumption of a routing object is MinArea/w i /T i if it triggers the minimum area rule. And the resource consumption is (MinArea/w i + 2 EOLSpace)/T i if it triggers the EOL-spacing rule too, where w i is the minimum width on this metal layer, and T i the track length in the gcell Via Modeling A fat via enclosure on a thin metal layer is as wide as the minimum width of the upper thick metal layer which it connects. Due to the minimum spacing rule on a thin metal layer, the via enclosure makes two neighboring wiring tracks unavailable for placing wire segments to pass through. Thus a fat via contributes 3 to pass-through demand of gcell on the thin metal layer. For a stacked via enclosure, it can easily trigger the minimum area rule and the EOL-spacing rule. To avoid design rule violations, the stacked via enclosure is enlarged to the minimum area value MA, and forbids

7 620 J. Comput. Sci. & Technol., May 2015, Vol.30, No.3 another feature to place within distance ES. Thus a stacked via enclosure contributes (MA/w i +2 ES)/T i to the gcell pass-through demand, where w i is the minimum width on this metal layer, and T i the track length in the gcell. This is according to the analysis of the minimum area and EOL-spacing rules in Subsection Afat viaenclosureonathin metallayerblocksseveral routing tracks intra the gcell. Using the spacing rule and minimum enclosure defined for a fat via, the number of routing tracks blocked by the fat via enclosure can be calculated. For example, in a typical 45nm technology, a fat via enclosure can block three tracks. Though two fat via enclosures can be placed adjacently and share some routing tracks, we use a pessimistic estimation to facilitate detailed routing. A fat via enclosure contributes n fat to pass-through demand. In 45nm technology, n fat is set to 3 in our experiments. A stacked via enclosure generally needs an island of M inarea with EOLSpace spacing beyond two lineends. Thus several stacked via enclosures can share a routing track in detailed routing. However, fat vias do not share tracks in the same gcell with a typical gcell size setting by our observation. This makes the difference between the modeling of stacked vias and fat vias. When a stacked via is also a fat via, the resource consumption is calculated in the fat via s way Local Pin Access Paths Modeling Local nets are fully embedded in each gcell. The local connections are usually small, but in a large quantity. They generally do not affect inter-gcell congestion, but greatly affect intra-gcell congestion, especially in lower metal layers such as Metal2 and Metal3. Modeling Approach 1. In our congestion model, each local net is decomposed to segments using rectilinear minimum spanning tree. Since a local net is relatively small, a segment (i.e., a wire in detailed routing) can easily violate the minimum area rule and the EOL-spacing rule. Since local nets are mainly routed on Metal2 and Metal3 layers, horizontal segments contribute to Metal3 pass-through demand, while vertical ones contribute to Metal2 pass-through demand. A wire segment of local nets increases gcell pass-through demand in a similar way that a stacked via enclosure does. The approach described above does not include local pin access paths of global nets inside the gcell. And the pin size and distribution are ignored. In practice, smaller pins are more difficult to access and need more routing resources, while denser packed pins also need more resources than loosely located pins. In addition, for dense pins, not only are M2 and M3 resources needed for pin access paths, higher layer resources may also be used. Thus we propose a more generalapproach for modeling local pin access paths. Modeling Approach 2. Resource consumption of these paths is not easy to estimate, since these paths are routed in detailed routing and are affected by distribution and geometry of pins. Wei et al. [8] used Steiner tree and pin density to estimate resources of pin access paths. However, this is only the first order estimation and not accurate enough. In our approach, we use real detailed routing paths to construct expression of pin access path resource consumption using regression technique. We seek to find the relationship between the quantity of resources consumed by pin access paths and several factors including pin count, pin size, and pin distribution in a gcell. Using routed designs, we get both resource consumption of pin access paths and pin information (count, size, and distribution). Then leastsquare-error regression is used to get the expression of pin access paths resource consumption. In more details, pin access paths among routing objects are identified in each gcell. The portion of tracks occupied by pin access paths is calculated. Then using the pin count, pin access point number, and pin distribution, we get a regression of resource consumption of pin access paths on a certain routing layer k: r(k) = f(p c,p s,p d ), where p c, p s and p d are scalar measurement of pin count, pin size and pin distribution inside the gcell respectively. For each pin i, the scalar metric of pin size p s (i) is the area of pin plus the number of detailed routing grid points it covers. For pins in a gcell, the scalar measurements are average value and standard deviation of all p s (i). The scalar metric of pin distribution p d (i) is its neighboring information, i.e., the ratio of area covered by other nets pins in its neighboring region. In our experiment, the neighboring region is a rectangle bloated from the pin by two pitches. For pins in a gcell, the scale measurements are average value and standard deviation of all p d (i). As a result, the expression is as follows: r(k) = w 1 p c +w 2 µ s +w 3 σ s +w 4 µ d +w 5 σ d,

8 Zhong-Dong Qi et al.: Congestion Model in Global Routing 621 whereµ s, µ d, σ s, σ d areaverageand standarddeviation of pin size and pin distribution measurement, respectively, and w i are coefficients to minimize total square errors. When using the approach, vias connecting the pins in global routes do not contribute to demand during via resource calculation, to prevent them from being double counted in pass-through demand. Because each gcell forms a data point containing resource consumption of pin access paths and pin information for the regression, a design with big number of gcells generally covers most situations of pin information in a gcell. One such design is enough to find the relationship of the quantity of routing resources consumed by pin access paths and information of pins in the gcell. With given design rules, the quantity of routing resources consumed by pin access paths in different designs follows the same relationship with pin information. Once the expression is constructed, it can be used for other unseen designs in the same technology node. 3.3 Calculation of Capacity and Demand The pass-through capacity is calculated by the number of tracks and partial tracks intra the gcell. Local pin access paths and vias all contribute to pass-through demand as described in Subsection 3.2. Inter-gcell wire segments also increase pass-through demand. A minimum-width wire segment passing through the gcell increases pass-through demand by 1. A wire segment with NDR or width larger than the minimum width on the layer contributes demand as presented in Subsection The wire segments connecting to the gcell but not passing through it (denoted as side wire segments) contribute max{n l,n r } to pass-through demand, where N l and N r are number of left/lower and right/upper side wire segments connecting to the gcell, respectively. For example, N l = 2 and N r = 1 for the gcell in Fig.7. If a component (a wire segment or a via enclosure and its connections in a gcell) is related to two or more pass-through demand contribution conditions, the demand by this component is calculated by the maximum value among all conditions. Using the gcell in Fig.7 as an example, the fat via enclosure on the lower side of the gcellwith wiresegmentconnectingtoit is relatedto the two demand contribution conditions, one for fat via enclosure and the other for side wire segment. The fat via enclosure contributes 3 to the demand, while the side wire segment contributes at most 1 to demand. Thus this component increases pass-through demand by 3. Overall, the gcell has pass-through capacity 12 and pass-through demand 12, which means no other wires can pass through this gcell, and no fat vias or stacked vias can be placed in the gcell. From this case, we can also see that this congestion model is relatively conservative, which gives more space to detailed router and is generally helpful for detailed routing in practice. 4 Compatibility and Applications of Proposed Model 4.1 Model Compatibility The proposed congestion model facilitates more accurate guidance for global routing than the traditional model. It is compatible with existing widelyused path search algorithms in global routing, such as maze routing [10-11], A* search [12], pattern routing [13], monotonic routing [3], and various layer assignment algorithms [14-16]. Conventionally, these path search algorithms are carried out on 2D/3D global routing grid graph edges (or nodes). The cost function is related to edge congestion, wirelength, via count, etc. Since nodes are connected by edges on the routing path, it is natural to perform these algorithms on global routing grid graph with both edge and node information. The only revision is to take node congestion into account during path searching. 4.2 Application in Layer Assignment Layer assignment is employed in many leading global routers, e.g., FGR [2], MaizeRouter [4], BoxRouter [17], NTHU-Route [5] and FastRoute [3]. It creates 3D(multi-layer) routing solutions from 2D routing results. COLA [14] is a well-performed layer assignment algorithm used in NTHU-Route. A variant of COLA optimizing via overflow is proposed in [15]. It first determines an order of nets to be processed, and then sequentially assigns layers for each net using this order. Finally, it post-processes each net s assignment result to get a better solution. The core routine in both the sequential assignment stage and the postprocessing stage is a single net layer assignment procedure. This single net layer assignment is to find the solution with minimum total via overflow for the net, using a dynamic programming approach. The layer assignment algorithm can be modified to adapt the proposed congestion model. The modifi-

9 622 J. Comput. Sci. & Technol., May 2015, Vol.30, No.3 cations include updating pass-through demand during layer assignment and taking pass-through overflow into account in single net layer assignment. The pass-through demand contributed by local pin access paths is updated before the layer assignment of all nets, using the approach presented in Subsection During the sequential assignment stage and the post-processing stage, after layer assignment of each single net, pass-through demand contributed by vias and wire segments of this net is updated. In single net layer assignment, the modification is to use total pass-through overflow as the objective, so that the layer assignment gets a solution with good congestion distribution for each net. 5 Experimental Validation 5.1 Experiment Setup We use full-flow routing comprised of global routing, detailed routing and design rule checking to validate the proposed congestion model, which is illustrated in Fig.10. Flow A 2D Global Routing Layer Assignment Detailed Routing Design Rule Checking Flow B 2D Global Routing Layer Assignment Project 3D Routes to 2D Layer Assignment Using Proposed Congestion Model Detailed Routing Design Rule Checking Fig.10. Routing flows used in experiments. To compare the impact of different congestion models, we use two different flow settings, namely flow A and flow B. In both flow settings, global routing is first performed by an academic global router which consists of 2D routing and layer assignment. In Fig.10, it is marked by a dashed rectangle in each flow. We use two academic global routers in the experiments. They are BFG-R [18] and NCTU-GR 2.0 [19-20], which are two global routers supporting DAC 2012 benchmark format as well as routing congestion model proposed by Wei et al. [8] In flow B, the 3D routing solutions produced by the global routers are projected to 2D planes and an extra layer assignment procedure using the proposed congestion model is performed. The layer assignment algorithm is described in Subsection 4.2 and is implemented in C++. The layer assignment results are fed into a commercial detailed router which supports sophisticated design rules and loads external global routing results into the tool. We check routing tools from several EDA vendors to find the capable one. The result is that IC Compiler from Synopsys and SoC Encounter from Cadence do not support loading external global routing solutions into the software to execute detailed routing. Blast Fusion from Magma supports loading global routing results using M-Tcl by users, but the procedure is error-prone. We finally use the tools from a startup Nimbus 1. The tools support loading external global routing solutions and design rules in 45nm technology node and beyond. The final DR results are checked by the design rule checker also from Nimbus. The major commands for the flow of loading global routing solution file, executing detailed routing and design rule checking in Nimbus tools are: loadgrsolution $design $gr file; routetrack $design -thread 8; routeconstruct $design; checkdrc $design; reportdrc $design. The benchmarks used in our experiments are generated from DAC 2012 routability-driven placement benchmark suite which contains several challenges in modern technology [21]. The designs in benchmarks use three kinds ofmetallayers, 1Xfor Metal1 Metal4, 2X for Metal5 Metal7, and 4X for Metal8 and Metal9. The placement solutions for these designs are produced by placers in DAC 2012 routability-driven placement contest [21]. These benchmarks are modified to facilitate detailed routing. We writeaconverterinc++totransformfiles in DAC 2012 benchmark format to LEF/DEF files. The benchmark files are read into the converter first, and then dimensions are adjusted. The gcell size is changed to 9 9 (9 is the placement row site height, in unit of 1 pitch) from One unit in placement image is mapped to one pitch (i.e., 140nm in 45nm technology node) on Metal1. 45nm design rules are added to the designs. The design rules include minimum 1 Nimbus Automation Technologies. Mar

10 Zhong-Dong Qi et al.: Congestion Model in Global Routing 623 width, width-length-dependent spacing, minimum enclosed area, end-of-line spacing, etc. Pin figures and routing blockages inside standard cells and macros are created. Pins of fixed macros are promoted to M4 from M1 to avoid being covered by routing blockages of the macros. At last, an LEF file containing technology rules and cell library, and a DEF file containing placement rows, routing tracks, placed cells, design pins and nets information are dumped from the converter. The process of modifying DAC 2012 benchmarks is similar in spirit to how DAC 2012 benchmarks were converted to ISPD 2014 detailed-routing-driven placement benchmark suite B by Liu et al. [22] The LEF/DEF files are further transformed to OpenAccess databases, which can be loaded into tools from Nimbus. The characteristics of these benchmarks are listed in Table 2. GCell Grid is the row and column count of gcell grid. Nets is the total net number. Layers denotes the number of metal layers. Table 2. Modified DAC 2012 Benchmark Suite Characteristics Circuit GCell Grid Nets Layers superblue superblue superblue superblue superblue superblue superblue superblue superblue Effectiveness of Proposed Model We run flow A and flow B to show the impact of different congestion models on global routing and detailed routing. In flow A, global routing uses the congestion model with pin blockage factor [8]. The pin blockage factor is set to 0.05 for both BFG-R and NCTU-GR, according to the paper proposing pin blockage factor model [8]. In flow B, the 3D global routing results are projected to 2D and new 3D routing solutions are obtained by layer assignment using the proposed congestion model. Specifically, in flow B, two resource modeling approaches of local pin access paths presented in Subsection are used. We denote the one using modeling approach 1 as flow B1, while the one using modelingapproach2asflowb2; flowb consistsofflows B1 and B2. In the regression approach of local pin access paths in flow B2, the design superblue12 is chosen to form the input data points and to construct the regression. Because it has the biggest number of gcells in standard cell region, which covers a lot of different situations of pins in gcells. Then the constructed regression expression is used in remaining eight designs as well as superblue12 itself. Table 3 and Table 4 show the layer assignment results in different flows using two global routers solutions, respectively. E-OF represents the number of overflowed edges, while N-OF represents the number of nodes with pass-through overflow. WL is routed wirelength, which is in unit of nm. Vias is total via count in unit of CPU denotes runtime in unit of minutes. The leftmost layer assignment procedure in each table is the one in global router BFG- R and NCTU-GR of flow A, respectively. The layer assignment algorithms in the two global routers comprise of net ordering and sequential single net layer assignment [2,19], which can be compared to the layer assignment in flow B. Note that in the experiments, the layer assignment algorithm in NCTU-GR is set to dynamic programming based method, which is the default setting in the parameter file. Pass-through overflow in layer assignment results of flow A is also listed, by additionally reading the layer assignment results and updating a clean congestion map using the proposed congestion model. From these two tables, we can see that layer assignment in flow B produces much smaller pass-through overflow while maintaining identical edge overflow compared with the one in flow A. The via number in layer assignment results of flow B is 3% more than the one in flow A. The reason is that some wire segments are assigned to higher layers to avoid pass-through overflow in lower layers. A large portion of resources on lower layers are consumed by local pin access paths and vias, thus some nets have to jump to higher layers, which leads to the increase of via count. The total wirelength of wire segments maintains the same after the layer assignment in flow B, since the layer assignment procedure only changes the layer of segments. Layer assignment in flow B is slower than the one in flow A, mainly due to extra updating of pass-through demand. Table 5 and Table 6 list the detailed routing results in different flows using BFG-R and NCTU-GR solutions, respectively. DRC is the total number of design rule violations (including spacing, short, and other design rule violations), in unit of The other no-

11 624 J. Comput. Sci. & Technol., May 2015, Vol.30, No.3 Table 3. Layer Assignment Results in Different Flows Using BFG-R Solutions Testcase BFG-R Layer Assignment in Flow A Layer Assignment in Flow B1 Layer Assignment in Flow B2 E-OF N-OF WL Vias CPU E-OF N-OF WL Vias CPU E-OF N-OF WL Vias CPU superblue superblue superblue superblue superblue superblue superblue superblue superblue Comparison Note: comparison: results normalized to those of BFG-R layer assignment in flow A. Table 4. Layer Assignment Results in Different Flows Using NCTU-GR Solutions Testcase NCTU-GR Layer Assignment in Flow A Layer Assignment in Flow B1 Layer Assignment in Flow B2 E-OF N-OF WL Vias CPU E-OF N-OF WL Vias CPU E-OF N-OF WL Vias CPU superblue superblue superblue superblue superblue superblue superblue superblue superblue Comparison Note: comparison: results normalized to those of NCTU-GR layer assignment in flow A. Table 5. Detailed Routing Results in Different Flows Using BFG-R Solutions Testcase DR in Flow A DR in Flow B1 DR in Flow B2 DRC WL Vias CPU DRC WL Vias CPU DRC WL Vias CPU superblue superblue superblue superblue superblue superblue superblue superblue superblue Comparison Note: comparison: results normalized to those of DR in flow A. tations follow the ones used in Table 3 and Table 4. We can see that detailed routing in flow B (B1 and B2) reduces runtime by over 44%, and produces over 38% less design rule violations compared with the one in flow A. This indicates that the proposed congestion model using both edge and pass-through demand captures detailed routing congestion more accurately than the pin factor model. The global routing paths produced by proposed model can guide the detailed router to find paths with less design rule violations. This helps reducing the amount of ripping-up and rerouting in detailed routing, which is performed on dense routing grid and is very time-consuming. Detailed routing wirelength and via count in flow

12 Zhong-Dong Qi et al.: Congestion Model in Global Routing 625 Table 6. Detailed Routing Results in Different Flows Using NCTU-GR Solutions Testcase DR in Flow A DR in Flow B1 DR in Flow B2 DRC WL Vias CPU DRC WL Vias CPU DRC WL Vias CPU superblue superblue superblue superblue superblue superblue superblue superblue superblue Comparison Note: comparison: results normalized to those of DR in flow A. B are both 2% 3% less than those in flow A. This is because that some global routes produced by layer assignment using the congestion model adopted in flow A would be infeasible during detailed routing, and the detailed router needs a lot of ripping-up and rerouting to find the feasible detailed path on dense routing grid. Since detailed routing is performed net-by-net sequentiallyinasmallregion,itlacksaglobalviewofavailable routing resources. Therefore, these rerouted paths generally have more vias and longer wirelength than global paths. As a result, guided by infeasible global routing paths, more detours and layer jumps would be created in interconnections in detailed routing, compared with the one with proper global paths. One may argue that 3D detailed routing can mitigate the issue. But it does not help, since cross-points on gcell boundaries are fixed during early iterations of ripping-up and rerouting in detailed routing, which restricts the path searching and causes layer jump and detours. Comparing the results of flow B1 and flow B2, layer assignment in flow B2 produces a little more vias than that in flow B1. This is due to more resources consumed by local pin access paths in lower metal layers bymodelingapproach2, whichforcessomenetstogoto higher layers. However, using global routes generated in flow B2, detailed router produces 6% 7% fewer design rule violations, and consumes shorter runtime than that in flow B1. This indicates that modeling approach 2 correlates better with the resource consumption of local pin access paths in detailed routing. And observed from the design rule checking report, the major difference of design rule violations in results of B1 and B2 is that the violations on M2, M3 and M4 of B2 results are reduced. The reason is that modeling approach 2 of local pin access paths resource has captured factors of pin size and pin distribution to make it more accurate. Reduction of violations on M4 indicates that pin access paths also contribute resource consumption in layers other than M2 and M3. To further show the effectiveness of reducing DRC violations by the proposed congestion model, we list different types of violations in flows using BFG-R and NCTU-GR results, in Table 7 and Table 8, respectively. The design rule checker reports over ten types of design rule checking violations (layout versus schematic violations, e.g., open and short, are also included). These different design rule types include different-net spacing, short, open, minimum area, notch spacing, minimum step, diagonal width, loop, minimum enclosed area, etc. The major ones are selected and shown in the tables. In Table 7 and Table 8, the number of violations from different design rules is shown, in unit of Space, Short, Open, Area, Notch are different-net spacing violations count, short violations count, open violation count, minimum area violation count, and notch spacing violation count, respectively. Among them, different-net spacing includes width-length-dependent spacing, end-of-line spacing, etc. Notch spacing violations are caused by geometries of the same net, typically forming a notch in shape. In the following, different-net spacing and notch spacing are respectively denoted as spacing and notch. From these two tables, we can see that differentnet spacing and short are the main parts of design rule violations. Using the proposed congestion model in flow B, spacing violations can be reduced by 37% 51% compared with flow A, which indicates that width-lengthdependent spacing and end-of-line spacing modeling is effective. Short and open violations are reduced by at least 39% in flow B. This is due to the practical modeling

13 626 J. Comput. Sci. & Technol., May 2015, Vol.30, No.3 Table 7. Design Rule Checking Results in Different Flows Using BFG-R Solutions Testcase DRC in Flow A DRC in Flow B1 DRC in Flow B2 Space Short Open Area Notch Space Short Open Area Notch Space Short Open Area Notch superblue superblue superblue superblue superblue superblue superblue superblue superblue Comparison Note: comparison: results normalized to those of DRC in flow A. Table 8. Design Rule Checking Results in Different Flows Using NCTU-GR Solutions Testcase DRC in Flow A DRC in Flow B1 DRC in Flow B2 Space Short Open Area Notch Space Short Open Area Notch Space Short Open Area Notch superblue superblue superblue superblue superblue superblue superblue superblue superblue Comparison Note: comparison: results normalized to those of DRC in flow A. resources consumed by vias and local pin access paths. If the resources consumed by vias and local pin access paths are ignored or underestimated, the vias and pin access paths would cause shorts and opens during detailed routing due to the lack of available resources. This reason also applies to the reduction of spacing violations. The reduction of spacing, short and open violations in flow B2 is greater than that in flow B1, which indicates that resource modeling approach 2 for pin access paths is more accurate than approach 1. Minimum area violations are reduced greatly in flow B comparedwiththeonesinflowa. Thisdemonstrates the effectiveness of via modeling considering the minimum area rule. In results of flow B, notch violations are reduced by 13% 25% compared with those in flow A. Although the notch is not explicitly modeled in the proposed congestion model, practical measurement of major design rules and routing path objects (including vias and local pin access paths) gives more space to prevent or to repair notch violations. Because in detailed routing, notches are generally caused by the lack of routing resources in a local region. The pin blockage factor is set to 0.05 in global routing of above routing flows, according to the paper proposing pin blockage factor model [8], in which pin blockage factor is tuned to 0.05 for 65nm and 45nm designs, and for 32nm designs. To investigate the impact of different pin blockage factors on global and detailed routing results, we run another routing flow using solutions of NCTU-GR with pin blockage factor set to 0.2. The results are shown in Table 9. The notations in the table have the same meanings and units as those in Table 4 and Table 6. Compared with corresponding results in Table 4 and Table 6, setting pin blockage factor to 0.2 leads to a smaller number of DRC violations. This may be due to the difference between technology design rules (and cell libraries) used in experiment de-

14 Zhong-Dong Qi et al.: Congestion Model in Global Routing 627 signs of [8] and those used in our experiment designs. It is difficult and time-consuming to find the best pin factor for given designs with a set of technology design rules, which needs iterative tuning and running routing flow. This is a possible limitation of the pin blockage factor model. It is also interesting to see that detailed routing results using NCTU-GR solutions have much smaller number of DRC violations than those using BFG-R solutions, fromtable5andtable6. Theremaybefactors other than congestion model affecting detailed routing solution quality in global routing. Table 9. Routing Results with NCTU-GR (Pin Factor 0.2) Circuit GR DR WL Vias DRC WL Vias superblue superblue superblue superblue superblue superblue superblue superblue superblue Table 10. Routing Results of Nimbus Routing Tools Circuit GR DR WL Vias DRC WL Vias superblue superblue superblue superblue superblue superblue superblue superblue superblue In above results, the DRC violation numbers are relatively large. There are several reasons. First, because exhaustive search and repair of DRC violations using ripping-up and rerouting (RNR) takes too long time, the detailed router is not set to the highest effort to save experiment time. Using some iterations of RNR, the detailed router produces solutions showing the detailed routing congestion. If more iterations of RNR are performed, the DRC violation number would be further decreased. Second, the global routing results used in above routing flows would lead to inevitable DRC violations in some regions. As shown in Table 3 and Table 4, there is remaining pass-through overflow measured by the proposed congestion model. Third, for current placement used in experiments and given technology design rules, routing resources in some regions are not sufficient for DRC-violation-free detailed routing solution. The DRC violation number would be smaller when using better routability-driven placement results (e.g., placement solutions produced by a commercial placer). For reference, we also list results of detailed routing using global routing solutions of Nimbus routing tools in Table 10. The settings of the detailed router are the same as those used in previous routing flows in this subsection. We can see that the detailed routing solutions have better quality compared with detailed routing solutions in Table 5 and Table 6. This implies that there is still room for improvement in academic global routers. 6 Conclusions In this paper, we presented a practical congestion model in global routing, to more accurately reflect modern design rule requirements. Intra-gcell congestion is measured using a concept of pass-through capacity and demand. Congestion contributors including vias, local pin access paths and related design rules are modeled. Validated by full-flow routing, this congestion model correlates better with real resource consumption situation in detailed routing. It leads to better solution quality and shorter runtime in detailed routing stage when used in global routing stage, compared with a previous congestion model. This model can also be used in global routing based congestion estimation during routability driven placement. References [1] Albrecht C. Global routing by new approximation algorithms for multicommodity flow. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001, 20(5): [2] Roy J A, Markov I L. High-performance routing at the nanometer scale. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, 27(6): [3] Pan M, Xu Y, Zhang Y, Chu C. FastRoute: An efficient and high-quality global router. VLSI Design, 2012, 2012: Article ID [4] Moffitt M D. MaizeRouter: Engineering an effective global router. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, 27(11):

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