Prerequisites for Rou4ng

Transcription

1 Basic Zroute Flow

2 Prerequisites for Rou4ng Library requirements Zroute gets all of the design rule informa4on from the technology file; therefore, you must ensure that all design rules are defined in the technology file before you start rou4ng. Design requirements Before you perform rou4ng, your design must meet the following condi4ons: Power and ground nets have been routed acer design planning and before placement. Clock tree synthesis and op4miza4on have been performed. Es4mated conges4on is acceptable. Es4mated 4ming is acceptable (about 0 ns of slack). Es4mated maximum capacitance and transi4on have no viola4ons.

3 Checking Routability ACer placement is completed, you can use the check_zrt_routability command (or choose Route > Check Routability in the GUI) to check whether your design is ready for detail rou4ng. By default, this command checks for Blocked standard cell ports A standard cell port is considered blocked if none of its physical pins is accessible. Blocked top-level or macro cell ports A top-level or macro cell port is considered blocked if none of its physical pins is accessible. Out-of-boundary pins This check verifies that all pins are within the design boundary. Minimum grid viola4ons This check verifies that all pins, including those within library cells, are on the minimum grid, as defined by the gridresolu4on avribute in the technology file.

4 Rou4ng Corridors A rou4ng corridor restricts Zroute global rou4ng for specific nets to the region defined by a set of connected rectangles. In addi4on to specifying the region in which the rou4ng occurs, you can also specify the minimum and maximum rou4ng layers for each of the rectangles that comprise the rou4ng corridor. Rou4ng corridors are intended to be used to route cri4cal nets before signal rou4ng. For example, Figure shows a rou4ng corridor named corridor_1, which is made up of six rectangles. This rou4ng corridor is associated with the nets shown in yellow. The figure on the lec shows the nets before rou4ng, while the figure on the right shows the nets routed within the rou4ng corridor.

5 Global Rou4ng The global router divides a design into global rou4ng cells. By default, the width of a global rou4ng cell is the same as the height of a standard cell and is aligned with the standard cell rows. For each global rou4ng cell, the rou4ng capacity is calculated according to the blockages, pins, and rou4ng tracks inside the cell. Although the nets are not assigned to the actual wire tracks during global rou4ng, the number of nets assigned to each global rou4ng cell is noted. The tool calculates the demand for wire tracks in each global rou4ng cell and reports the overflows, which are the number of wire tracks that are s4ll needed acer the tool assigns nets to the available wire tracks in a global rou4ng cell. Global rou4ng is done in two phases: The ini4al rou4ng phase (phase 0), in which the tool routes the unconnected nets and calculates the overflow for each global rou4ng cell The rerou4ng phases, in which the tool tries to reduce conges4on by ripping up and rerou4ng nets around global rou4ng cells with overflows

6 Global Rou4ng Before proceeding to detail rou4ng, display the conges4on map in the GUI, and check the overflow distribu4on. The conges4on report and map help you to iden4fy congested areas.

7 Track Assignment The main task of track assignment is to assign rou4ng tracks for each global route. During track assignment, Zroute performs the following tasks: Assigns tracks in horizontal par44ons. Assigns tracks in ver4cal par44ons. Reroutes overlapping wires. ACer track assignment finishes, all nets are routed but not very carefully. There are many viola4ons, par4cularly where the rou4ng connects to pins. Detail rou4ng works to correct those viola4ons.

8 Track Assignment At the end of track assignment, Zroute reports a summary of the wire length and via count. ACer track assignment, you can display a conges4on report and map that are based on the track assignment results.

9 Detail Rou4ng The detail router uses the general pathways suggested by global rou4ng and track assignment to route the nets, and then it divides the design into par44ons and looks for DRC viola4ons in each par44on. When the detail router finds a viola4on, it rips up the wire and reroutes it to fix the viola4on. During detail rou4ng, Zroute concurrently addresses rou4ng design rules and antenna rules and op4mizes via count and wire length

10 Detail Rou4ng ACer detail rou4ng, you can display a conges4on report and map that are based on the detail rou4ng results.

11 Analyzing Conges4on In the default conges4on report, H rou4ng refers to results for horizontal routes only and V rou4ng refers to results for ver4cal routes only. The Overflow value is the total number of wires in the design that do not have a corresponding track available. The Max value corresponds to the highest number of overu4lized wires in a single global rou4ng cell. The GRCs value is the total number of overcongested global rou4ng cells in the design.

12 Conges4on Map

13 Conges4on Map If the design shows congested areas, zoom into the congested area to see the conges4on value on the global rou4ng cell. For example, in Figure 6-9, the red highlight on the edge of the global rou4ng cell shows 18/9. This means there are 9 wire tracks available, but 18 tracks are needed.

14 Chip Finishing

15 Tap Cells Tap cells are a special nonlogic cell with well and substrate 4es. These cells are typically used when most or all of the standard cells in the library contain no substrate or well taps. Generally, the design rules specify the maximum distance allowed between every transistor in a standard cell and a well or the substrate 4es. You can insert tap cells in your design before or acer placement: You can insert tap cell arrays before placement to ensure that the placement complies with the maximum diffusion-to-tap limit. You can insert tap cells acer placement to fix maximum diffusion-to-tap viola4ons.

16 Antenna Viola4ons In chip manufacturing, gate oxide can be easily damaged by electrosta4c discharge. The sta4c charge that is collected on wires during the mul4level metalliza4on process can damage the device or lead to a total chip failure. The phenomenon of an electrosta4c charge being discharged into the device is referred to as either antenna or charge-collec4ng antenna problems. To prevent antenna problems, the tool verifies that for each input pin the metal antenna area divided by the gate area is less than the maximum antenna ra4o given by the foundry: (antenna-area)/(gate-area) < (max-antenna-ra4o) The antenna flow consists of the following steps: 1. Define the antenna rules 2. Specify the antenna proper4es of the pins and ports 3. Analyze and fix the antenna viola4ons

17 Filler Cells Filler cells fill gaps in the design to ensure that all power nets are connected and the spacing requirements are met. Before rou4ng, you can - Insert standard-cell fillers - Insert end cap cells ACer rou4ng, you can - Insert well fillers - Insert pad fillers

18 Filler Cells You can fill empty spaces in the standard-cell rows with instances of reference filler cells to make sure all power nets are connected. One method of improving the stability of the power supply is to add decoupling capacitors as filler cells.

19 Metal Fill ACer rou4ng, you can fill the empty spaces in the design with metal wires to meet the metal density rules required by most fabrica4on processes. Before inser4ng metal fill, the design should be close to mee4ng 4ming and have only a very few or no DRC viola4ons. An IC Validator license is required to run the signoff_metal_fill command.

20 RTL Synthesis Flow

21 P&R Flow

22 Chip Layout

23 Timing Driven Placement The trouble with a place-then-route strategy is that acer the layout is completed, the parasi4c rou4ng capacitance is extracted and the 4ming analysis is done to es4mate 4ming. The 4ming is not known un4l the physical layout is complete. If 4ming problems are found, the cycle has to be repeated with some kind of constraint placed on the problema4c paths. Cells on cri4cal paths are given priority to minimize wire delay. finished

24 Mixed Signal Flow