Interprocess Communication

Transcription

1 VLSI Systems Design Connection and Communication Models Goal: You can make the link between the low level connection architectures and the higher level communication models and master their implementation. You are familiar with the most common buses and networks. Interprocess Communication multitasking systems need mechanisms for communication between tasks real-time operating systems (RTOS) provide interprocess communication mechanisms in embedded systems definition of process element (PE): a piece of software running on an embedded processor a hardware unit executing an algorithm implemented for example as a FSM-D D architecture model interprocess communication is information exchange between processing elements MicroLab, VLSI-31 (1/61) MicroLab, VLSI-31 (2/61) page 1

2 Blocking/Non-Blocking Communication We distinguish between blocking and non-blocking communication: blocking communication: the process element initiating the communication goes in a waiting state until communication end. non-blocking communication: the process element initiating the communication can execute other useful tasks during an ongoing communication. both types of communication are useful. Shared Memory Communication: test-and and-set operation two major (logically equivalent) communication styles exist: shared memory message passing shared memory communication between processing elements using bus a structure message is stored in communication link PE1 shared location PE2 Memory write read MicroLab, VLSI-31 (3/61) need of atomic test-and and-set operations, else: PE 1 reads flag location and sees not busy PE2 reads flag location and sees no busy PE1 sets flag location to busy writing and writes to the shared location PE2 erroneously sets flag busy writing and overwrites the left by PE1 MicroLab, VLSI-31 (4/61) page 2

3 Shared Memory Communication: Semaphores a semaphore is a language level synchronization element with semaphores guarded access to shared memory can be realized: wait for semaphore: P(); P() uses a test-and and-set operation to repeatedly test a location that holds a memory lock release semaphore: V(); V() resets the memory lock Message Passing Communication each communication entity has its own send/receive unit message is stored on endpoints of send/receive unit and not in communication link as at shared memory communication message passing is used at applications where units operate relatively autonomous: ex. car control system... /* non-protected memory access is here */ P(); /* wait for semaphore */ /* do protected memory access here */ V(); /* release semaphore */ /* non-protected memory access is here */ PE1 send/receive message PE2 send/receive... MicroLab, VLSI-31 (5/61) MicroLab, VLSI-31 (6/61) page 3

4 Signals Data Dependencies major interprocess communication mechanisms: shared memory message passing simple interprocess communication mechanism: signal a signal does not pass beyond its existence a signal is analogous to hardware interrupt, but can entirely be implemented in software a signal is generated by a process and transmitted to another process by the operating system signal have fairly limited functionality: CPU exceptions to operating system operating system services termination of a process PE1 OS/PE2 signal send receive communication processes that execute exchange at identical rates: relationship shown using dependencies dependencies define a partial ordering of process execution directed acyclic graph (DAG): task graph P1 P3 P4 P2 communication processes that execute exchange at different rates: no one-to to-one one relation between source and destination of video system audio MicroLab, VLSI-31 (7/61) MicroLab, VLSI-31 (8/61) page 4

5 Deadlocks The Four-Cycle Cycle-Handshake US Kansas legislature law early last century: When two trains approach each other at a crossing, both shall come to a full stop and neither shall start up again until the other has gone. Dealing with deadlock problem: ignoring (very popular) detection and recovering (quite popular) preventing avoiding (not applicable) R 1 R 3 the four-cycle cycle-handshake ensures a correct communication between two devices predefined master/slave devices device 1 is master and initiates communication device 2 is slave send or receive is possible bus is bidirectional device 1 (master) req ack rw device 2 (slave) P 1 P 2 P 3 R 2 MicroLab, VLSI-31 (9/61) MicroLab, VLSI-31 (10/61) page 5

6 device 1 device 2 The Four-Cycle Cycle-Handshake: predefined master/slave four-cycle cycle-handshake for sending: rw req ack valid request phase store phase stored acknowledge phase end phase four-cycle cycle-handshake for receiving: rw Bus Allocation complex SoC may have sharable resources: memories processing elements I/O devices buses bus allocation principles: allocation on a fixed time schedule bus allocation on the basis of need destructive bus allocation (Ethernet: Carrier Sense Multiple Access with Collision Detection CSMD/CD,...) non-destructive bus allocation (arbitration) device 1 req stored device 2 ack valid request phase achnowledge phase store phase end phase MicroLab, VLSI-31 (11/61) MicroLab, VLSI-31 (12/61) page 6

7 Bus Arbitration Algorithms arbitration is the method to grant the bus to a requesting master arbitration schemas: fixed priority (or rate-monotonic) algorithm round robin algorithm Typical Processor Bus a bus is a collection of wires as well as a protocol microprocessor buses build on handshake protocol basic bus operations are reading and writing system clock helps to increase transfer speed device 1 device 2 top priority processing element (CPU) clock r/w addr en addr rdy priorities clock A B C D E F G H r/w wait state addr en priorities A B C D E F G H addr rdy addr valid addr valid valid valid MicroLab, VLSI-31 (13/61) read write MicroLab, VLSI-31 (14/61) page 7

8 Bus With DMA Controller direct memory access (DMA) controllers perform direct transfers between devices without CPU involvement four-cycle cycle-handshake with processor to get bus master (interrupt processor when finished) used for high speed requirements to prevent to block the processor too long, partial block transfer mode possible, 16, 32 or 256 words for example. bus DMA controller is a bus with 2 masters processing element (CPU) bus request bus grant DMA controller device 1 clock r/w addr en addr rdy System Bus embedded systems-on on-chip use bus hierarchies: Avalon from Altera Inc., used for Nios (simple) AMBA TM bus from AMD Inc., used for ARM TM CoreConnect TM from IBM Inc., used for PowerPC TM features: high-speed buses provide wider connections high-speed buses require more expensive circuitry and connectors. The cost of low-speed devices can be held down by using lower-speed, lower-cost bus. The bridge may allow the buses to operate independently, thereby providing some parallelism in processing an I/O operations. bus bridge: slave at fast bus, master at slow bus high-speed bus CPU bridge low-speed I/O device low-speed bus device 2 memory high-speed processing element low-speed processing element MicroLab, VLSI-31 (15/61) MicroLab, VLSI-31 (16/61) page 8

9 The AMBA System Bus advanced high-performance bus (AHB) high-performance pipelined operation multiple bus master burst transfer split transactions advanced high-performance system bus (ASB) dito,, but no split transactions advanced peripheral bus (APB) external memory interface (highbandwidth) low-power latched address and control simple interface suitable for many peripherals DMA on-chip RAM (highbandwidth) AHB or ASB CPU processing element (high-speed) bridge PIO UART APB MicroLab, VLSI-31 (17/61) Keypad Timer Advanced High-Performance Bus (AHB) The AHB bus consists of the following elements: AHB master: able to initiate read and write transfers only one bus master is allowed to control the bus AHB slave: responds to read and write operations in a given address space signals back to the master: success, failure or waiting of the transfer AHB arbiter: ensures that only one master at a time is allowed to control bus any arbitration algorithm can be used, like highest priority, fair access, etc AHB decoder: decodes address and generates device select signals single centralized decoder is required MicroLab, VLSI-31 (18/61) page 9

10 Basic AHB Interconnection Schema arbiter determines bus master central multiplexor schema central decoder for read additional characteristics: single cycle bus master handover single clock edge operation non-tristate implementation wider bus configuration (64/128 bits) Phases: Basic AHB Transfer address & control phase one or more phase Slave can delay transfer with HREADY address source is master: HADDR[31:0] source for write operations is master: HWDATA[31:0] source for read operations is slave: HRDATA[31:0] master # 1 master # 2 master # 3 HADDR HWDATA HRDATA HADDR HWDATA HRDATA HADDR HWDATA HRDATA arbiter HADDR HWDATA HRDATA HADDR HWDATA HRDATA HADDR HWDATA HRDATA HADDR HWDATA HRDATA slave # 1 slave # 2 slave # 3 slave # 4 HCLK HADDR[31:0] control HWDATA[31:0] HREADY addr phase (A) phase (A) A B C D ctrl A ctrl B ctrl C ctrl D A B C decoder HRDATA[31:0] A B C MicroLab, VLSI-31 (19/61) MicroLab, VLSI-31 (20/61) page 10

11 AHB Transfer Example Master shows transfer type with HTRANS[1:0] IDLE ( 00 ): no transfer is required BUSY ( 01 ): master is delaying an ongoing transfer NONSEQUENTIAL ( 10 ): first transfer of a burst or single transfer SEQ ( 11 ): remaining transfers of a burst Delaying transfer master delays transfer with HTRANS[1:0] slave delays transfer with HREADY incremental burst of unspecified length is shown AHB Transfer Example (4-beat wrapping burst) Master defines bus operation with HBURST[2:0] SINGLE ( 000 ): single transfer INCR ( 001 ): increment burst of unspecified length WRAP4 ( 010 ): 4-beat 4 wrapping burst INCR4 ( 011 ): 4-beat 4 incrementing burst WRAP8 ( 100 ): 8-beat 8 wrapping burst INCR8 ( 101 ): 8-beat 8 incrementing burst WRAP16 ( 110 ): 16-beat wrapping burst INCR16 ( 111 ): 16-beat incrementing burst Burst must not cross 1kB address boundary HCLK C1 C2 C3 C4 C5 C6 C7 C8 HCLK HTRANS[1:0] NONSEQ SEQ NONSEQ SEQ SEQ SEQ HTRANS[1:0] NONSEQ BUSY SEQ SEQ SEQ SEQ HADDR[31:0] 0x70 0x72 0x38 0x3C 0x30 0x34 HADDR[31:0] 0x20 0x24 0x24 0x28 0x2C 0x30 HBURST[2:0] INCR WRAP4 HBURST[2:0] HWDATA[31:0] INCR 0x20 0x24 0x28 0x2C 0x30 HWRITE HSIZE[2:0] HPROT[3:0] SIZE=halfword control for burst, SIZE=word HREADY HWDATA[31:0] 0x70 0x72 0x38 0x3C 0x30 0x34 HRDATA[31:0] 0x20 0x24 0x28 0x2C 0x30 HREADY HRDATA[31:0] 0x70 0x72 0x38 0x3C 0x30 0x34 MicroLab, VLSI-31 (21/61) MicroLab, VLSI-31 (22/61) page 11

12 AHB Transfer Example with Response slave can complete a transfer in a number of ways: complete the transfer immediately insert wait states signal an error to indicate transfer has failed delay the completion of the transfer, but allow master/slave to back off bus slave shows status of transfer with HRESP[1:0] in combination with HREADY OKAY: transfer is progressing normally ERROR: transfer has been unsuccessful RETRY and SPLIT: both indicate that transfer cannot complete immediately ERROR, RETRY and SPLIT are at least two-cycles AHB Bus Arbitration signals for bus arbitration: HBUSREQx: : master sends bus request HGRANTx: : arbiter issues bus grant HMASTER[3:0]: arbiter issues bus master number HLOCKx: : master may request bus lock HMASTLOCKx: : arbiter issues bus lock grant signal arbiter can terminate non size-limited bursts early master can require locked access if a master looses bus access in the middle of a burst it must re-assert HBUSREQx to regain access C1 C2 C3 C4 C5 C6 C7 C8 HCLK HBUSREQ_M1 HCLK C1 C2 C3 C4 C5 C6 C7 C8 HBUSREQ_M2 HGRANT_M1 HTRANS[1:0] NONSEQ SEQ IDLE NONSEQ SEQ IDLE NONSEQ HGRANT_M2 HADDR[31:0] A A+4 B B+4 B HMASTER[3:0] Mx M1 M2 HWDATA[31:0] A B HTRANS[1:0] IDLE IDLE NONSEQ SEQ SEQ SEQ NONSEQ HREADY HADDR[31:0] A A+4 A+8 A+12 B HRESP[1:0] OKAY ERROR ERROR OKAY RETRY RETRY HWDATA[31:0] A A+4 A+8 A+12 HREADY MicroLab, VLSI-31 (23/61) MicroLab, VLSI-31 (24/61) page 12

13 AHB Address Decoder Schematic slaves sample HSELx when HREADY is active minimum address space allocated to a slave is 1kB if system does not contain complete memory map, default slave (decoder) should respond to wrong addresses access attempt to nonexistent location will be answered by default slave: ERROR response to NONSEQUENTIAL or SEQUENTIAL zero wait state OKAY response to IDLE or BUSY Master determines transfer size with HSIZE[2:0] 000 : size is byte 001 : size is half-word 010 : size is word : size is 32 bytes master # 1 HADDR_M1[31:0] master # 2 HADDR_M2[31:0] HADDR decoder HSEL_S1 HSEL_S2 HSEL_S3 MicroLab, VLSI-31 (25/61) slave # 1 slave # 2 slave # 3 address select address and control reset clock arbiter grant transfer response reset clock arbiter requests and locks address and control reset clock AHB Interface Diagrams HRDATA[31:0] HSELx HADDR[31:0] HWRITE HTRANS[1:0] HSIZE[2:0] HBURST[2:0] HWDATA[31:0] HRESETn HCLK HMASTER[3:0] HMASTLOCK HGRANTx HREADY HRESP[1:0] HRDATA[31:0] HRESETn HCLK HBUSREQx1 HLOCKx1 HBUSREQx2 HLOCKx2 HADDR[31:0] HSPLITx[15:0] HTRANS[1:0] HBURST[2:0] HRESP[1:0] HREADY HRESTEn HCLK AHB decoder AHB slave split-capable slave AHB master AHB arbiter HSELx1 HSELx2 HREADY HRESP[1:0] HRDATA[31:0] HSPLIT[15:0] HBUSREQx HLOCKx HTRANS[1:0] HADDR[31:0] HWRITE HSIZE[2:0] HBURST[2:0] HPROT[3:0] HWDATA[31:0] HGRANTx1 HGRANTx2 HMASTER[3:0] HMASTLOCK MicroLab, VLSI-31 (26/61) select transfer response arbiter transfer type address and control arbiter grants page 13

14 AHB-Lite AHB-Lite is a subset of full AHB specifications only one bus master thus no request/grant protocol for arbiter thus no split or retry response from slaves AHB-Lite enables faster design and verification compatibility: full AHB master can be used in AHB-Lite system AHB slaves can be used in AHB-Lite system, if they do not support split and retry AHB-Lite slaves can be used in full AHB system slave #1 Advanced Peripheral Bus (APB) the APB is a low-power extension to the AHB/ASB APB appears as a local secondary bus encapsulated as a single AHB/ASB slave device APB bridge acts as slave and handles necessary handshake control and bus retiming APB bridge proves latching of all addresses, control and APB should be used to handle low-bandwidth devices APB slave devices have following characteristics: address and control valid throughout the access (non- pipelined) zero-power interface during non-peripheral bus activity timing can be provided by decode with strobe timing (un- clocked interface) write valid for the whole access (allowing glitch-free transparent latch implementation) master slave #2 slave #3 MicroLab, VLSI-31 (27/61) highbandwidth external memory interface DMA bus master highbandwidth on-chip RAM AHB or ASB CPU high-speed processing device bridge PIO Keypad APB UART Timer MicroLab, VLSI-31 (28/61) page 14

15 APB Basic Transfers APB Interface Diagrams write transfer PCLK PADDR[31:0] PWRITE C1 C2 C3 C4 addr A reset clock PRDATA[31:0] PRESETn PCLK APB bridge PSEL1 PSEL2 PENABLE PADDR[31:0] PWRITE PWDATA[31:0] selects strobe address & control write PSEL PENABLE PWDATA[31:0] read transfer A IDLE SETUP ENABLE IDLE recommended to implement APB bus as multiplexed or OR-bus schema tri-state is possible but not recommended C1 C2 C3 C4 PCLK PADDR[31:0] PWRITE PSEL addr A select strobe address & control PSELx PENABLE PADDR[31:0] PWRITE PWDATA[31:0] APB slave PENABLE PRDATA[31:0] PRDATA[31:0] read PRDATA[31:0] A IDLE SETUP ENABLE IDLE reset clock PRESETn PCLK MicroLab, VLSI-31 (29/61) MicroLab, VLSI-31 (30/61) page 15

16 Read Transfer from AHB to APB for a write transfer the can be latched when: risinf edge of PCLK, when PSEL is high rising edge of PEANBLE, when PSEL is high AMBA Test Interface AMBA test philosophy allows individual modules in the system to be tested in isolation modules are designed to be tested by bus transfers only test harness provides access to inputs/outputs of modules not already connected to bus HCLK &PCLK C1 C2 C3 C4 C5 C6 C7 C8 C8 dedicated module inputs application module dedicated module outputs HADDR[31:0] addr A addr A+4 addr A+8 addr A+12 addr A+12 HWRITE HRDATA[31:0] (A) (A+4) (A+8) (A+12) test stimuli bus interface test results HREADY AMBA bus PADDR[31:0] addr A addr A+4 addr A+8 addr A+12 PWRITE PSEL control address AMBA bus PENABLE PRDATA[31:0] (A) (A+4) (A+8) (A+12) Test Interface Controller (TIC) External Bus Interface (EIB) MicroLab, VLSI-31 (31/61) TCLK TREQA TREQB TACK TBUS[31:0] MicroLab, VLSI-31 (32/61) page 16

17 AMBA Test Interface Write Cycle test control signals during normal operation TREQA TREQB TACK description normal operation enter test mode request test mode entered test control signals during test mode TREQA TREQB TACK description current access incomplete address, control or turnaround vector write vector read vector exit test mode HCLK TREQA C1 C2 C3 C4 C5 C6 C7 C8 C9 Introduction to Networks motivation for distributed embedded systems: if processing tasks are physically distributed, processing power can be implemented there (eg ( eg.. automotive) reduction by signal pre-processing processing for reduction (eg ( eg: : finger print feature recognition) modularity by encapsulating processing operations and not using local system bus interprocess communication in SoC shared memory is often used in distributed system networks shared memory is not available TREQB TACK TBUS[31:0] HTRANS[31:0] addr write1 write2 write3 addr IDLE NONSEQ SEQ SEQ IDLE sensor/ actuator PE #1 32-bit RISC PE #2 32-bit RISC PE #3 HADDR[31:0] control HWDATE[31:0] A A+4 A+8 HBURST[2:0],HWRITE,HSIZE[2:0],HPROT[3:0] A A+4 A+8 sensor/ actuator PE #4 DSP PE #5 SoC PE #6 network HREADY MicroLab, VLSI-31 (33/61) MicroLab, VLSI-31 (34/61) page 17

18 Switching-Based Architectures crossbar: higher bandwidth compared to bus-based based architectures major drawback is its expense omega: PEout1 PEout2 PEout3 PEout4 PEin1 PEin2 PEin3 PEin4 crosspoint switch higher bandwidth compared to bus-based based architectures, but lower than crossbar more expense than bus, but less expensive than crossbar OSI Network Abstraction Model open system interconnection reference model (OSI) OSI defines communication formats, contents and meanings: connection-oriented oriented protocol: first connection is established and possibly protocol negotiated connectionless protocol: no setup necessary, message directly transmitted for modularization/encapsulation 7 layers are defined in OSI: machine #1 process A machine #2 process B 7 6 application presentation end-user interface format application presentation PEout1 PEin1 5 4 session transport application dialog format connections session transport PEout2 PEin2 3 network end-to-end service network PEout3 PEin3 2 1 link physical reliable transport mechanical, electrical link physical PEout4 2 x 2 switch PEin4 MicroLab, VLSI-31 (35/61) MicroLab, VLSI-31 (36/61) page 18

19 The OSI Layer Message link layer header link layer trailer network layer header transport layer header session layer header presentation layer header application layer header each layer has its own protocol that can be changed independently of the other ones technology improvement message bits that actually appear on the network this independence makes layer protocols attractive the collection of protocols in a particular system is called protocol stack MicroLab, VLSI-31 (37/61) The Physical Layer: The OSI Layers basic property of interface, mechanical, electrical and bit exchange procedure The Data Link Layer: primary purpose is error detection and correction group bits into frames, appends checksum The Network Layer: end-to to-end transmission by routing The Transport Layer: defines connection-oriented oriented services breaks message into packets, and guarantees delivery of whole message The Session Layer: enhanced version of transport layer adds checkpoints for crash handling The Presentation Layer: defines exchange formats The Application Layer: collection of miscellaneous protocols like , file transfer, etc MicroLab, VLSI-31 (38/61) page 19

20 The Client-Server Model protocol overhead in OSI might be to high for LAN: traversing half a dozen layers up and down (acceptable for WAN) client-server model structures the cooperating processes: server: processes who offer services to users client: processes who consumes services use of connectionless request/reply protocol primary advantage: simplicity: no connection has to be established, reply message serves as acknowledge efficiency: protocol stack is shorter, only 3 OSI levels are necessary layer 7 request 6 client server 5 request/reply µkernel reply 4 µkernel 3 network 2 link 1 physical MicroLab, VLSI-31 (39/61) Buffered vs. Un-Buffered Message Passing: Mailbox un-buffered message passing receive has to be issued before send primitive buffered message passing: mailbox serving processes install mailbox before using it client µkernel client µkernel address refers to a process network address refers to a mailbox network server addr µkernel server µkernel addr MicroLab, VLSI-31 (40/61) page 20

21 Reliable Message Passing different approaches to reliable message passing: assume the message passing is unreliable (e.g. post office) reliable message passing using separate acknowledgement (compare four cycle handshake) layer 1st request 7 6 client 3rd reply server 5 request/reply 2nd ACK 4 transport µkernel 4rd ACK µkernel 3 2 link network 1 physical reliable message passing using acknowledgment principle client 1st request 2rd reply/ack 3rd ACK server µkernel µkernel network The I2C Bus: Physical Layer popular for initialization & command word exchange between up and peripherals like MP3, AD, smart sensor, small EEPROM, etc serial bi-directional 2-wire 2 bus multi-master/slave master/slave operation open drain/open collector lines structure of an I2C bus system master #1 transmitter & receiver SCL SDA physical layer SCL SDA master #2 transmitter slave #1 transmitter & receiver I2C driver clock input assert clock input assert slave #2 receiver MicroLab, VLSI-31 (41/61) MicroLab, VLSI-31 (42/61) page 21

22 Level Shifter for I2C Bus (Physical Layer) due to chip technology scaling single supply voltage is rarely seen today networks connecting devices of different voltage sections thus need level shifters Multiple Level Shifter for I2C Bus (Physical Layer) multiple power supplies power down of supply sections possible modular and extendable VDD3 = max(vddi) VDD1=3.3V VDD2=5V VDD1=3.3V VDD2=5V SCL1 g s d d g s SCL2 SCL1 g s d SCL2 SDA1 g s d d g s SDA2 SDA1 g s d SDA2 3.3V I 2 C device 3.3V I 2 C device 5V I 2 C device 5V I 2 C device 3.3V I 2 C device 3.3V I 2 C device 5V I 2 C device 5V I 2 C device lower voltage section higher voltage section lower voltage section higher voltage section MicroLab, VLSI-31 (43/61) MicroLab, VLSI-31 (44/61) page 22

23 I2C Bus: Data Link Layer transmitting one byte (start) - byte - acknowledge (stop) I2C Bus: Data Link Layer Transfer Formats master write format (2 bytes) 7-bit slave address 0 can be repeated n times SCL Start addr Write Ack Ack Ack Stop SDA MSB start condition 8-bit byte ack stop condition master read format (2 bytes) 7-bit slave address 1 can be repeated n times Start addr Read Ack Ack NAck Stop SCL master SDA transmitter SDA receiver who activates the bus lines MSB transmitter stays off the bus during acknowledgement acknowledgement signal from receiver trasnsmitter takes bus ( or stop) 2 succeeding master write formats can be repeated n times Start addr Write Ack Ack Start addr Ack Stop no proceeding Stop condition MicroLab, VLSI-31 (45/61) MicroLab, VLSI-31 (46/61) page 23

24 The CAN Bus Control Area Network (CAN): ISO standard high-integrity integrity serial communications bus for real-time applications operates at rates of up to 1 Mbit/sec excellent error detection and confinement capabilities originally developed by Bosch for use in cars, now being used in many other industrial automation and control applications features: message prioritization guarantee of latency time error detection and signaling, automatic retransmission of corrupted messages multi-master master master #1 transmitter & receiver master #2 transmitter & receiver slave #1 transmitter & receiver slave #2 transmitter & receiver physical layer The CAN Bus OSI Layer Structure not defined in CAN protocol but in ISO link layer object layer transfer layer Application Layer Data Link Layer (Object Layer) -message filtering -message and status handling (Transfer Layer) -fault confinement -error detection and signaling -message validation -acknowledgement -arbitration -message framing -transfer rates and timing Physical Layer -signal level and bit representation - transmission medium MicroLab, VLSI-31 (47/61) MicroLab, VLSI-31 (48/61) page 24

25 CAN: Physical Layer application domain specific electrical characteristics voltage levels for automotive applications up to 36V wired-and logic on CAN bus lines separation between CAN controller an transceiver often seen CAN bus V diff C_H C_L bus termination CAN Network: Data Link Layer principles of exchange no nodes are addressed content-oriented oriented addressing schema: - identifier of message content (unique in network) - identifier defines priority V dd_n transceiver V dd_m transceiver 2-wire differential lines (up to 1 Mbaud) CAN node #1 (receiver) accept CAN node #2 (transceiver) prepare CAN node #3 (receiver) accept CAN node #4 (receiver) V gnd_n V gnd_m CAN controller node #n CAN controller node #m CAN bus V dd bus pull-up select receive message send message select receive message select receive message CAN bus single wire line (only 33.3 kbaud) CAN controller node #1 CAN controller node #2 MicroLab, VLSI-31 (49/61) MicroLab, VLSI-31 (50/61) page 25

26 CAN Network: Data Link Layer Bus Arbitration bus allocation: fast transmission asks for fast bus allocation non-destructive bitwise arbitration identifier defines arbitration priority wired-and priority: low value means high priority CSMA/AMP: Carrier Sense Multiple Access with Arbitration on Message Passing CAN bus node #1 node #2 node #3 CAN node #1 CAN bus CAN node #2 CAN node #3 interframe space CAN Network: Data Link Layer Message Frame Formats CAN supports two message frame formats: standard (CAN 2.0A): 11 bit identifier extended (CAN 2.0B): 29 bit identifier ( bit) to start arbitration field identifier RTR bit control field identifier extension r0 Standard Data Frame length code field RTR: remote transmission request r0: reserved CRC field CRC field CRC delimiter ack field ACK slot ACK delimiter end of frame inter frame space node #1 loses node #3 loses MicroLab, VLSI-31 (51/61) MicroLab, VLSI-31 (52/61) page 26

27 CAN Network: Data Link Layer Error Handling detecting and signaling errors: CRC: x 15 + x 14 + x 10 + x 8 + x 7 + x 4 + x 3 +1 frame check ACK check error detection at bit level: monitoring: each transmitter checks locally send signals bit stuffing: after 5 identical consecutive bits the sender adds one complementary bit which will be removed by the receivers (used for bit synchronization) error handling: if error is detected, the current transmission is aborted by sending an error flag sender automatically re-attempts transmission CAN distinguishes between sporadic and permanent errors and thus localizing node failures (statistical assessment) automatic switch off failure nodes is possible The CAN Bus: Time Triggered CAN event and time triggered protocol time division multiplexed access (TDMA) reference message send by time master control unit 4 bytes for global time, 4 bytes for message exclusive window reserved for one particular CAN message only arbitration window one arbitration arbitration losers: retransmitting is disabled free window reference message reserved for future TTCAN expansion exclusive window Basic Cycle exclusive window arbitration window free window reference message MicroLab, VLSI-31 (53/61) MicroLab, VLSI-31 (54/61) page 27

28 Ethernet widely used as local area network for general purpose computing Carrier Sense Multiple Access with Collision Detection (CSMA/CD) non synchronized bus exponential backoff limits bus overload at high demand factors wait time maximum length defined by exp weighting nodes ability to detect factor collisions. random dithered times # of attempts Internet Protocol (IP) Internet protocol on OSI network level connectionless, packet-based communication real-time performance is hard to predict, except within embedded systems by simulation relationship between IP and network layers IP packet structure appliation... transport network link physical IP network link physical appliation... transport network link physical node A router node B sender receiver node # 1 preamble start frame sender receiver node # 2 destination address source address sender receiver node # 3 sender receiver node # 4 length padding CRC service stack FTP HTTP SMTP Telnet SNMP TCP UDP IP transmission control protocol file transfer protocol hypertext transport protocol simple mail transfer protocol user gram protocol simple network management MicroLab, VLSI-31 (55/61) MicroLab, VLSI-31 (56/61) page 28

29 design tasks Network-Based Design Communication Analysis scheduling computations and assigning them to PEs scheduling and allocating communication message delay no contention: t m = t x + t n + t r t x transmission delay, t n network transmission time, t r receiver side overhead with contention: t = t y d + t m network availability delay t d contention: fixed-priority: network may be blocked fair arbitration (round-robin): robin): t = d N(t +t x +t arb ) P1 Network-Based Design 1 Example PE1 PE2 PE3 Example: adjusting messages to improve network delay P1 is allocated to PE1, P2 to PE2, and P3 to PE3 processes and transmission times are 4 time units simple implementations: implementation with rescheduling: d1 P2 d2 PE1 PE2 P1 P2 PE3 P3 network d1 d2 time PE1 P1 P3 PE2 P2 PE3 network d3 d3 d3 d3 d1d2d1d2d1d2d1d2 time MicroLab, VLSI-31 (57/61) MicroLab, VLSI-31 (58/61) page 29

30 System Performance Analysis no interference t p1 t p2 nt x t p1 +nt x +t p2 P1 P2 interference between tasks dependency from P1 to P2 translates uncertainty in execution time of P1 to start of P2 co-allocation of P2 and P3 to PE2 means that variations of start of P2 affects completion time of P3 dependency from P3 to P4 translates variations of completion time of P3 to start time of P4 P1 P2 P4 P3 PE1 PE2 PE3 Hardware Platform Design, Allocation & Scheduling use only as much hardware as is necessary choices: number and types of PEs number and types of networks procedure to construct scheduling and allocation: for I/O intensive systems start with I/O devices inventory required I/O processing with I/Os with short deadlines may need local processing, other I/O can be attached with simple interfaces determine which devices can share PE or network analyze communication times to determine whether critical communication may interfere with each other allocate minimum required PE to go with each I/O design the rest of the system shown as below for computing-intensive intensive systems start with processes start with task with shortest deadline analyze communication times to determine whether critical communication may interfere with each other allocate lower-priority tasks to shared PEs where possible MicroLab, VLSI-31 (59/61) MicroLab, VLSI-31 (60/61) page 30

31 Exercises: VLSI-31 Ex vlsi31.1: (difficulty: easy, short time): Assume that our I2C bus runs at 200kbits/s and we need to send one 2 bytes. Some of the instructions in the transmitter and receivers drivers namely the loops that send/receive bytes will run concurrently with the message transmission. If we assume that 20 instructions outside the loops are executed by the transmitter and receiver, overheads on a 20 MHz microcontroller have to be taken into account. Calculate the total message delay. Result: start bit + address byte + ack + byte + ack + byte + ack + stop bit; t =147µs m MicroLab, VLSI-31 (61/61) page 31