VLSI Systems Design. Connection and Communication Models

Transcription

1 VLSI Systems Design Connection and Communication Models Goal: You can make the link between the low level connection architectures and the higher level communication models and master their implementation. You are familiar with the most common buses and networks.

2 Interprocess Communication multitasking systems need mechanisms for communication between tasks real-time operating systems (RTOS) provide interprocess communication mechanisms in embedded systems definition of process element (PE): a piece of software running on an embedded processor a hardware unit executing an algorithm implemented for example as a FSM-D architecture model interprocess communication is information exchange between processing elements

3 Blocking/Non-Blocking Communication We distinguish between blocking and non-blocking communication: blocking communication: the process element initiating the communication goes in a waiting state until communication end. non-blocking communication: the process element initiating the communication can execute other useful tasks during an ongoing communication. both types of communication are useful.

4 Shared Memory Communication: test-and-set operation two major (logically equivalent) communication styles exist: shared memory message passing shared memory communication between processing elements using bus a structure message is stored in communication link PE1 shared location Memory PE2 write read need of atomic test-and-set operations, else: PE 1 reads flag location and sees not busy PE2 reads flag location and sees no busy PE1 sets flag location to busy writing and writes to the shared location PE2 erroneously sets flag busy writing and overwrites the left by PE1

5 Shared Memory Communication: Semaphores a semaphore is a language level synchronization element with semaphores guarded access to shared memory can be realized: wait for semaphore: P(); P() uses a test-and-set operation to repeatedly test a location that holds a memory lock release semaphore: V(); V() resets the memory lock... /* non-protected memory access is here */ P(); /* wait for semaphore */ /* do protected memory access here */ V(); /* release semaphore */ /* non-protected memory access is here */...

6 Message Passing Communication each communication entity has its own send/receive unit message is stored on endpoints of send/receive unit and not in communication link as at shared memory communication message passing is used at applications where units operate relatively autonomous: ex. car control system PE1 send/receive message PE2 send/receive

7 Signals major interprocess communication mechanisms: shared memory message passing simple interprocess communication mechanism: signal a signal does not pass beyond its existence a signal is analogous to hardware interrupt, but can entirely be implemented in software a signal is generated by a process and transmitted to another process by the operating system signal have fairly limited functionality: CPU exceptions to operating system operating system services termination of a process PE1 send signal OS/PE2 receive

8 Data Dependencies communication processes that execute exchange at identical rates: relationship shown using dependencies dependencies define a partial ordering of process execution directed acyclic graph (DAG): task graph P1 P3 P4 P2 communication processes that execute exchange at different rates: no one-to-one relation between source and destination of video system audio

9 Deadlocks US Kansas legislature law early last century: When two trains approach each other at a crossing, both shall come to a full stop and neither shall start up again until the other has gone. Dealing with deadlock problem: ignoring (very popular) detection and recovering (quite popular) preventing avoiding (not applicable) R 1 R 3 P 1 P 2 P 3 R 2

10 The Four-Cycle-Handshake the four-cycle-handshake ensures a correct communication between two devices predefined master/slave devices device 1 is master and initiates communication device 2 is slave send or receive is possible bus is bidirectional req device 1 (master) ack rw device 2 (slave)

11 The Four-Cycle-Handshake: predefined master/slave four-cycle-handshake for sending: rw device 1 req valid device 2 ack stored request phase store phase acknowledge phase end phase four-cycle-handshake for receiving: rw device 1 req stored device 2 ack valid request phase hnowledge phase store phase end phase

12 Bus Allocation complex SoC may have sharable resources: memories processing elements I/O devices buses bus allocation principles: allocation on a fixed time schedule bus allocation on the basis of need destructive bus allocation (Ethernet: Carrier Sense Multiple Access with Collision Detection CSMD/CD,...) non-destructive bus allocation (arbitration)

13 Bus Arbitration Algorithms arbitration is the method to grant the bus to a requesting master arbitration schemas: fixed priority (or rate-monotonic) algorithm round robin algorithm top priority priorities A B C D E F G H priorities A B C D E F G H

14 Typical Processor Bus a bus is a collection of wires as well as a protocol microprocessor buses build on handshake protocol basic bus operations are reading and writing system clock helps to increase transfer speed device 1 device 2 processing element (CPU) clock r/w addr en addr rdy clock r/w addr en wait state addr addr valid addr valid rdy valid valid read write

15 Bus With DMA Controller direct memory access (DMA) controllers perform direct transfers between devices without CPU involvement four-cycle-handshake with processor to get bus master (interrupt processor when finished) used for high speed requirements to prevent to block the processor too long, partial block transfer mode possible, 16, 32 or 256 words for example. bus DMA controller is a bus with 2 masters processing element (CPU) bus request bus grant DMA controller device 1 clock r/w addr en addr rdy device 2

16 System Bus embedded systems-on-chip use bus hierarchies: Avalon from Altera Inc., used for Nios (simple) AMBA TM bus from AMD Inc., used for ARM TM CoreConnect TM from IBM Inc., used for PowerPC TM features: high-speed buses provide wider connections high-speed buses require more expensive circuitry and connectors. The cost of low-speed devices can be held down by using lower-speed, lower-cost bus. The bridge may allow the buses to operate independently, thereby providing some parallelism in processing an I/O operations. bus bridge: slave at fast bus, master at slow bus CPU low-speed I/O device high-speed bus bridge low-speed bus memory high-speed processing element low-speed processing element

17 The AMBA System Bus advanced high-performance bus (AHB) high-performance pipelined operation multiple bus master burst transfer split transactions advanced high-performance system bus (ASB) dito, but no split transactions advanced peripheral bus (APB) low-power latched address and control simple interface suitable for many peripherals external memory interface (highbandwidth) DMA on-chip RAM (highbandwidth) AHB or ASB CPU processing element (high-speed) bridge PIO Keypad APB UART Timer

18 Advanced High-Performance Bus (AHB) The AHB bus consists of the following elements: AHB master: able to initiate read and write transfers only one bus master is allowed to control the bus AHB slave: responds to read and write operations in a given address space signals back to the master: success, failure or waiting of the transfer AHB arbiter: ensures that only one master at a time is allowed to control bus any arbitration algorithm can be used, like highest priority, fair access, etc AHB decoder: decodes address and generates device select signals single centralized decoder is required

19 Basic AHB Interconnection Schema arbiter determines bus master central multiplexor schema central decoder for read additional characteristics: single cycle bus master handover single clock edge operation non-tristate implementation wider bus configuration (64/128 bits) master # 1 master # 2 master # 3 HADDR HWDATA HRDATA HADDR HWDATA HRDATA HADDR HWDATA HRDATA arbiter HADDR HWDATA HRDATA HADDR HWDATA HRDATA HADDR HWDATA HRDATA HADDR HWDATA HRDATA slave # 1 slave # 2 slave # 3 slave # 4 decoder

20 Phases: Basic AHB Transfer address & control phase one or more phase Slave can delay transfer with HREADY address source is master: HADDR[31:0] source for write operations is master: HWDATA[31:0] source for read operations is slave: HRDATA[31:0] HCLK addr phase (A) phase (A) HADDR[31:0] A B C D control ctrl A ctrl B ctrl C ctrl D HWDATA[31:0] A B C HREADY HRDATA[31:0] A B C

21 AHB Transfer Example Master shows transfer type with HTRANS[1:0] IDLE ( 00 ): no transfer is required BUSY ( 01 ): master is delaying an ongoing transfer NONSEQUENTIAL ( 10 ): first transfer of a burst or single transfer SEQ ( 11 ): remaining transfers of a burst Delaying transfer master delays transfer with HTRANS[1:0] slave delays transfer with HREADY incremental burst of unspecified length is shown C1 C2 C3 C4 C5 C6 C7 C8 HCLK HTRANS[1:0] NONSEQ BUSY SEQ SEQ SEQ SEQ HADDR[31:0] HBURST[2:0] 0x20 0x24 0x24 0x28 0x2C 0x30 INCR HWDATA[31:0] 0x20 0x24 0x28 0x2C 0x30 HREADY HRDATA[31:0] 0x20 0x24 0x28 0x2C 0x30

22 AHB Transfer Example (4-beat wrapping burst) Master defines bus operation with HBURST[2:0] SINGLE ( 000 ): single transfer INCR ( 001 ): increment burst of unspecified length WRAP4 ( 010 ): 4-beat wrapping burst INCR4 ( 011 ): 4-beat incrementing burst WRAP8 ( 100 ): 8-beat wrapping burst INCR8 ( 101 ): 8-beat incrementing burst WRAP16 ( 110 ): 16-beat wrapping burst INCR16 ( 111 ): 16-beat incrementing burst Burst must not cross 1kB address boundary HCLK HTRANS[1:0] NONSEQ SEQ NONSEQ SEQ SEQ SEQ HADDR[31:0] 0x70 0x72 0x38 0x3C 0x30 0x34 HBURST[2:0] INCR WRAP4 HWRITE HSIZE[2:0] HPROT[3:0] SIZE=halfword control for burst, SIZE=word HWDATA[31:0] 0x70 0x72 0x38 0x3C 0x30 0x34 HREADY HRDATA[31:0] 0x70 0x72 0x38 0x3C 0x30 0x34

23 AHB Transfer Example with Response slave can complete a transfer in a number of ways: complete the transfer immediately insert wait states signal an error to indicate transfer has failed delay the completion of the transfer, but allow master/slave to back off bus slave shows status of transfer with HRESP[1:0] in combination with HREADY OKAY: transfer is progressing normally ERROR: transfer has been unsuccessful RETRY and SPLIT: both indicate that transfer cannot complete immediately ERROR, RETRY and SPLIT are at least two-cycles C1 C2 C3 C4 C5 C6 C7 C8 HCLK HTRANS[1:0] NONSEQ SEQ IDLE NONSEQ SEQ IDLE NONSEQ HADDR[31:0] A A+4 B B+4 B HWDATA[31:0] A B HREADY HRESP[1:0] OKAY ERROR ERROR OKAY RETRY RETRY

24 AHB Bus Arbitration signals for bus arbitration: HBUSREQx: master sends bus request HGRANTx: arbiter issues bus grant HMASTER[3:0]: arbiter issues bus master number HLOCKx: master may request bus lock HMASTLOCKx: arbiter issues bus lock grant signal arbiter can terminate non size-limited bursts early master can require locked access if a master looses bus access in the middle of a burst it must re-assert HBUSREQx to regain access C1 C2 C3 C4 C5 C6 C7 C8 HCLK HBUSREQ_M1 HBUSREQ_M2 HGRANT_M1 HGRANT_M2 HMASTER[3:0] Mx M1 M2 HTRANS[1:0] IDLE IDLE NONSEQ SEQ SEQ SEQ NONSEQ HADDR[31:0] A A+4 A+8 A+12 B HWDATA[31:0] A A+4 A+8 A+12 HREADY

25 AHB Address Decoder Schematic slaves sample HSELx when HREADY is active minimum address space allocated to a slave is 1kB if system does not contain complete memory map, default slave (decoder) should respond to wrong addresses access attempt to nonexistent location will be answered by default slave: ERROR response to NONSEQUENTIAL or SEQUENTIAL zero wait state OKAY response to IDLE or BUSY Master determines transfer size with HSIZE[2:0] 000 : size is byte 001 : size is half-word 010 : size is word : size is 32 bytes slave # 1 master # 1 HADDR_M1[31:0] master # 2 HADDR_M2[31:0] HADDR HSEL_S1 decoder HSEL_S2 HSEL_S3 slave # 2 slave # 3

26 AHB Interface Diagrams select HSELx HADDR[31:0] HWRITE HTRANS[1:0] HSIZE[2:0] HBURST[2:0] HWDATA[31:0] HRESETn HCLK HMASTER[3:0] HMASTLOCK address and control reset clock HREADY HRESP[1:0] HRDATA[31:0] HSPLIT[15:0] AHB slave split-capable slave transfer response arbiter grant HGRANTx HREADY HRESP[1:0] HRDATA[31:0] HRESETn HCLK transfer response reset clock HBUSREQx HLOCKx HTRANS[1:0] HADDR[31:0] HWRITE HSIZE[2:0] HBURST[2:0] HPROT[3:0] HWDATA[31:0] AHB master address and control arbiter transfer type arbiter requests and locks HBUSREQx1 HLOCKx1 HBUSREQx2 HLOCKx2 HADDR[31:0] HSPLITx[15:0] HTRANS[1:0] HBURST[2:0] HRESP[1:0] HREADY HRESTEn address and control reset HGRANTx1 HGRANTx2 HMASTER[3:0] HMASTLOCK AHB arbiter arbiter grants HRDATA[31:0] HSELx1 HSELx2 AHB decoder select address

27 AHB-Lite AHB-Lite is a subset of full AHB specifications only one bus master thus no request/grant protocol for arbiter thus no split or retry response from slaves AHB-Lite enables faster design and verification compatibility: full AHB master can be used in AHB-Lite system AHB slaves can be used in AHB-Lite system, if they do not support split and retry AHB-Lite slaves can be used in full AHB system slave #1 master slave #2 slave #3

28 Advanced Peripheral Bus (APB) the APB is a low-power extension to the AHB/ASB APB appears as a local secondary bus encapsulated as a single AHB/ASB slave device APB bridge acts as slave and handles necessary handshake control and bus retiming APB bridge proves latching of all addresses, control and APB should be used to handle low-bandwidth devices APB slave devices have following characteristics: address and control valid throughout the access (nonpipelined) zero-power interface during non-peripheral bus activity timing can be provided by decode with strobe timing (unclocked interface) write valid for the whole access (allowing glitch-free transparent latch implementation) highbandwidth highbandwidth external memory interface DMA bus master AHB or ASB CPU high-speed processing bridge PIO Keypad APB UART Timer

29 write transfer APB Basic Transfers PCLK PADDR[31:0] PWRITE PSEL PENABLE PWDATA[31:0] C1 C2 C3 C4 addr A A IDLE SETUP ENABLE IDLE read transfer PCLK PADDR[31:0] PWRITE PSEL PENABLE PRDATA[31:0] C1 C2 C3 C4 addr A A IDLE SETUP ENABLE IDLE

30 APB Interface Diagrams reset clock PRDATA[31:0] PRESETn PCLK APB bridge PSEL1 PSEL2 PENABLE PADDR[31:0] PWRITE PWDATA[31:0] selects strobe address & control write recommended to implement APB bus as multiplexed or OR-bus schema tri-state is possible but not recommended select strobe address & control PSELx PENABLE PADDR[31:0] PWRITE PWDATA[31:0] APB slave PRDATA[31:0] PRDATA[31:0] read reset clock PRESETn PCLK

31 Read Transfer from AHB to APB for a write transfer the can be latched when: risinf edge of PCLK, when PSEL is high rising edge of PEANBLE, when PSEL is high C1 C2 C3 C4 C5 C6 C7 C8 C8 CLK &PCLK ADDR[31:0] HWRITE addr A addr A+4 addr A+8 addr A+12 addr A+12 RDATA[31:0] (A) (A+4) (A+8) (A+12) HREADY PADDR[31:0] addr A addr A+4 addr A+8 addr A+12 PWRITE PSEL PENABLE RDATA[31:0] (A) (A+4) (A+8) (A+12)

32 AMBA Test Interface AMBA test philosophy allows individual modules in the system to be tested in isolation modules are designed to be tested by bus transfers only test harness provides access to inputs/outputs of modules not already connected to bus dedicated module inputs application module dedicated module outputs test stimuli bus interface test results AMBA bus control Test Interface Controller (TIC) External Bus Interface (EIB) TCLK TREQA TREQB TACK address AMBA bus S[31:0]

33 AMBA Test Interface Write Cycle test control signals during normal operation TREQA TREQB TACK description normal operation enter test mode request test mode entered test control signals during test mode TREQA TREQB TACK description current access incomplete address, control or turnaround vector write vector read vector exit test mode HCLK C1 C2 C3 C4 C5 C6 C7 C8 C9 TREQA TREQB TACK TBUS[31:0] HTRANS[31:0] HADDR[31:0] control addr write1 write2 write3 addr IDLE NONSEQ SEQ SEQ IDLE A A+4 A+8 HBURST[2:0],HWRITE,HSIZE[2:0],HPROT[3:0] HWDATE[31:0] A A+4 A+8 HREADY

34 Introduction to Networks motivation for distributed embedded systems: if processing tasks are physically distributed, processing power can be implemented there (eg. automotive) reduction by signal pre-processing for reduction (eg: finger print feature recognition) modularity by encapsulating processing operations and not using local system bus interprocess communication in SoC shared memory is often used in distributed system networks shared memory is not available sensor/ actuator PE #1 32-bit RISC PE #2 32-bit RISC PE #3 sensor/ actuator PE #4 DSP PE #5 SoC PE #6 network

35 Switching-Based Architectures crossbar: higher bandwidth compared to bus-based architectures major drawback is its expense PEin1 PEin2 PEin3 PEin4 PEout1 PEout2 PEout3 crosspoint switch PEout4 omega: higher bandwidth compared to bus-based architectures, but lower than crossbar more expense than bus, but less expensive than crossbar PEout1 PEin1 PEout2 PEin2 PEout3 PEin3 PEout4 2 x 2 switch PEin4

36 OSI Network Abstraction Model open system interconnection reference model (OSI) OSI defines communication formats, contents and meanings: connection-oriented protocol: first connection is established and possibly protocol negotiated connectionless protocol: no setup necessary, message directly transmitted for modularization/encapsulation 7 layers are defined in OSI: process A machine #1 machine #2 process B 7 application end-user interface application 6 presentation format presentation 5 session application dialog format session 4 transport connections transport 3 network end-to-end service network 2 link reliable transport link 1 physical mechanical, electrical physical

37 The OSI Layer Message link layer header link layer trailer network layer header transport layer header session layer header presentation layer header application layer header message bits that actually appear on the network each layer has its own protocol that can be changed independently of the other ones technology improvement this independence makes layer protocols attractive the collection of protocols in a particular system is called protocol stack

38 The OSI Layers The Physical Layer: basic property of interface, mechanical, electrical and bit exchange procedure The Data Link Layer: primary purpose is error detection and correction group bits into frames, appends checksum The Network Layer: end-to-end transmission by routing The Transport Layer: defines connection-oriented services breaks message into packets, and guarantees delivery of whole message The Session Layer: enhanced version of transport layer adds checkpoints for crash handling The Presentation Layer: defines exchange formats The Application Layer: collection of miscellaneous protocols like , file transfer, etc

39 The Client-Server Model protocol overhead in OSI might be to high for LAN: traversing half a dozen layers up and down (acceptable for WAN) client-server model structures the cooperating processes: server: processes who offer services to users client: processes who consumes services use of connectionless request/reply protocol primary advantage: simplicity: no connection has to be established, reply message serves as acknowledge efficiency: protocol stack is shorter, only 3 OSI levels are necessary layer 7 client µkernel request reply server µkernel 6 5 request/reply 4 3 network 2 link 1 physical

40 Buffered vs. Un-Buffered Message Passing: Mailbox un-buffered message passing receive has to be issued before send primitive buffered message passing: mailbox serving processes install mailbox before using it client µkernel address refers to a process server addr µkernel network client µkernel address refers to a mailbox server µkernel addr network

41 Reliable Message Passing different approaches to reliable message passing: assume the message passing is unreliable (e.g. post office) reliable message passing using separate acknowledgement (compare four cycle handshake) layer client µkernel 1st request 3rd reply 2nd ACK 4rd ACK server µkernel request/reply 4 transport 3 network 2 link 1 physical reliable message passing using acknowledgment principle 1st request client 2rd reply/ack server µkernel 3rd ACK µkernel network

42 The I2C Bus: Physical Layer popular for initialization & command word exchange between up and peripherals like MP3, AD, smart sensor, small EEPROM, etc serial bi-directional 2-wire bus multi-master/slave operation open drain/open collector lines structure of an I2C bus system master #1 transmitter & receiver master #2 transmitter slave #1 transmitter & receiver slave #2 receiver SCL SDA physical layer I2C driver SCL SDA clock input assert clock input assert

43 Level Shifter for I2C Bus (Physical Layer) due to chip technology scaling single supply voltage is rarely seen today networks connecting devices of different voltage sections thus need level shifters VDD1=3.3V VDD2=5V SCL1 g s d SCL2 SDA1 g s d SDA2 3.3V I 2 C device 3.3V I 2 C device 5V I 2 C device 5V I 2 C device lower voltage section higher voltage section

44 Multiple Level Shifter for I2C Bus (Physical Layer) multiple power supplies power down of supply sections possible modular and extendable VDD3 = max(vddi) VDD1=3.3V VDD2=5V SCL1 g s d d g s SCL2 SDA1 g s d d g s SDA2 3.3V I 2 C device 3.3V I 2 C device 5V I 2 C device 5V I 2 C device lower voltage section higher voltage section

45 I2C Bus: Data Link Layer transmitting one byte (start) - byte - acknowledge (stop) SCL SDA MSB 8-bit byte ack start condition stop condition who activates the bus lines SCL master SDA transmitter SDA receiver MSB transmitter stays off the bus during acknowledgement acknowledgement signal from receiver trasnsmitter takes bus ( or stop)

46 I2C Bus: Data Link Layer Transfer Formats master write format (2 bytes) 7-bit slave address 0 can be repeated n times Start addr Write Ack Ack Ack Stop master read format (2 bytes) 7-bit slave address 1 can be repeated n times Start addr Read Ack Ack NAck Stop 2 succeeding master write formats can be repeated n times Start addr Write Ack Ack Start addr Ack Stop no proceeding Stop condition

47 The CAN Bus Control Area Network (CAN): ISO standard high-integrity serial communications bus for real-time applications operates at rates of up to 1 Mbit/sec excellent error detection and confinement capabilities originally developed by Bosch for use in cars, now being used in many other industrial automation and control applications features: message prioritization guarantee of latency time error detection and signaling, automatic retransmission of corrupted messages multi-master master #1 transmitter & receiver master #2 transmitter & receiver slave #1 transmitter & receiver slave #2 transmitter & receiver

48 physical layer The CAN Bus OSI Layer Structure not defined in CAN protocol but in ISO link layer object layer transfer layer Application Layer Data Link Layer (Object Layer) -message filtering -message and status handling (Transfer Layer) -fault confinement -error detection and signaling -message validation -acknowledgement -arbitration -message framing -transfer rates and timing Physical Layer -signal level and bit representation - transmission medium

49 CAN: Physical Layer application domain specific electrical characteristics voltage levels for automotive applications up to 36V wired-and logic on CAN bus lines separation between CAN controller an transceiver often seen CAN bus V diff C_H C_L bus termination V dd_n transceiver V dd_m transceiver 2-wire differential lines (up to 1 Mbaud) V gnd_n V gnd_m CAN controller node #n CAN controller node #m CAN bus V dd bus pull-up single wire line (only 33.3 kbaud) CAN controller node #1 CAN controller node #2

50 CAN Network: Data Link Layer principles of exchange no nodes are addressed content-oriented addressing schema: - identifier of message content (unique in network) - identifier defines priority CAN node #1 (receiver) CAN node #2 (transceiver) CAN node #3 (receiver) CAN node #4 (receiver) accept prepare accept select select select receive message send message receive message receive message CAN bus

51 node #1 loses node #3 loses CAN Network: Data Link Layer Bus Arbitration bus allocation: fast transmission asks for fast bus allocation non-destructive bitwise arbitration identifier defines arbitration priority wired-and priority: low value means high priority CSMA/AMP: Carrier Sense Multiple Access with Arbitration on Message Passing CAN bus CAN node #1 CAN node #2 CAN node #3 CAN bus node #1 node #2 node #3

52 CAN Network: Data Link Layer Message Frame Formats CAN supports two message frame formats: standard (CAN 2.0A): 11 bit identifier extended (CAN 2.0B): 29 bit identifier ( bit) interframe space Standard Data Frame to inter frame space start arbitration field control field field CRC field ack field end of frame identifier RTR bit identifier extension r0 length code CRC field CRC delimiter ACK slot ACK delimiter RTR: remote transmission request r0: reserved

53 CAN Network: Data Link Layer Error Handling detecting and signaling errors: CRC: x 15 + x 14 + x 10 + x 8 + x 7 + x 4 + x 3 +1 frame check ACK check error detection at bit level: monitoring: each transmitter checks locally send signals bit stuffing: after 5 identical consecutive bits the sender adds one complementary bit which will be removed by the receivers (used for bit synchronization) error handling: if error is detected, the current transmission is aborted by sending an error flag sender automatically re-attempts transmission CAN distinguishes between sporadic and permanent errors and thus localizing node failures (statistical assessment) automatic switch off failure nodes is possible

54 The CAN Bus: Time Triggered CAN event and time triggered protocol time division multiplexed access (TDMA) reference message send by time master control unit 4 bytes for global time, 4 bytes for message exclusive window reserved for one particular CAN message only arbitration window one arbitration arbitration losers: retransmitting is disabled free window reserved for future TTCAN expansion Basic Cycle reference message exclusive window exclusive window arbitration window free window reference message

55 Ethernet widely used as local area network for general purpose computing Carrier Sense Multiple Access with Collision Detection (CSMA/CD) non synchronized bus exponential backoff limits bus overload at high demand factors maximum length defined by nodes ability to detect collisions. wait time exp weighting factor random dithered times # of attempts sender receiver node # 1 sender receiver node # 2 sender receiver node # 3 sender receiver node # 4 preamble start frame destination address source address length padding CRC

56 Internet Protocol (IP) Internet protocol on OSI network level connectionless, packet-based communication real-time performance is hard to predict, except within embedded systems by simulation relationship between IP and network layers IP packet structure appliation... transport network link physical IP network link physical appliation... transport network link physical node A router node B service stack FTP HTTP SMTP Telnet SNMP TCP UDP IP transmission control protoco file transfer protocol hypertext transport protocol simple mail transfer protoco user gram protocol simple network managemen

57 design tasks Network-Based Design Communication Analysis scheduling computations and assigning them to PEs scheduling and allocating communication message delay no contention: t m = t x + t n + t r t x transmission delay, t n network transmission time, t r receiver side overhead with contention: t y = t d + t m t d network availability delay contention: fixed-priority: network may be blocked fair arbitration (round-robin): t d = N(t x +t arb )

58 Network-Based Design P11 Example PE1 PE2 PE3 Example: adjusting messages to improve network delay P1 is allocated to PE1, P2 to PE2, and P3 to PE3 processes and transmission times are 4 time units simple implementations: P2 d1 d2 P3 PE1 PE2 P1 P2 PE3 P3 network d1 d2 time implementation with rescheduling: PE1 PE2 P1 P2 PE3 network d3 d3 d3 d3 d1d2d1d2d1d2d1d2 time

59 System Performance Analysis no interference t p1 t p2 P1 nt x P2 t p1 +nt x +t p2 interference between tasks dependency from P1 to P2 translates uncertainty in execution time of P1 to start of P2 co-allocation of P2 and P3 to PE2 means that variations of start of P2 affects completion time of P3 dependency from P3 to P4 translates variations of completion time of P3 to start time of P4 P1 P2 P3 P4 PE1 PE2 PE3

60 Hardware Platform Design, Allocation & Scheduling use only as much hardware as is necessary choices: number and types of PEs number and types of networks procedure to construct scheduling and allocation: for I/O intensive systems start with I/O devices inventory required I/O processing with I/Os with short deadlines may need local processing, other I/O can be attached with simple interfaces determine which devices can share PE or network analyze communication times to determine whether critical communication may interfere with each other allocate minimum required PE to go with each I/O design the rest of the system shown as below for computing-intensive systems start with processes start with task with shortest deadline analyze communication times to determine whether critical communication may interfere with each other allocate lower-priority tasks to shared PEs where possible

61 Exercises: VLSI-31 Ex vlsi31.1: (difficulty: easy, short time): Assume that our I2C bus runs at 200kbits/s and we need to send one 2 bytes. Some of the instructions in the transmitter and receivers drivers namely the loops that send/receive bytes will run concurrently with the message transmission. If we assume that 20 instructions outside the loops are executed by the transmitter and receiver, overheads on a 20 MHz microcontroller have to be taken into account. Calculate the total message delay. Result: start bit + address byte + ack + byte + ack + byte + ack + stop bit; t m =147µs