Buffered Distributor Proposal. Gigabit. (a.k.a. Full Duplex Repeater) (a.k.a. Buffered Repeater) Packet Engines. Bernard Daines

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1 Gigabit Buffered Distributor Proposal (a.k.a. Full Duplex Repeater) (a.k.a. Buffered Repeater) Bernard Daines Packet Engines (59) FAX (59) Mailing Address Shipping Address Box E Sprague Spokane WA Spokane WA 9926 Buffered Distributor -- 1

2 The Issue Desire better performance for fiber links than proposed half duplex repeater schemes Buffered Distributor -- 2

3 With Gigabit Ethernet We have Full Duplex Media Full Duplex PHY s Full Duplex MAC s Let s have a repeater/switch sort of device that is not half duplex. Buffered Distributor -- 3

4 The Breakthrough! If all we have to do is support full-duplex links, the problem becomes very easy. Buffered Distributor -- 4

5 An Important Point! MOTIVATION FOR THE GIGABIT BUFFERED DISTRIBUTOR IS COST VS. GIGABIT SWITCH Buffered Distributor -- 5

6 N Ports Buffered Distributor N port hub with full duplex links Full Duplex Links Buffered Distributor -- 6

7 Step 1: Provide a FIFO for each incoming line to avoid collision domain timing and distance restrictions. Tx Full Duplex Link Rx FIFO PHY PHY Rx Tx FIFO Add small output FIFO for convenience. Buffered Distributor -- 7

8 Solution! Use frame based flow control to keep each input FIFO from overflowing. It s already standard. We don t have to invent anything new. Buffered Distributor -- 8

9 Step 2: Add.3x flow control to each port. Tx Full Duplex Link Rx FIFO Flow Control PHY PHY Flow Control Rx Tx FIFO Detailed view of port interface showing how flow control circuitry connects. Buffered Distributor -- 9

10 Step 3: Hook ports to the arbitration method of your choice inside the box. Buffered Distributor -- 1

11 Tx Flow Control PHY Full Duplex Link Rx Tx Flow Control PHY Full Duplex Link Rx Tx Flow Control PHY Full Duplex Link Rx Rx FIFO PHY Flow Control Tx FIFO Rx FIFO PHY Flow Control Tx FIFO Rx FIFO PHY Flow Control Tx FIFO Buffered Distributor A R B I T R A T I O N R E P E A T E R A N D C O R E

12 The box arbitrates among its local FIFO s and forwards packets, one at a time, back to all the devices - except the source port. Buffered Distributor -- 12

13 Specifications Link Length (up to 2km) Receiver FIFO Size (1KBytes) Repeater Core Algorithm (your choice) Outbound FIFO (your choice) Buffered Distributor -- 13

14 1BASE-T/F Just One Distributor! Buffered Distributor DTE DTE DTE DTE Buffered Distributor -- 14

15 Conclusion Formalize a one distributor topology Standardize asymmetric flow control Standardize only minimal behavior of buffered distributor leaving features and link lengths to implementers Buffered Distributor -- 15

16 1518 Byte Packets - Round Robin Core Bandwidth XOFF Frames Core Bandwidth (Gb/S) XOFF Fames Offered Load (Gb/S) Repeated Ports = 12 Simulation Time = 2MS Buffered Distributor -- 16

17 Random Size Packets - Round Robin Core Bandwidth XOFF Frames Core Bandwidth (Gb/S) XOFF Frames Offered Load (Gb/S) Repeated Ports = 12 Simulation Time = 2MS Buffered Distributor -- 17

18 64 Byte Packets - Round Robin Core Bandwidth (Gb/S) Core Bandwidth XOFF Frames XOFF Frames Offered Load (Gb/S) Repeated Ports = 12 Simulation Time = 2MS Buffered Distributor -- 18

19 1518 Byte Packets - CSMA/CD Core Bandwidth (Gb/S) Core Bandwidth XOFF Frames Contentions XOFF Frames & Contentions Offered Load (Gb/S) Repeated Ports = 12 Simulation Time = 2MS Buffered Distributor -- 19

20 Random Size Packets - CSMA/CD Core Bandwidth XOFF Frames Contentions Core Bandwidth (Gb/S) XOFF Frames & Contentions Offered Load (Gb/S) Repeated Ports = 12 Simulation Time = 2MS Buffered Distributor -- 2

21 64 Byte Packets - CSMA/CD Core Bandwidth (Gb/S) Core Bandwidth XOFF Frames Contentions XOFF Frames & Contentions Offered Load (Gb/S) Repeated Ports = 12 Simulation Time = 2MS Buffered Distributor -- 21