Gigabit Ethernet Switch Subsystem

Transcription

1 Gigabit Ethernet Switch Subsystem 1

2 Agenda GbE Switch SGMII MDIO Example Code SGMII Loopback PC-EMAC Communication 2

3 GbE Switch Overview ALE Operational mode Normal Mode Direct Packet Bypass Mode MAC Flow Control 3

4 GbE Switch - Overview One CPPI port Two SGMII ports One MAC per SGMII port Address Lookup Engine (ALE) Determine which port to forward the frame A lookup table with 1024 entries shared for three ports. Entry table can be updated by ALE through learning and semiautomatic age-out mechanism or maintained by host. Learn based on source MAC address Forward based on destination MAC address Packet streaming interface Port 0 ( CPPI port ) ALE 1 MAC ) Port1 SGMII port MAC Port2 SGMII port SGMII0 SGMII1 4

5 GbE Switch ALE Operational Mode Normal Mode Direct Packet Bypass Mode 5

6 GbE Switch ALE Normal Mode Configure all the three ports as forward state, and enable learn for src addr learning to update the ALE table in time. Entered frame with dstaddr0 is forwarded to TX port0, with dstaddr1 is forwarded to port1, and with dstaddr2 is forwarded to port2. While the frame without the matched dstaddr will be broadcasted. Port 0 ( CPPI port ) Enable learn Forward state Dstaddr0 Dstaddr1 Dstaddr2 ALE port0 port1 port2 Port 1 ( SGMII port ) Enable learn Forward state Port 2 ( SGMII port ) Enable learn Forward state TX TX 6

7 GbE Switch Direct Packet Only for transmit packet output from port0, the packet can be sent to the specified port1 or port2 directly through setting the ps_flag in the descriptor. Port 1 ( SGMII port ) TX TX Port 0 ( CPPI port ) ALE Port 2 ( SGMII port ) TX 7

8 GbE Switch ALE Bypass Mode Only for received packet from port1 or port2, the received packet is sent to port0 directly Port 1 ( SGMII port ) Port 0 ( CPPI port ) ALE Port 2 ( SGMII port ) 8

9 GbE Switch MAC Flow control is enabled by setting the RX_FLOW_EN or the TX_FLOW_EN bit in the MAC_CONTROL register, and the flow control event is triggered by configure the MAC receive FIFO by host Receive flow control For half-duplex mode, generate a collision sequence for received frames to prevent frame reception. For full-duplex mode, send a pause frame with multicast destination address and set the source address with the MAC address to make all the station stop sending frame to the received port within the indicated period. Transmit flow control Only support for full-duplex mode, incoming pause frame with destination address equal to multicast address or the MAC address of the switch port to be controlled, and set the source address equal to the transmit device to make the source MAC port stop transmitting frame. 9

10 SGMII Support Operation Modes Digital Loopback Mode SGMII to PHY SGMII to SGMII with auto-negotiation SGMII to SGMII with forced link 10

11 SGMII Digital loopback Transmit and receive signals are connected before reaching SerDes module. Tx SGMII Port SGMII Digital loopback SerDes 11

12 SGMII SGMII to PHY Configure external PHY device as master, while SGMII as the slave. Tx SGMII Port (MAC) SGMII SerDes PHY Enable EXT_CTL Enable AN SLAVE MASTER 12

13 SGMII SGMII to SGMII with auto-negotiation Configure one SGMII as the master, while the other as the slave. Tx SGMII Port (MAC) SGMII SerDes SerDes SGMII SGMII Port (MAC) Tx Enable EXT_CTL Enable AN Master Enable full-duplex Enable gigabit mode Enable AN Slave Enable EXT_CTL 13

14 SGMII SGMII to SGMII with forced link Configure both SGMII as master. Tx SGMII Port (MAC) SGMII SerDes SerDes SGMII SGMII Port (MAC) Tx Master Enable full-duplex Enable gigabit mode Master Enable full-duplex Enable gigabit mode 14

15 MDIO Connect up to 32 PHY devices Store the connected PHY devices link state in the ALIVE and LINK register Monitor Process Set two PHY devices to be monitored simultaneously, enable interrupt for link status change When generate link status change interrupt, the host can read or write the related PHY device s link status register Set another two PHY devices to be monitored 15

16 GbE Switch Initialization Procedure Configure the SerDes PLL, TX/RX registers Configure the SGMII_CONTROL and MR_ADV_ABILITY register to establish a link and autonegotiation Configure the MAC1_SA and MAC2_SA source address hi and lo registers for flow control Configure the MAC_CONTROL, and MAC_RX_MAXLEN register to enable GMII, Gigabit, and flow control and set the receive maximum length Enable the desired statistics ports by programming the CPSW_STAT_PORT_EN register Configure the CPSW_CONTORL register to enable the switch port Configure the ALE, can be set as bypass mode for simple test 16

17 GbE Switch Tx/ Transmit data through EMAC, push the descriptor with linked buffer to TXQ648 Receive data from external devices through EMAC The packet can be routed to PA according to the below CPSW_CFG_REG. At reset the PA is set as bypass mode, and the received packet is routed out to the CPU through the PA CPPI channel22(flow 22) for TXTA, and channel23(flow 23) for TXTB. 17

18 Example code SGMII loopback data flow QMSS PDSP0 Accu HostISR48 INTC HWI8 ISR Q704 Ping-pong list flow22 PDSP3 PDSP1 PDSP0 TxQ648 PA flow0 Packet streaming interface Port 0 ( CPPI port ) Enable learn Forward state Dstaddr1 Dstaddr1 Dstaddr2 ALE port0 port1 port2 Port 1 ( SGMII port ) Enable learn Forward state Port 2 ( SGMII port ) Tx SGMII0 Flow with ALE and PA enable Flow with ALE and PA bypass Enable learn Forward state 18

19 PC-EMAC communication example based on TN EVM (C5) 19

20 Hardware diagram and data link Hardware diagram Ethernet sub-system SGMII port connect with Marvell switch SGMII port through SERDES Marvell switch PHY port configured by DSP1 through MDIO in Marvell switch and MDIO arbitration logic in FPGA MDIO arbitration logic in FPGA guaranteed only one DSP can be the MDIO controller at any given time 20

21 Hardware diagram and data link Data link CPSW Port1 SGMII0 PA ALE MDIO Port0 controller Ethernet sub-system CPPI / QMSS Core DSP1 FPGA SERDES 0xC MDIO Arbitration logic SGMII (Port 4) Marvell 88E6131 Ethernet Switch MDIO PHY 0 RJ45 (RJ1) PC Data flow Control flow Data link of EMAC-PC example on TN EVM C5 21

22 Example code processing flow (TX) Transimt DSP System initialization (includingevm board, CPPI/QMSS, PASS, EMAC, Marwell switch, Serdes) DSP System configuration (including CPPI/QMSS, PASS) DSP Send packets Through EMAC Packets send to PC PC waiting packets Set ALE bypass mode (data from SGMII fort of EMAC can only be received by PKTDMA port) Configure link between EMAC SGMII port and Marvell switch SGMII port as Force Link without Auto Negotiation Send packets from PKTDMA to SGMII with specified port (set TO_PORT bit of PS flag in descriptor) instead of using ALE Enable ALE Self-learning function and print ALE s entry to see the record Use Ethernet sniffer software (WireShark) to parser received packets 22

23 Example code processing flow (RX) Receive PC Change packets header and combine packets PC Send packets to EVM by script Packets send to EVM DSP Waiting and receiving packets from EMAC DSP PA match MAC address and receive by CPPI/QMSS DSP Verify packets and exit PA only match MAC destination address to decide whether receive the packet or not in this example Use Ethernet sniffer software (WireShark) to check whether the script sent on the right device or not Example code provide ALE entry print function, which can be used for checking EMAC routing information 23