A Scalable and High Capacity All-Optical Packet Switch: Design, Analysis, and Control

Transcription

1 Photonic Network Communications, 3:1/2, 101±110, 2001 # 2001 Kluwer Academic Publishers. Manufactured in The Netherlands. A Scalable and High Capacity All-Optical Packet Switch: Design, Analysis, and Control Ti-Shiang Wang, Sudhir Dixit Nokia Research Center, 5 Wayside Road, Burlington, MA {ti-shiang.wang, sudhir.dixit}@nokia.com Received August 25, 2000; Revised November 8, 2000 Abstract. In this paper, a modular and scalable all-optical packet switch (AOPS) is proposed. The range of its capacity can be easily scaled from gigabit per second to multi-terabits per second. Due to its broadcast-and-select property, the proposed AOPS is capable of performing a multicast function. By taking the advantage of wavelength division multiplexing (WDM), this architecture can provide the best network performance using a limited number of optical ber delay lines as buffers. To perform the header replacement function, a novel all-optical header replacement unit (HRU) is introduced to be integrated with the switching function. The proposed HRU is shared by all the inputs which provides cost advantages. In addition, we present a generic control scheme for the proposed AOPS. To implement the function of the AOPS, two possible approaches, based on the design of wavelength conversion pools (WCPs), are presented and their cascadability performances are compared. Our simulations show that the proposed AOPS with an arrayed waveguide grating (AWG) based WCP provides better cascadability performance than the one with a star coupler based WCP. We conclude that, based on the status of current optical and electronic technologies, the proposed architecture is feasible to be implemented, and can be a good candidate for future packet switching solutions. Keywords: all-optical packet switch, wavelength division multiplexing (WDM), header replacement unit (HRU), optical buffers 1 Introduction The explosive growth in traf c in the Internet has put tremendous pressure on the telecommunication networks for more capacity. As the data traf c increases dramatically, packet switching is poised to take over circuit switching since it can deliver services far more cost-effectively and exibly. On one hand, electronic packet switches and routers, including the accompanying technologies of internet protocol (IP) and asynchronous transfer mode (ATM), will get faster and process hundreds of thousands of ows with service-level-guarantees. On the other hand, the huge bandwidth of optical ber ( * Tb/s) and advanced wavelength division multiplexing (WDM) technologies, such as erbium-doped ber ampli er (EDFA), planar lightwave circuit (PLC) and optoelectronic integrated circuit (OEIC), have been considered as the emerging solution to break the overhead of network layers to provide multiple services in an ef cient way [1]. That is, transparent services will provide the advantage for system network operations and fast service provisioning in the near future. As shown in Fig. 1, EDFA played a pivotal role in accelerating the deployment of point-to-point WDM in long haul applications. With the advent of optical add/drop multiplexers (OADMs), which enable adding and dropping of the local traf c, WDM deployment in the metropolitan area network (MAN) is currently receiving a lot of attention. With migration toward an IP optical networking backbone, terabit packet switches will support the very high bandwidth demand of future networks. In other words, modular and scalable terabit packet switches are not only for high bandwidth required in the backbone networks but are also capable of bridging the gap between backbone and access networks to provide the end-to-end services of the future. Thus, how to design a scalable and high-speed terabit packet switch (called optical packet switch) using WDM technology is one of the most active and important research topics in both the industry and the academia. Much research has been done on optical packet switching design [2±16]. However, to provide transparent services in the next generation WDM network, there still are several challenging issues when building optical packet switches (OPS). One of the challenging issues concerns buffering. In general,

2 102 T.-S. Wang, S. Dixit/A Scalable and High Capacity All-Optical Packet Switch Fig. 1. Evolution scenario of WDM networks. OPS can be categorized as transparent or opaque depending upon whether the payload is processed optically or electronically, as shown in Fig. 2. Transparent OPS are a major advance on bit rate/ signal format independence, network integration, and operational simplicity. That is, in the transparent OPS, packets are allowed to bypass extensive electronic signal processing at intermediate switching nodes. On the other hand, in an opaque OPS, the payload of each incoming packet is regenerated electrically at each switching node. Transponders, which perform opticalto-electrical (O/E) and electrical-to-optical (E/O) function, clean up the signal and provide wavelength interchange. However, in the switching core that uses opaque switches, either optical or electronic switching fabrics can be used to perform switching. As contention occurs when multiple packets are destined to the same output port, an OPS without Fig. 2. Categories of optical packet switches. buffering scheme either relies on de ection or on wavelength conversion to solve the contention problem. De ection makes the contending packet(s) to be rerouted to other available output port(s) and the sequencing and/or the service requirements of the packets are controlled by the higher layer protocol (e.g., the TCP layer). Alternatively, wavelength conversion technique is used to switch all the contending packets to different wavelengths so that these packets do not experience wavelength con icts at the same output port. In the opaque OPS, transponders can, at the same time, perform wavelength conversion and reshaping of the incoming packet electronically. On the other hand, each transparent OPS uses all-optical wavelength converters to perform wavelength conversion in the switching node. Another approach for dealing with the issue of contention is to use buffers to store the contending packet(s). Due to the opacity of the opaque OPS, electronic buffering is integrated with the transponder and placed at either the input or the output of the switching node. On the other hand, unlike electronic buffers with mature logical functions and signal processing, optical buffers are implemented by delaying the transmission time of optical packets by ber delay lines. For the transparent OPS, two kinds of optical buffers have been proposed: ber delay lines [3,5±9] and buffer loops [2,4,17±22]. Optical buffers based on ber delay lines are used to stagger the incoming contending packets into different ber delay lines. On the other hand, considering optical buffers based on a random access scheme, all of the packets with different wavelengths share the same ber delay line and optical switching gates (e.g., semiconductor optical ampli er (SOA) gates or electroabsorption (EA) modulators) are controlled to provide optical signal ampli cation and selection of the packets which should be switched out of the optical buffer. Though this approach provides the advantage of sharing the physical infrastructure compared to optical buffers using ber delay lines, the buffering time (or the number of circulations) of packets in the random access buffer is limited because of the ampli ed spontaneous emissions (ASE). Furthermore, this limits its overall switching capacity, even though low loss optical multiplexers or demultiplexers (e.g., arrayed-waveguide grating (AWG) router) and gain-clamped SOA gates are suggested [23].

3 T.-S. Wang, S. Dixit/A Scalable and High Capacity All-Optical Packet Switch 103 In addition to providing the buffering function, the placement of these buffers will be critical in determining the performance of the network in terms of throughput and delay. Several opaque OPSs using optical interconnection networks (OINs) have been proposed [10±16]. That is, the OIN is designed to interconnect electronic switches/routers at both input and output sides. In this approach, electronic buffers are inherently placed at the input and output ports of the OIN. To achieve the best throughput/delay performance, fast arbitration schemes are required to overcome head of line (HOL) blocking [12,16]. The OIN-based OPS derives strength from electronic logical operation and avoids the issues of optical buffering as mentioned above. However, somewhat complicated and centralized electronic controls are required so that the control complexity increases. Furthermore, OIN based OPSs do not have the capability of providing transparent services in terms of data rates and protocols. To support future optical packet switching networks, the capability of packet header replacement must be implemented in the switching node as well. To perform this function optically, several ideas have been proposed either in the wavelength [24] or in the time domain [25,26]. In the former approach, wavelength converters are used to perform header replacement and wavelength conversion simultaneously. However, this approach involves more components and control complexity. In the latter approach, extra processing overhead and complexity are experienced. In this paper we propose a scalable terabit AOPS. In other words, the range of its capacity can be easily scaled from gigabit per second to multiple terabits per second. With limited optical buffers at the output ports, our proposed architecture can achieve excellent throughput/delay performance. We also analyze the buffer size and component complexity with respect to the available wavelengths. To perform the header replacement function, we introduce a novel all-optical header replacement unit integrated with the switching function. To ensure transparent services in the future, the cascadability of the proposed AOPS is evaluated. The paper is organized as follows. Section 2 introduces the proposed architecture. In Section 2.1, two types of wavelength conversion pools are introduced followed by a presentation of the design of sub-optical switching fabric (sub-osf). This is followed by an investigation of the size of optical buffers needed with respect to the available wavelengths in Section 2.2. In Section 2.3 we introduce our proposed header replacement unit, and discuss the advantages of its placement in the switching node and describe its operation. Section 2.4 discusses the cascadability of the proposed AOPS and, in Section 2.5, a generic electronic control scheme is presented. Finally, conclusions are presented in Section 3. 2 Architecture In Fig. 3, we show a generic optical packet switch architecture. Basically, each optical switching architecture consists of four subsystems: input port interface (IPI), optical switching node (OSN), output port interface (OPI), and electronic controller. Depending on the architecture, both the IPI and the OPI perform one or more of the following functions: buffering, synchronization, packet delineation, header processing and updating, and optical or optoelectronic conversion. The OSN is controlled by an electronic controller to perform the switching function and to route optical packets to their destinations. In this paper, we will focus on the design and analysis of OSN and its electronic control scheme. The OSN plays an important role in routing the packets, and the electronic controller resolves any contention in real time. The design of OSN depends on the switch requirements, the maturity in technology of the optical devices, and the contention approach used in the switch. Some optical switching Fig. 3. A generic optical packet switch architecture.

4 104 T.-S. Wang, S. Dixit/A Scalable and High Capacity All-Optical Packet Switch Fig. 4. A generic proposed all-optical packet switch with W suboptical switching fabrics. devices with fast switching speeds, such as SOA gates, lithium niobate switches and optical external modulators, have been considered for use in future optical packet switching applications. Thanks to current advanced OEIC and PLC technologies, optical active components (e.g., laser diodes, SOA gates and optical modulators) and passive devices (e.g., optical couplers, and optical multiplexers/demultiplexers) can be monolithically integrated in the same package or substrate. These technologies enable a wide variety of functions that will be required in building the OSN, and provide cost minimization. Further, the reliability of the OSN can be enhanced as well. As far as the OSN is concerned, Fig. 4 depicts a generic architecture of the proposed N6N AOPS with W wavelengths at each incoming/outgoing ber. Generally speaking, the optical switching fabric (OSF), which performs the switching function optically, consists of N wavelength converter pools (WCPs) and W sub-osf's. Each WCP is controlled to balance the traf c load (or distribute the incoming wavelengths evenly) in the whole network and is shared by all the sub-osf's. Each sub-osf performs the switching function with respect to its corresponding wavelength, and consists of a non-blocking switching fabric (NSF) and optical delay lines as buffers. This modular architecture has the advantage of scaling the capacity in the range of terabit levels. For example, assuming the switch size of N ˆ 16, available wavelengths, W ˆ 32, and data rate of each wavelength, S ˆ 2:5 Gb/s, the total capacity is N6W6S ˆ 1:28 Tb/s. Fig. 5. Star coupler based wavelength conversion pool. wavelength conversion [27]. Basically, each WCP performs not only the wavelength conversion function but also distribute the incoming traf c evenly to all sub-osf's. That is, any incoming wavelength or traf c from any input ber link can be wavelengthconverted to another wavelength and switched in the sub-osf. There are two types of WCPs presented in this paper. One is the star-coupler based WCP (i.e., SC- WCP) and the other is the arrayed-waveguide grating based WCP (i.e., AWG-WCP). Without losing generality, we consider W ˆ 16 here. In the SC- WCP, as shown in the Fig. 5, the incoming wavelength is wavelength-converted to its speci c sub-osf through its tunable wavelength converter, and then broadcast to all of the output ports of star coupler. Then, a xed grating device used at the output port lters out the converted wavelength, followed by switching in the sub-osf. Compared to the SC-WCP, the AWG-WCP given in Fig. 6 incurs less power loss. For the AWG-WCP, the incoming wavelength is wavelength-converted through a tunable wavelength 2.1 Wavelength Converter Pool (WCP) All-optical wavelength-conversion techniques based on SOA gates are proving to be most promising for Fig. 6. Arrayed-waveguide grating based wavelength conversion pool.

5 T.-S. Wang, S. Dixit/A Scalable and High Capacity All-Optical Packet Switch 105 Fig. 7. A generic architecture of a sub-osf. converter at the input port to the speci c sub-osf based on the routing connection of the AWG. At the output of the AWG, a wavelength is then converted by a xed wavelength converter and sent to the sub-osf. Fig. 9. Plot of packet loss probability versus buffer size N; r ˆ 16; 0:8, with different number of available wavelengths. 2.2 Sub-OSF Architecture Fig. 7 shows a generic architecture of a sub-osf. Basically, each sub-osf provides the broadcast-andselect function to all output switching modules (OSMs). Each OSM is individually controlled by an electronic controller to perform the switching function, see Fig. 8. Thus, the proposed switch is capable of providing multicast functionality as well. At each OSM, there is a non-blocking switching fabric (NSF) and several ber delay lines used as optical buffers. Because of output buffering, the proposed switch could achieve very good throughput/delay performance. Control signals from the electronic controller are required to control the SOA gates in the NSF to stagger the incoming wavelengths (or packets) to the optical buffers if multiple inputs are destined for the same output. Fig. 9 shows simulation results on the packet loss probability with respect to buffer size (or the depth of Fig. 8. An architecture of an OSM with optical delay lines as buffers at each sub-osf. the ber delay line) at each OSM. For simplicity, it is assumed that the packet arrivals to each input are independent and with identical Bernoulli process. Based on the simulation results, it is concluded that the probability of packet loss reduces as the number of available wavelengths increases while also decreasing the size of optical buffers at each OSM. For example, when the switch size is 16 ports N ˆ 16, the traf c load is 0.8 r ˆ 0:8 and the available wavelengths are 4 W ˆ 4, an optical buffer of depth 9 m ˆ 9 is suf cient to achieve a packet loss probability of Furthermore, the size of the SOA gates at each OSM is also reduced when the number of available wavelengths is increased. Here, we recommend gainclamped SOA gates [23] because they are capable of providing high speed switching functionality ( * ns) in order to achieve high transmission ef ciency and to support optical ampli cation simultaneously. 2.3 Header Replacement Unit To support future optical packet switching networks, a packet header replacement capability will be required. To perform this function optically, several proposals have been made [24±26]. However, in our opinion, very limited work has been done to integrate the header replacement function with the packet switching function. In this section, a novel header replacement unit (HRU) is proposed and its operation is integrated with the proposed switching function. In Fig. 10, the proposed HRU is placed at the output of each OSM.

6 106 T.-S. Wang, S. Dixit/A Scalable and High Capacity All-Optical Packet Switch Fig. 12. An architecture of a proposed header replacement unit (HRU). Fig. 10. Placement of a proposed header replacement unit (HRU). At each input of the OSM, a small part of the optical power is tapped and the packet's header information is detected for processing in the electronic controller. Then, based on the header information, the electronic controller sends control signals to control the SOA gates in the OSM to deliver the packets with their old headers to the speci c ber delay lines. When packets are sent to the output ports in the sequence of the packet time slots, T, their new header information is updated through the HRU. For example, in Fig. 11, before performing the new header replacement function, each packet is attached with its old header information (as shown at positions A and B). Then, the packet buffering/switching and the erasure of the old header can be performed simultaneously by controlling the SOA gates, as shown at position C of Fig. 11. This logic function and clock control function can be easily implemented in the electronic controller. At each packet time slot, only the payload of a packet is presented (as shown at position D) and its new header is updated in the HRU (as shown at position E). Fig. 12 shows an architecture of a proposed HRU where a small amount of ber delay line (i.e., with the length of T_NH) is reserved for delaying the payload for updating the new header. A xed laser associated with a high-speed optical modulator (i.e., EA modulator or SOA gate) is controlled to modulate the new header using the electronic controller. Our proposed HRU at each OSM has the following advantages. First, each HRU is shared by all inputs destined to the same output port. It provides cost advantages. Second, with the robustness of the logic function supported by the electronic controller, the erase function of the old header can be performed along with the packet switching function. It means that the complexity of the HRU is reduced and the overhead processing avoided [25]. In addition, the simplicity of the proposed HRU architecture renders it to be implemented with current technology without the complexities of the wavelength converter [24,26]. Fig. 11. Operation of a proposed header replacement unit (HRU) at each output switching module (OSM). 2.4 Evaluation and Comparison of Cascadability In addition to performing fast switching functionality and wavelength conversion, SOA gates are used for compensating the power loss caused by passive components and the insertion loss between optical components. Nevertheless, the ampli ed spontaneous emissions generated by SOA gates will degrade the signal-to-noise ratio. To evaluate the cascadability of the proposed AOPS, we consider AOPS with both the SC-WCP and the AWG-WCP. In addition, we adopt the data from Wang and Dixit [15] and assume that the noise is Gaussian distributed and the total output power at each stage is the same. Thus,

7 T.-S. Wang, S. Dixit/A Scalable and High Capacity All-Optical Packet Switch 107 P total;n ˆ P ase;n P sig;n ˆ P in ˆ 0 dbm P ase;n ˆ n6p6n sp 6 G SOA 1 6hv6B 0 ; 1 2 where P total;n ; P ase;n ; P sig;n and P in are the total power, the ampli ed spontaneous emission power, the average routing signal power and the input power at the n-th stage, respectively. In addition, p is a factor whose range is from 1 to 2 according to the polarization insensitivity of the ampli er. In this paper, we assume that all the ampli ers (i.e., SOA gates) are polarization insensitive. In our calculations we set p at 2, N sp which is the excess spontaneous emission factor at between 1 and 5 (for SOA gates this being 3.5), G SOA being the gain of an SOA gate (described later), h being the Planck's constant, and being the center frequency of the ampli er bandwidth. G SOA can be readily computed to be 18 for the AWG- WCP and 25 for the SC-WCP. In Fig. 13, the power experienced by the ASE increases as the number of stage increases so that the power of the dominant routing signal decreases. That is, the ASE begins to grow due to subsequent ampli cation of the attenuated ASE power from the previous stage and the addition of a xed amount of ASE power generated at each stage. The signal power steadily falls as it traverses the chain of stages. The increasing ASE power uses an increasing portion of the gain, and the signal uses the declining remainder of the gain. Eventually, the ASE power would be equal or exceed the signal power if the signal goes through more stages. Thus, the ASE is the dominant noise contributor to the AOPS and it limits the cascadability performance. When we detect light, which is the combination of the signal and the ASE, the mean-squared noise currents associated with the noise introduced by the ASEs are I 2 ase sig ˆ 26I ase 6I sig 6 B e B o 3 Iase ase 2 ˆ Iase6 2 B e ; 4 B o where B e and B 0 are the electrical bandwidth of the receiver and the optical bandwidth of the optical lter, respectively. The currents experienced by the ASE and routed signal are expressed as I ase ˆ R6P ase I sig ˆ 26R6P sig ; 5 6 where R is equal to Z6e h6v and is the responsivity of the detector at the ASE wavelength. The signal wavelength, P ase, is the ASE power in the optical bandwidth B 0 at the receiver, and P sig is the average signal power at the receiver, i.e., P sig ˆ P1 P 0 2, where P 1 and P 0 are power values for logical-one and logical-zero, respectively. By de ning the ratio of the optical bandwidth to the electrical receiver bandwidth as R B ˆ B0 B e 7 and the ratio of the ASE power to the signal power as R ase ˆ Pase P sig ; 8 the value of the Q-parameter at the receiver, which is related to the achievable BER at the receiver, is given by Fig. 13. Power distribution of signal and ampli ed sponeous emission vesrsus number of switching nodes with respect to different WCP implementations. I sig Q ˆ p p I 2 N1 BER ˆ I 2 N0 9 Q 1 erf p ; 10 2 where IN1 2 I2 N0 is the noise in the receiver when a logical-one (logical-zero) is received. Assuming that Gaussian noise and only the ASE-signal and ASE-ASE beat noises are considered,

8 108 T.-S. Wang, S. Dixit/A Scalable and High Capacity All-Optical Packet Switch p 2 R Q ˆ p B R ase 11 4R ase R 2 ase Using (1) through (11), Fig. 14 shows the relationship between the bit error rate and the number of the proposed AOPS. From the results of Fig. 13 and Fig. 14, it can be concluded that the proposed AOPS with the AWG-WCP provides better cascadability performance compared to those with the SC-WCP. Furthermore, the AOPS with the AWG-WCP has a lower ASE effect due to less gain required to compensate for the power loss. For example, for a given BER of 10 12, about twelve AOPSs with the Fig. 15. Control diagram of the proposed AOPS. AWG-WCP can be achieved whereas only three AOPSs with the SC-WCP can be achieved. 2.5 Generic Control Diagram As a key building block of the proposed AOPS, the OSM performs the optical switching function. In this section, we discuss the control of each OSM. When packets from multiple inputs are destined for the same output port, the write-in procedure is controlled such that they sequentially reach the optical buffers so as not to be out of sequence at the output port. The readout procedure consists of delivering the speci c packet to the output and updating its new header at the HRU. As shown in Fig. 15, the output signal at each input line is tapped and converted to an electronic signal. It is then fed to the packet delineation circuit that nds the boundary, controls the synchronization unit to adjust the arriving packet delay to align with a local packet clock, and extracts old header (OH) value. Here, we use content addressable memory (CAM) as the input port table. The output address pattern (OAP) information is read out from the input port table, compared with the local output address (LOA) and then the result is fed to the output address bus. The OAP data is a list map of output ports. When the bit is set to ``1'', it means that the packet is destined for the associated output port. For a multicast packet, multiple bits can be set to ``1''. The LOA is also a list map of output ports, but only one of them is set to ``1'' for its speci c output port, and the others are set to ``0''. If the bit in the OAP matches the LOA, it means that the packet will be sent to this output port. The compared result of the OAP and the LOA will be used as a write signal for the occupied address of rstin- rst-out (OA-FIFO), where the occupied information of optical ber delay line is buffered. Meanwhile, the idle address information at the head of line (HOL) is also used as an address to write the arriving packet's OH value into a random access memory (RAM), called OH RAM. The OH is then used at the output side to access a new header (NH), which is in the NH CAM. Fig. 14. Bit error rate versus number of optical switching nodes with respect to different WCP implementations Write-In Procedure As shown in Fig. 15, the OH value is latched at a register. A global counter controls the sequence of writing and reading packets into and out of the optical ber delay lines. It counts from 1 to N in one packet time slot, T. Let us call the short interval slot as minislot, T=N. In a packet time slot T, OH values are used to look up a table for each input port, where the OAP information is buffered. To keep track of the incoming packets accessing the optical bers, a FIFO (as shown

9 T.-S. Wang, S. Dixit/A Scalable and High Capacity All-Optical Packet Switch 109 in the Fig. 15) which is used to store the available ber delay line (A-FDL) information, is called idle address FIFO (IA-FIFO). The A-FDL is used to control the states (``ON'' and ``OFF'') of the SOA gates so that the incoming packets can be written to the A-FDLs simultaneously. In the meantime, the A-FDL information is used as the write signal and the OHs of the incoming packets are stored in the OH-RAM. In addition, the A-FDL is written to the OA-FIFO and named as occupied ber delay line (O-FDL), which stores the occupied information of the optical ber delay line at each output switching module (OSM) Read-Out Procedure In the read-out procedure, the HOL O-FDL information is read out. This means that the packet buffered in the optical ber delay line is ready to be read out from the OA-FIFO. Meanwhile, the HOL of the O-FDL is used as a read address to access the OH of this readyto-go packet and written back to the IA-FIFO for future use. Once this OH is extracted from the OH RAM, it is used as a read address to access its corresponding new header, which is stored in the NH CAM. Then, the new header is used to control the HRU and perform the header replacement function optically. 3 Conclusion In this paper, a modular and scalable terabit all-optical packet switch architecture is presented. The range of its capacity can be easily scaled from gigabit per second to multiple terabits per second so that it will t the ``pay-as-you-go'' model in the application. With limited number of optical buffers at the output ports, our proposed architecture can achieve the best throughput/delay performance and provide multicast function as well. We also analyzed the buffer size and component complexity with respect to available wavelengths in the switch. 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10 110 T.-S. Wang, S. Dixit/A Scalable and High Capacity All-Optical Packet Switch [17] M. Calazavara, et al., Optical- ber-loop memory for multiwavelength packet buffering in ATM switching applications, Proc. of OFC/IOOC'93, Paper TuE3, (1993), pp. 19±20. [18] W. Pieper, et al., Crosstalk in a ber-loop optical buffer, Proc. of OFC'94 Technical Digest, Paper ThD1, (1994), pp. 194± 195. [19] G. Bendelli, et al., Photonic ATM switch based on a multiwavelength ber-loop buffer, Proc. of OFC'95 Technical Digest, Paper Wj4, (1995), pp. 141±142. [20] G. Bendelli, et al., Performance assessment of a photonic ATM switch based on a wavelength-controlled ber loop buffer, Proc. of OFC'96, Paper WD1, (1996), pp. 106±107. [21] Y. Chai, et al., Optical DRAMS using refreshable WDM loop memories, Proc. of ECOC'98, vol. 1, (1998), pp. 171± 172. [22] M. Calzavara, et al., Simultaneous buffering of ATM packets in a multiwavelength optical- ber-loop memory, Proc. of OFC'94, Paper ThD2, (1994), pp. 195±196. [23] S. L. Danielsen, et al., Detailed experiment and theoretical investigation and comparison of the cascadability of semiconductor optical ampli er gates and gain-clamped semiconductor optical ampli er gates, Proc. of OFC'98, vol. 2, (1998), pp. 41±42. [24] E. Park, D. Norte, A. E. Willner, Simultaneous all-optical packet header replacement and wavelength shifting for a dynamically-recon gurable WDM network, IEEE Photonic Technology Letters, vol. 7, no. 7, (July 1995), pp. 810±812. [25] J. Spring, R. M Fortenberry, R. S. Tucker, Photonic header replacement for packet switching, Electronics Letters, vol. 29, no. 17, (August 1993), pp. 1523±1525. [26] X. Jiang, X. P. Chen, A. E. Willner, All optical wavelength independent packet header replacement using a long CW region generated directly from the packet ag, IEEE photonic technology Letters, vol. 10, no. 11, (November 1998), pp. 1638±1640. [27] S. J. B. Yoo, Wavelength conversion technologies for WDM network applications, J. Lightwave Technol., vol. 14, no. 6, (June 1996), pp. 955±966. Ti-Shiang Wang received the B.S. and M.S. degree from Automatic Control Engineering, Feng Chia University, Taiwan, in 1986 and He received the Ph.D. degree from Electrical Engineering, Polytechnic University, New York, USA, in He has served as a lecturer in Nan-Kai Institute of Technology, Taichung, Taiwan, during From 1991 to 1998, his works were focused on control theory, detection and estimation, digital signal processing and optical packet switching systems areas. Since 1999, Dr. Wang has been working as a senior research engineer and a project manager in Nokia Research Center, Boston, USA. His areas of works are currently engaged in the research and development of IP and WDM networks, optical access networks and terabit optical packet switches. Dr. Wang has published more than 20 papers in conferences and journals, and also has one patent granted in the optical networking area. Dr. Wang is a member of IEEE. Sudhir Dixit received the B.E. degree from Maulana Azad College of Technology (MACT), Bhopal, India, the M.E. degree from Birla Institute of Technology and Science (BITS), Pilani, India, and the Ph.D. degree from the University of Strathclyde, Glasgow, Scotland, all in electrical engineering. He also received the M.B.A. degree from Florida Institute of Technology, Melbourne, Florida. Dr. Dixit is currently a Senior R&D Manager and a Site Manager at Nokia Research Center in Burlington, Massachusetts. His areas of interest are ATM, Internet, optical networks, and 3rd Generation mobile networks. From 1991 to 1996 he was a broadband network architect at NYNEX Science and Technology (now Verizon Communications). Prior to that he held various engineering and management positions at other major companies, e.g., GTE, Motorola, Wang, Harris, and STL (now Nortel Europe). He has published extensively, given invited talks/ panels, and has sixteen patents either granted or pending. He has served in various capacities in several conferences, and has also been an ATM Forum Ambassador since He has served as a guest editor in IEEE Network and IEEE Communications Magazine. Currently, he is a Lightwave Series editor of the IEEE Communications Magazine. He is listed in numerous Who's Who publications.