Hybrid Optoelectronic Router

Transcription

1 Hybrid Optoelectronic Router Ryohei Urata, Tatsushi Nakahara, Hirokazu Takenouchi, Toru Segawa, Ryo Takahashi NTT Photonics Laboratories, NTT Corporation Supported in part by the National Institute of Information and Communications Technology (NICT)

2 Electrical Routers 2m Multi-rack Router System SWITCHES Reproduced with permission of Nick McKeown, Stanford University LINECARDS Power (kw) Power consumption per rack/chassis For 92 Tb/s: 80 racks >1 MegaWatt Need to Reduce power consumption Reduce size Increase performance - Increase throughput - Increase traffic engineering capability

3 Problem with Electrical Routers Header Processing Buffering Switching Line Card Line Card Electrical Switch O/E E/O O/E E/O O/E E/O O/E (DEMUX) CMOS Buffer & Processor (MUX) E/O : Serial-to-Parallel Converter : Parallel-to-Serial Converter Optical Electrical Optical Excessive buffering and processing Problems at the interfaces (MUX/DEMUX) - High power consumption - Speed limited by electronic components

4 Photonic Router Electrical Router High Capacity Low Power Compact Low Latency Photonic Router Novel optical device and subsystem technologies for processing burst packets New router architecture incorporating optical technologies Buffering Label Proc. Switching

5 Hybrid Optoelectronic Router Node Architecture

6 Node Architecture Label processor Optical switch RAM Shared buffer Drop Add No contention Contention Passes through transparently Forwarded to shared buffer

7 Node Architecture Label processor Optical switch CMOS Shared buffer Drop Add Contention Resolution 10 Gbit/s IP packet 1 st : To the Desired Port 2 nd : Buffering in CMOS 3 rd : Wavelength Conversion 4 th : Deflection Routing

8 Node Architecture Label processor Optical switch RAM Shared buffer Drop Add Buffering in CMOS RAM Traffic engineering between wavelength layers 3R regeneration based on TTL

9 Node Architecture Label processor Optical switch RAM Shared buffer Drop Add Buffer supports various services QoS,, FEC, Multicast routing, Policy routing

10 Sub-Systems

11 Label Processor Label processor Optical switch CMOS Shared buffer Drop Add

12 Label Processor Sub-System 1x2 SW trigger trigger ECG splitter + delay lines PD Serial-to-Parallel Conversion () fiber array OCTA Parallel-to-Serial EA-DFB Conversion () Packet Envelope Detection N bits IN CMOS Scheduler N bits OUT Control Signals for Switch ECG: Electrical Clock-Pulse Generator, OCTA: Optically Clocked Transistor Array Detect input label, packet envelope Process label, configure switch Merges,, clock generation for compact, low-power system

13 Optical Switch Label processor Optical switch CMOS Shared buffer Drop Add

14 Optical Switch Sub-System TWC FWC TWC TWC N N FWC FWC Control Signals from Scheduler DRR-TLD LN Mod APD-TIA Label Swapped Packet APD-TIA TWC, FWC: Tunable, Fixed Wavelength Converter DRR-TLD: Double-Ring-Resonator-Coupled Tunable Laser Diode EA-DFB N N N non-blocking switch for packet-level switching Low power, compact, fast switching, scalable

15 Shared Buffer Label processor Optical switch CMOS Shared buffer Drop Add

16 Shared Buffer CMOS Drop : Serial-to-Parallel Conversion : Parallel-to-Serial Conversion Add Selective buffering, high-level packet functions Asynchronous burst mode compliant, low power, CMOS functionality

17 Conclusion Optical Technology + Electrical Technology Photonic Router Optical technologies for high-speed burst packet processing Node architecture for transparency and high functionality Optically Clocked Transistor Array (OCTA) Double-Ring Resonator Tunable Laser All-Optical Serial-to-Parallel Converter () Optical Clock-Pulse Pulse-Train Generator (OCPTG)