Physical Design Closure

Transcription

1 Physical Design Closure Olivier Coudert Monterey Design System DAC 2000 DAC2000 (C) Monterey Design Systems 1 DSM Dilemma SOC Time to market Million gates High density, larger die Higher clock speeds Long wires Project management Re-use, IPs Larger database Larger design space Need abstraction levels to manage complexity Abstraction Accuracy DSM Higher resistance Higher crosscoupling Non-linear timing Power Electromigration IR Drop Inductances etc... Require detailed analyses to understand physical interactions DAC2000 (C) Monterey Design Systems 2 1

2 Top 10 Impediments to Design Closure Strong placement/timing dependency Timing/congestion interaction Timing signoff Signal integrity Power design Problem size Computational resources Clock design Modeling accuracy Marketing hype DAC2000 (C) Monterey Design Systems 3 Top 10 Impediments to Design Closure Strong placement/timing dependency Timing/congestion interaction Timing signoff Signal integrity Power design Problem size Computational resources Clock design Modeling accuracy Marketing hype DAC2000 (C) Monterey Design Systems 4 2

3 Timing & Placement Interconnect dominance makes DSM netlist signoff difficult Wireload models were ALWAYS inaccurate Post-synthesis signoff was possible when interconnect contributed ~20% of the total capacitance But now the interconnect-c is becoming dominant over the total-c with each new process generation Wire Cap. (ff/um) DAC2000 (C) Monterey Design Systems 5 Long-Wire Problems For DSM designs the metal resistance further complicates timing prediction and closure for the global wires Average long-wire length is not scaling with new technologies since the systems are becoming bigger Local wires Occurrence Rate (Normalized) Global wires ~0.5 wire length die size DAC2000 (C) Monterey Design Systems 6 3

4 Top 10 Impediments to Design Closure Strong placement/timing dependency Timing/congestion interaction Timing signoff Signal integrity Power design Problem size Computational resources Clock design Modeling accuracy Marketing hype DAC2000 (C) Monterey Design Systems 7 Placement Quadratic placement fast restricted cost function, e.g., timing driven placement mimicked with net weighting Simulated annealing open cost function extremely slow Force directed semi-open cost function slower than quadratic placement tuning more difficult Bisection (mincut + partitioning) open cost function slower than quadratic placement DAC2000 (C) Monterey Design Systems 8 4

5 Netlist Clustering Start placement by building a hierarchical tree of cell-clusters from the netlist (hmetis DAC 97) A key to optimal placement is to optimize the size and locations of these clusters Both functional hierarchy and netlist topology need to be considered Netlist A B C D E F DAC2000 (C) Monterey Design Systems 9 Placement The clusters are sized and placed within partitions and among megacells Long wires are modeled among partitions, and congestion is approximated within partitions Initially, congestion is dominated by local wires Early wireplanning for long wires will not work DAC2000 (C) Monterey Design Systems 10 5

6 Placement This process continues to smaller clusters and smaller partitions Long wires are not planned, but are placed probabilistically in terms of where the router is likely to want to route them DAC2000 (C) Monterey Design Systems 11 Placement This process continues to smaller clusters and smaller partitions Long wires are not planned, but are placed probabilistically in terms of where the router is likely to want to route them DAC2000 (C) Monterey Design Systems 12 6

7 Placement This process continues to smaller clusters and smaller partitions Long wires are not planned, but are placed probabilistically in terms of where the router is likely to want to route them DAC2000 (C) Monterey Design Systems 13 Placement One eventually reaches a cluster and partition size for which timing and congestion are predictable Timing signoff can be done at this level ONLY! DAC2000 (C) Monterey Design Systems 14 7

8 Top 10 Impediments to Design Closure Strong placement/timing dependency Timing/congestion interaction Timing signoff Signal integrity Power design Problem size Computational resources Clock design Modeling accuracy Marketing hype DAC2000 (C) Monterey Design Systems 15 Placement Cells are non uniformily distributed into bins Dynamic whitespace allocation addresses congestion at the global level DAC2000 (C) Monterey Design Systems 16 8

9 Placement Cells are nonuniformily distributed at subfloorplan level Dynamic whitespace allocation addresses congestion at the global level Inter- and intra-partition congestion is predictable at this placement level DAC2000 (C) Monterey Design Systems 17 Non-Uniform Whitespace Mgmt. Example of whitespace allocation after timing driven placement and optimization White Space addedto relieve congestion White Space addedto relieve congestion White Space removed to help relieve congestion in other areas Movement of cells for timing optimization DAC2000 (C) Monterey Design Systems 18 9

10 Placement The placement algorithm generality and common database provide for the front-to-back logic optimization, control of wiring, etc These same features provide for powerful ECO capabilities too Netlist can be adjusted via API at all levels of the placement progression Design progress can be viewed and manipulated at every placement level DAC2000 (C) Monterey Design Systems 19 Top 10 Impediments to Design Closure Strong placement/timing dependency Timing/congestion interaction Timing signoff Signal integrity Power design Problem size Computational resources Clock design Modeling accuracy Marketing hype DAC2000 (C) Monterey Design Systems 20 10

11 Timing Prediction As the routing models become more precise, so do the timing predictions for the long wires The timing/delay models and analyses are only as precise as the physical information New metrics provide excellent correlation from front-end to backend DAC2000 (C) Monterey Design Systems 21 Timing Prediction As the routing models become more precise, so do the timing predictions for the long wires The timing/delay models and analyses are only as precise as the physical information New metrics provide excellent correlation from front-end to backend Intra-partition wiring delays are accurately predicted at this partition size too DAC2000 (C) Monterey Design Systems 22 11

12 Timing Optimization The first tech mapping was an approximation, since the wiring capacitances were not known With sufficient physical information at the placement level, we begin timing optimization Buffers are inserted for shielding, delay and attenuation DAC2000 (C) Monterey Design Systems 23 Timing Optimization Buffers are added only when it is determined that they will not have to be removed Global routing is used to place the buffers and inverters Long wires are seeded by buffers Long wire design is driven by accurate physical information DAC2000 (C) Monterey Design Systems 24 12

13 Top 10 Impediments to Design Closure Strong placement/timing dependency Timing/congestion interaction Timing signoff Signal integrity Power design Problem size Computational resources Clock design Modeling accuracy Marketing hype DAC2000 (C) Monterey Design Systems 25 Logic Optimization Analytical approaches Assume continuous size Fast Map a continuous solution onto a discrete library Use oversimplified models (e.g., Elmore delay) Refinement approaches Can use complex and/or discrete models Can mix a wide range of transformations Slower Strategy/control more difficult DAC2000 (C) Monterey Design Systems 26 13

14 Logic Optimization Placement provides enough physical information to accurately buffer, resize, remap, resynthesize, etc. Yet design is still abstract enough for global exploration E.g.: Logic optimization for global congestion relief Placement is coarse enough that resizing in one region does not require cells to be moved in another More effective than completing a placement, feeding back custom wireload models, and iterating DAC2000 (C) Monterey Design Systems 27 Logic Optimization Buffering targets slope fixing and timing Several algorithm, slack, delay, and slope driven Critical path Shielding buffer for timing optimization 4 5 Buffering can help in reducing congestion too DAC2000 (C) Monterey Design Systems 28 14

15 Logic Optimization More aggressive for critical paths, e.g., logic collapsing and decomposition, logic duplication and logic sharing, logic remapping, logic resynthesis 1 path path 2 both paths 1 & 2 are critical DAC2000 (C) Monterey Design Systems 29 Logic Optimization The generality of the placement algorithm allows logic optimization to continue throughout the flow No net constraints Continual monitoring of what is critical Includes simple logic restructuring for congestion relief: DAC2000 (C) Monterey Design Systems 30 15

16 Top 10 Impediments to Design Closure Strong placement/timing dependency Timing/congestion interaction Timing signoff Signal integrity Power design Problem size Computational resources Clock design Modeling accuracy Marketing hype DAC2000 (C) Monterey Design Systems 31 Clock Distribution Most clock tree synthesis algorithms attempt to build the clock tree post -placement This is too late congestion could disturb timing closure But you can t build it too early, since you don t know where the latches are Synthesis Floorplanning Placement Clock Tree Generation Clock Routing DAC2000 (C) Monterey Design Systems 32 16

17 Clock Distribution The placement should provide enough information to know the distribution of latches, but should be abstract enough to avoid being trapped by congestion caused by the clock wiring DAC2000 (C) Monterey Design Systems 33 Clock Distribution First clock tree is created with the clock pins distribution A complete buffered/gated tree can be automatically synthesized The user has the option to instantiate the top portions of a tree based on the distribution of latches and flipflops DAC2000 (C) Monterey Design Systems 34 17

18 Clock Distribution This clock tree congestion is used to predict the overall congestion, since the latch distribution will not change substantially from this point forward As the lower portions of the clock tree continue to grow, the top levels of the tree take root The top levels will continue to adjust slightly as the placement and optimization processes continue DAC2000 (C) Monterey Design Systems 35 Clock Distribution Accurate timing projections enable useful skew methods to be applied at this level Placement is still coarse enough so that objects with commonskew targets can be grouped DAC2000 (C) Monterey Design Systems 36 18

19 Top 10 Impediments to Design Closure Strong placement/timing dependency Timing/congestion interaction Timing signoff Signal integrity Power design Problem size Computational resources Clock design Modeling accuracy Marketing hype DAC2000 (C) Monterey Design Systems 37 Power/Ground Distribution The placement also provides sufficient information to judge the quality and integrity of the power/ground network Power/ground network can have a huge impact on congestion Power rail currents will not change much as the placement is refined Yet there is enough space to add/widen stripes API driven adjustment using incremental IR-drop analyses Ultimately this optimization process can be automated DAC2000 (C) Monterey Design Systems 38 19

20 Power/Ground Distribution Eventually automation process will have to consider more detailed analysis too: Inductance of chip and packaging Resonance frequencies via ac analyses On-chip decoupling DAC2000 (C) Monterey Design Systems 39 Top 10 Impediments to Design Closure Strong placement/timing dependency Timing/congestion interaction Timing signoff Signal integrity Power design Problem size Computational resources Clock design Modeling accuracy Marketing hype DAC2000 (C) Monterey Design Systems 40 20

21 Model refinement Once the quadrisection level s results are acceptable, we proceed with a similar partition-based placement strategy The cost function includes timing, area, congestion, power, and eventually xtalk and signal integrity There are no timing constraints fed forward! Logic optimization, buffering, whitespace allocation, etc., all continue on a more local scale DAC2000 (C) Monterey Design Systems 41 Design Closure Transformation scale Model accuracy System RTL Synthesis Place Route Logic opt. Extraction & delay calculation Timing Final static timing analysis time global/estimate local/accurate Continuity and correlation are keys! DAC2000 (C) Monterey Design Systems 42 21

22 Top 10 Impediments to Design Closure Strong placement/timing dependency Timing/congestion interaction Timing signoff Signal integrity Power design Problem size Computational resources Clock design Modeling accuracy Marketing hype DAC2000 (C) Monterey Design Systems 43 Pre-DSM Design Flow RTL custom WLM Synthesis Placement Clock Tree statistical WLM timing library logical domain physical domain (SDF, RC s) Netlist Signoff Routing Extraction Delay Calculation Static Timing Analysis DAC2000 (C) Monterey Design Systems 44 22

23 DSM Design Signoff No physical information at that level Timing, congestion, clock, etc, predictable at that level Timing RTL Synthesis + opt. floorplan Remap Route Place Physical implementation Delay Calculation Static Timing Analysis DAC2000 (C) Monterey Design Systems 45 DSM Design Signoff No physical information at that level Timing, congestion, clock, etc, predictable at that level Timing RTL Synthesis + opt. floorplan Remap Route Place Design signoff can only be done when DSM timing & congestion can be properly estimated: physical prototype level Physical implementation Delay Calculation Static Timing Analysis DAC2000 (C) Monterey Design Systems 46 23

24 Top 10 Impediments to Design Closure Strong placement/timing dependency Timing/congestion interaction Timing signoff Signal integrity Power design Problem size Computational resources Clock design Modeling accuracy Marketing hype DAC2000 (C) Monterey Design Systems 47 Routing Requirements for the DSM Router: N-layer shape-based router Supports gridless and gridded routing Variable wire width for optimal delay constraints Cross-talk avoidance, antenna effects Clock tree sizing for tree balancing Power routing sizing for voltage drop and electromigration DAC2000 (C) Monterey Design Systems 48 24

25 Routing Correlation Global routing can utilize the whitespace to avoid long-distance couplings for critical nets Extra spacing, shielding, or space for rip-up and reroute No surprises for the detailed router after GR Shape-based gridless area router Timing and xtalk aware Spacing wires nonuniformily within and among layers is handled without loss of generality Router capabilities are also critical for delay optimization and satisfying reliability constraints DAC2000 (C) Monterey Design Systems 49 Crosstalk Fact: the same layer coupling capacitance is beginning to dominate the total net capacitance Makes cross-talk a dominant factor in achieving timing closure Coupling vs. Inter-layer capacitance Cc/Cs Source: 1998 Update, International Technology Roadmap for Semiconductors DAC2000 (C) Monterey Design Systems 50 25

26 Crosstalk Neighboring-net switching can cause DR surprises Trying to solve this problem at DR is far too late! Passing constraints to Detailed Routing to avoid routing certain nets in parallel is easy, but DR is already overconstrained! The right way is to attack the xtalk problem starting at the proper placement level DAC2000 (C) Monterey Design Systems 51 Crosstalk Delay Impact Simply modeling the coupling capacitance as grounded capacitance scaled by ~2x is overly pessimistic Timer should model early and late arrival times at all nodes (for each library) so that worst/best case switching can be determined during path traversal TACO: Timing Analysis with Coupling (DAC 2000) DAC2000 (C) Monterey Design Systems 52 26

27 Electromigration During clock-tree synthesis, top level wires are automatically sized to satisfy E/M constraints Below 0.25um we expect similar constraints for signal nets Don t wait until DR to determine layer assignments or find extra space for wide wires The wire sizes and layers should be modeled at the earliest possible placement level DAC2000 (C) Monterey Design Systems 53 IR drop P = P net + P int + P leak Simulation and/or probabilistic based dynamic power evaluation Power distribution at the chip level, along with the quadrisection level Consequently power distribution can be optimized along with the other design variables DAC2000 (C) Monterey Design Systems 54 27

28 Top 10 Impediments to Design Closure Strong placement/timing dependency Timing/congestion interaction Timing signoff Signal integrity Power design Problem size Computational resources Clock design Modeling accuracy Marketing hype DAC2000 (C) Monterey Design Systems 55 Moore s Law: Tapering off? Thousands of transistors x in 2 years Merced P.Pro Pentium 2.5 years Year 28

29 Parallel Processing Parallel processing: The process of breaking a problem into multiple pieces and executing them simultaneously Speedup: Let T(n) = wall-clock time for executing the original task on n processors. Then speedup is T(1)/T(n) Speedup depends on: load balancing inter-processor communication scheduling Load balancing Objectives Evenly balance computational loads among available processors Minimize inter-processor communication This is a hard problem Load balancing is a NP-complete! The time taken to load-balance should be a fraction of the total process time 29

30 Job Scheduling 10 independent Jobs, 2 Processors p q p p p p p p p q T(p) = 1 Serial runtime: 8 * * 10 = 28 T(q) = 10 T2 T1 S(2) = Thread scheduling chart Poor scheduling is detrimental for speedup Improving Job Scheduling 10 independent Jobs, 2 Processors p q p p p p p p p q Reschedule q q p p p p p p p p T2 T1 S(2) = Thread scheduling chart Simple scheduling algorithms improve speedup 30

31 Inter-job Communication k jobs 1 2 p q q p Reducing job-communication improves scaling Partition the problem! Global Routing Global doesn t lend itself to parallelism q is a very big portion of each task q = updating of global congestion map Quality vs Speed trade of: Lazy update Multi-level partitioning... k 1 2 p q q p 31

32 Global Routing: Lazy Update Algorithm: Each parallel task gets a list of nets to be routed While routing a net, Global congestion map represents an earlier state After a while, routing stops and congestion map is updated Cons: Quality degradation Possibility of slowing convergence due to delayed congestion map Global Routing: Multi-level partitioning Algorithm: Divide routing area into partitions, at each level partitions are non-overlapping Levels could be 1x1, 2x2, 3x3, 5x

33 Global Routing: Multi-level partitioning Algorithm (cnt d): At each level, routing within partitions can be threaded. Detail Routing Detail Router optimizes local interaction of routes Localized, thus simple partition based threading scheme: Divide chip into small partitions Instantiate router on partitions in parallel Quasi-linear speed-up 33

34 Detail Routing In reality, partitions will be overlapping Better quality near partition boundaries Can not route adjacent partitions concurrently To minimize locks, need a scheduler Speedup (n=4) Global Placement Congestion modeling Static Timing Analysis (with crosstalk) Place - Logic interaction Sizing Buffering Technology mapping Clock generation Power topology construction Detailed placement Global routing (with crosstalk ) Shape-based detailed routing (with crosstalk) 34

35 Top 10 Impediments to Design Closure Strong placement/timing dependency Timing/congestion interaction Timing signoff Signal integrity Power design Problem size Computational resources Clock design Modeling accuracy Marketing hype DAC2000 (C) Monterey Design Systems 69 35