Concurrent, OA-based Mixed-signal Implementation

Transcription

1 Concurrent, OA-based Mixed-signal Implementation Mladen Nizic Eng. Director, Mixed-signal Solution 2011, Cadence Design Systems, Inc. All rights reserved worldwide.

2 Mixed-Signal Design Challenges Traditional model Over the Wall Collaborative model Floorplan Architect Results of World-wide MS ToT survey of 561 attendees; Q Abstract Floorplan Concurrent block design Analog/Custom group group Integration, ECO, Signoff Integration lead Data translation Setup & maintenance for multiple tools Informal communication of design intent Black-box : no visibility in each other domain Sequential design tasks Increased iterations Prolong TAT Costly ECO Sub-optimal design Increased risk of silicon re-spin Common DataBase for analog and digital Unified technology setup Constraints drive design Full transparency of each domain Concurrent design Relative importance Fewer iterations Shorten TAT Effective ECO Quality design Reduced risk of silicon re-spin Cadence Design Systems, Inc. All rights reserved.

3 Weighted Importance Biggest Challenges in MS Implementation World-wide survey of 561 MS ToT attendees, Q Cadence Design Systems, Inc. All rights reserved.

4 Schematic-driven Mixed-signal Flow Evolution Traditional Separate analog and digital environments Black-box/Abstract/GDS level exchange Data translation OA-integrated Analog-centric Unified database no data translation Full visibility into analog and digital, in separate hierarchy Concurrent Highest level of mixed-signal integration instantiated in layout module hierarchy and bind to schematic at the top level Virtuoso 3 rd Party P&R tool Virtuoso EDI Virtuoso EDI OA Proprietary DB OA OA MS architecture and integration 1 st generation 2 nd generation 30% Gain 30% Gain

5 Unified Environment for MS Design Area Better floorplanning No Data translation Virtuoso EDI TAT Effective ECO at any design stage No Data translation Quality of Silicon Avoid re-spins by better timing signoff No Data translation Design constraints passing No Data translation OpenAccess Unified Design DataBase No Data translation Efficiency Maintain one instead of two technology setups Unified Library and Technology setup Cadence Design Systems, Inc. All rights reserved.

6 Mixed-Signal PDK Virtuoso EDI Optional for digital users techlef OA techfile One time consolidation One time effort on consolidating technology information for OA interoperable MS Implementation flows Taking advantage of Incremental Technology Data Base (ITDB) Single, consolidate OA techfile for both Virtuoso and EDI Cadence Design Systems, Inc. All rights reserved.

7 Mixed-signal Implementation Flows A A/d A/D D/A D/a D Methodology Analog-centric Concurrent -centric Design Top level is analog; standard cell contained in block Analog and standard cell digital mixed at same level. Predominantly digital design with analog integrated as macros Top level connectivity Schematic Schematic and Netlist Netlist Verification SPICE; Mixed-signal simulation, analog behavioral models Mixed-signal simulation; behavioral models; Assertions and MDV simulation with RNM; MDV Floor-planning Controlled, constraint driven Control and automation Highly automated, timing, congestion, power driven Analog content Main/Top Co-designed Separate partition content in separate partition Co-designed Main/Top Routing Custom for top and analog.; timingdriven on-grid for digital Combination of custom of-grid and digital on-grid Top level analog by VSR; all other routing by NR. Chip Integration Custom Environment Custom or environment Full-chip Signoff Mixed-signal parasitic simulation STA and/or Mixed-signal parasitic simulation STA Cadence Design Systems, Inc. All rights reserved.

8 OpenAccess DFM AMS IP Implementation Flow Top Level Floorplan RTL netlist Library Constraints Analog/Custom Blocks Top Level Synthesis DFT Test Insertion Floor planning Power Planning Placement Low Power Optimization Chip Integration & Signoff Clock Tree Synthesis Timing optimization Routing Physical Verification Cadence Design Systems, Inc. All rights reserved.

9 Mixed-signal Floorplanning Top Level Floorplan in Virtuoso Encounter and Virtuoso interoperate on refining floorplan using constraints: Pin fixed or locked Halo Density screen Group and region Placement status of an instance Timing driven Placement and pin Optimization Block floorplan in Encounter Cadence Design Systems, Inc. All rights reserved.

10 Mixed-Signal Constraint Interoperability Specification and capture of MS design integration intent Hierarchical manipulation of integration constraints Storage and delivery through OA db Implementation support within both EDI System and Virtuoso Signoff validation using PVS Phase 1 support for MS routing constraints Cadence Design Systems, Inc. All rights reserved.

11 Timing & SI Signoff Analysis for Mixed-Signal Challenge: Full chip STA signoff should cover paths through digital embedded in AMS blocks No visibility into AMS black-box during integration Timing model for AMS blocks are inaccurate, do not account for SI and hard to generate Solution: Bring AMS blocks to EDI system via OA Expose its digital content (instances, layout routing) and stitch it to top level Extract and time full chip design including digital from AMS blocks Perform SI analysis No need for timing (.lib) models for AMS blocks (besides std. cells) Cadence Design Systems, Inc. All rights reserved.

12 ECO steps ECO for Mixed-Signal SoC Design Pre-Mask ECO Flow Analog PCell Stdceell OA Libraries Pre and post mask ECO functionality available in EDI Post-mask use spare cells, and limits eco routing to only specific layers Performed on design s unified OA database Save time by avoiding block level changes and repeating integration Highly automated No manual work EDI does re-mapping Full OA DB Connects the global net Connections for new instances If new Tie Hi/Tie Lo Connections are required Load (OA) design (restoreoadesign) Output and edit Verilog netlist Set OA update mode setoaxmode -UpdateMode true ecooadesign applyglobalnets addtiehilo ecoplace addfiller ecoroute Save design (saveoadesign) Cadence Design Systems, Inc. All rights reserved.

13 Benefits of Cadence MS Implementation Solution Predictability TAT TAT TAT Predictability Predictability Mature, Proven Analog and design platforms Common OA Database and unified technology setup Constraint driven methodology Easy to adopt and use Powerful Floorplanning/Pin-optimization Integrated analysis/signoff Automated ECO flow Strong Ecosystem Ability to serve entire scope (A<>A/d<>A/D<>D/a<>D) Support and Services Modern Mixed-signal design raises new challenges, Cadence is your best partner in addressing them Cadence Design Systems, Inc. All rights reserved.

14 Cadence Design Systems, Inc. All rights reserved.

15 Cadence Design Systems, Inc. All rights reserved.