High-Performance Real-Time Lab (HiPeRT) Marko Bertogna University of Modena, Italy

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1 High-Performance Real-Time Lab (HiPeRT) Marko Bertogna University of Modena, Italy

2 HiPeRT Lab Research on High-Performance Real-Time Systems ~20 people 4 faculties 8 post docs 4 PhD students 3 research collaborators Multiple students > 3MEuro funding Ongoing EU projects: Past EU projects: To start in 2018: PRYSTINE, SECREDAS Industrial collaborations: Confindustria, Mantova - January 9,

3 Research areas High-Performance Embedded Systems Multi-/many-core, GPU, FPGA Next-Generation Real-Time Applications Autonomous Driving, Industrial Automation, Unmanned Aerial Vehicles 3+ million Euros of secured funding in the last 4 years 7 EU projects in the real-time systems and autonomous driving domain Multiple industrial collaborations Industrial automation: Tetra Pak, SACMI, IMA, Neos, etc. Automotive: Maserati, Magneti Marelli, Denso, Bosch, Egicon, Bylogix, etc. Avionic: Airbus, Leonardo, etc. Platform: Nvidia, Xilinx, etc. Others: Doxee, Expert System Copyright of the University of Modena - HiPeRT Lab 3

4 Next-generation Embedded Systems Complex workload-intensive tasks Perception, planning, ML/DNN Latency-critical control tasks Cyber-physical interaction Tight actuation loops Industry 4.0 Cyber-physical systems Artificial intelligence Autonomous driving Robotics Confindustria, Mantova - January 9,

5 Higher performance NECST Seminar - October 20,

6 Bottom-line Use a higher number of slower logic gates Multi/Many-core systems! The number of cores will double every 18 months, while power, clock frequency and costs will remain constant [Patterson & Hennessy] Currently, 4/8 cores are mainline, and counting AMD: 16-core, 32-thread 3.4-GHz Threadripper 1950X Intel: 18-core Core i9-7980x COTS with 256 cores-in-a-chip (Kalray MPPA) GPU, FPGA, TPU Real-time systems are not immune CAST-32a paper Use of multi-core chips with only one core enabled..! Sacrifice performance for predictability NECST Seminar - October 20,

7 Performance vs Predictability Performance-oriented world Highly parallel data crunching applications General purpose operating systems Wide and dynamic library support Optimized for the average case Divergi g eeds Predictability-oriented world Safety critical routines Hard real time requirements Functional safety standards (ISO 26262, DO178c) Qualification/certification (ASIL, DAL) Strict programming practices (MISRA C, AUTOSAR) Optimized for the worst-case NECST Seminar - October 20,

8 The Predictability Challenge Multiple factors may affect predictability: Dynamic control flows (conditional branches, loops, etc.) Concurrency (mutual exclusion, synchronization, shared resources) OS interference (interrupts, I/O, preemptions, context switches, etc.) Hardware (caches, memory hierarchy, OoO engines, pipeline, etc.) Lot of established results for single-core technologies ASIL D platforms/rtos, RT schedulers, Timing analyzers, etc. Multi-core systems are inherently unpredictable Lots of functional and timing inter-dependencies Strongly NP-hard problems Need for Freedom from Interference! Getting worse with increasing number of cores NECST Seminar - October 20,

9 The HERCULES Project: Reconciling Performance and Predictability Industrial-grade framework to provide predictab e performa ce on top of cutting-edge embedded COTS platforms Autonomous driving and UAV use-cases EU funded H hercules2020.eu Confindustria, Mantova - January 9,

10 The CLASS project Duration: 36 month ( ) Budget: European Funding: 100% Fog computing infrastructure for Urban Autonomous driving: a public-private partnership within Modena Automotive Smart Area (MASA) Accurate awareness of road users and obstacles in real-time Distributed traffic monitoring and enforcement in metropolitan areas Enabling technology for advanced AD applications in urban settings V2I obstacle detection, Coordinated intersection crossing, Dynamic traffic signalling, Green routes for public vehicles, Smart parking: free lot detection and valet parking

11 Real-time fog computing system Hundreds of smart cameras installed Cameras are locally connected to a high-performance embedded board (a.k.a. Fog node) Each Fog node elaborates video streams detecting road users in realtime Elaborated information is sent in V2I to vehicles for enhanced perception to L3/L4 autonomous driving Fog nodes are connected to servers receiving data at block level (a.k.a. cluster nodes) Control Room Cluster nodes are fiber connected to main control center

12 Real-time Urban Awareness Infrastructure sensors Real-time detection Low-latency V2I communication In-vehicle sensors Data analytics Public authorities Traffic enforcement Autonomous vehicles

13 Low-latency V2X Communication Infrastructure Predictable communication infrastructure- 4G/LTE 5G enb enb Athonet 4G+ Mobile Core Loca apps MME Loca HSS S-PGW PCRF Application IP N e t w o r k layer Vehicle-to-vehicle V2V Vehicle-toinfrastructure V2I

14 Edge-side: Real-time road user detection Multiple infrastructure cameras detect road users and obstacles vehicles, buses, trucks, pedestrians, bicycles, etc. A consistent representation of RU s is sent to L3/L4 vehicles (V2I) in real-time To cloud infrastructure Camera-to-car < 100ms! V2I sensing system for harsh urban environment Redundant and robust perception Safer obstacle detection

15 Cloud side: Advanced control center Distributed intelligence system for real-time urban awareness Smart city map updated every second Tight reaction time to urban hazards Traffic/parking monitoring & enforcement Emergency vehicle routing

16 Use cases Data analytics Highly valuable dataset for smart urban mobility enforcement and understanding Highly detailed and accurate mobility data Traffic/mobility analysis and prediction Road user behavioural understanding Improved algorithms for autonomous driving Anonimization of data for privacy compliance Implemented at source/edge level Big data analytics developed with IBM, UNIMORE, ATOS, Barcelona Supercomputing Center

17 Thank you! Marko Bertogna