A Performance Modeling and Simulation Approach to Software Defined Radio

Transcription

1 A Performance Modeling and Simulation Approach to Software Defined Radio OMG Software-Based Communications (SBC) Workshop San Diego, CA - August, 2005 Shawkang Wu & Long Ho Integrated Defense Systems The Boeing Company Anaheim, CA

2 Typical M&S Approach Define problem Collect and analyze input sources Develop, verify, and validate model Define scenarios and conduct simulations Analyze outputs and draw conclusions 2

3 Defining Problem Hardware Capability Verification Verify that the hardware resources meet the requirements for the radio software Software Portability Optimization Validate that a particular waveform is properly partitioned to maximize software portability while satisfying application performance System Performance Analysis Analyze end-to-end latency, component throughput, data and control bottlenecks to meet resource loading and/or critical timing requirements 3

4 Input Source Collection and Analysis Source Collection Specifications Data SCA and its Supplements, RTOS and CORBA Waveform and radio application JTR architecture Estimated and measured data Source Analysis Identify controllable and uncontrollable inputs Identify constraints on the decision variables Define system performance measure 4

5 Developing Model: Roadmap Start Model Architectural HW Model Radio SW Map Radio SW to HW then Simulate Analyze Simulation Results Timeline for this roadmap is not shown Yes Yes Change Existing Models No Satisfied? Yes Changes in HW? No Changes in Radio? No Satisfied? Yes No Model Waveform Model Waveform Model Waveform Model Waveform Map WF SW to HW then Simulate Analyze Simulation Results Exit Change HW or WF Models No Satisfied? Yes 5

6 Developing Model: Hardware Resources The architectural model describes the hardware resources used in processing or transporting the radio and waveform application data Create Models of Resource Building Blocks Build Models of HW Components Generate Models of HW Architecture Resource name and its capacity are simulation parameters for a HW component 6

7 Hardware Architecture ADC DAC FPGA DSP Black CPU Red Ch CPU Red IO Volatile MEM Volatile MEM Volatile MEM NV MEM NV MEM CORBA ORB Inside Basic Resource Process Resource 7

8 SCA Generic Building Block Process Output Port Process Output Port Input Port Input Port Software Block A Software Block B Internal Data Flow (Small Latency) External Data Flow (Large Latency) Control Flow 8

9 Tool Selection Co-Design tools provide two orthogonal views of a system Architectural and functional views - which are linked by a partitioning specification The capability for simulation of virtual system prototype A Co-Design tool by Foresight Systems 9

10 Software to Hardware Mapping Functional Design Architectural Design 10

11 A Generic Communication Model IO Driver Format Source Encode Encrypt Channel Encode Multiplex Modulate Freq Spread Red GPP-based Component Manager (GPPCM) Black GPPCM Black Non-GPPCM IO Driver Format Source Decode Decrypt Channel Decode Demultiplex Demodulate Freq Despread Transmit Receive Control 11

12 Problem Studies Base Scenario Configuration Preset for Radio Operation Scenario I HW Capability Verification Scenario II SW Portability Estimation 12

13 Base Scenario Defining Configuration Data Input Input data rate is 200 message per second Payload is 1500 bits/message Radio Resources Red GPP = 400 Million Instructions / second (MI/sec) Black GPP = 400 MI/sec DSP = 800 MI/sec Port = 500 Megabits / second (Mbps) Remote Port = 100 Mbps Waveform Utilization Red Component = MI 4 components Black Component = 0.75 MI 2 components DSP Component = 1.5 MI 2 components Port = Mb 5 ports Remote Port = Mb 3 ports 13

14 Base Scenario End-to to-end Latency Processors + Ports + Remote Ports = (4*0.375/ *0.750/ *1.5/800) + (5*0.0625/500) + (3*0.0625/100) = ( ) = sec 14

15 Base Scenario Resource Utilization Processor Utilization (%) Red GPP Black GPP DSP Data Throughput Data Throughput (bps) Time (seconds) 0 15

16 Base Scenario Latency Distribution Latency (sec) IO Data Format Source Encode Remote Encryption Remote Channel Encode Multiplexing Remote Modulation Spread Spectrum Resource Consumers Accumulative Latency Latency Distribution Accumulative Latency

17 Scenario I HW Capability Verification 17

18 Scenario I Resource Utilization Processor Utilization (%) Red GPP Black GPP DSP Data Throughput Time (seconds) Data Throughput (bps) 18

19 Scenario I Latency Distribution Latency (sec) IO Data Format Source Encode Remote Encryption Remote Channel Encode Multiplexing Remote Modulation Spread Spectrum Resource Consumers Accumulative Latency Base Avg HW Verification Accumulative Base Accumulative HW Verification

20 Scenario I HW Verification Summary Configuration Reduce Black GPP from 400 to 200 MIPS Results Black GPP utilization increased to 100% Data throughput reduced by 33% Latency increased by 68% 20

21 Scenario II SW Portability Optimization 21

22 Scenario II Resource Utilization Processor Utilization (%) Red GPP Black GPP DSP Data Throughput Data Throughput (bps) Time (seconds) 22

23 Scenario II Latency Distribution Latency (sec) IO Data Format Source Encode Remote Encryption Remote Channel Encode Multiplexing Remote Modulation Spread Spectrum Resource Consumers Accumulative Latency Base Avg SW Portability Accumulative Base Accumulative SW Portability

24 Scenario II SW Portability Summary Configuration Re-map the modem software component from DSP resource to Black GPP resource Result Black GPP utilization increased to 100% Data throughput reduced by 33% Latency increased by 119% 24

25 Conclusion Verified that hardware capability satisfied resources required by radio software Validated that a waveform partitioned to match hardware resources, and maximized software portability and performance Co-design approach helps to optimize flexibility and performance It minimizes risks and maximizes chance of successful completion 25

26 Future Work Trade studies on Message priority and length Data throughput and latency Component queue length Incoming traffic distribution Time/space partitioning Different hardware architectures Upgrade models with SCA 3.x 26