Introduction to MLM. SoC FPGA. Embedded HW/SW Systems

Transcription

1 Introduction to MLM Embedded HW/SW Systems SoC FPGA European SystemC User s Group Meeting Barcelona September 18, 2007 rocco.le_moigne@cofluentdesign.com

2 Agenda Methodology overview Modeling & simulation environment MLM presentation Benefits of presented approach 11/28/2007 Copyright CoFluent Design ESCUGM16 2

3 Company Overview Technology History Public R&D at the University of Nantes, France (Pr. Calvez) MCSE co-design methodology: Development of first tool prototypes: CoFluent Studio v persons-years of software development Patented and customer-proven technology Corporate Information CoFluent Design created in 2003 $2.6M VC funding raised in 2007 Headquarters Nantes, France Products R&D CoFluent Design, Inc. San Jose, CA Sales office & representatives: France, Germany, Israel, Japan Unique expertise in System-Level Design 11/28/2007 Copyright CoFluent Design ESCUGM16 3

4 Methodological Backgrounder SCOPE: SoCs Embedded devices GOALS: Create innovative architectures Optimize performance of systems Analyze change impact in designs Validate platforms against new features FROM PARTIAL HW AND SW DESCRIPTIONS MEANS: Modeling & simulation Input = graphics + C code Automatic SystemC code generation (MLM) & instrumentation Rich model analysis environment 11/28/2007 Copyright CoFluent Design ESCUGM16 4

5 Modeling & Simulation Environment KEY CONCEPTS: Separate behavioral & resource views Y design flow with mapping TOOLING: Graphical front-end modeling SystemC simulation library Support for abstract behavioral & architectural concepts MLM on top of TLM v1.0 TL3 Behavioral model of system s functionality Generic HW performance models No embedded software No ISS needed No hardware IPs needed Timed-Behavioral Modeling Platform Architecting Mapping Architecture Exploration 11/28/2007 Copyright CoFluent Design ESCUGM16 5

6 Timed-Behavioral Modeling Application = network of concurrent processes called functions Hierarchy of functions Higher level functions are just structuring containers Synchronous and asynchronous communications Including time information (durations) Communications, synchronizations, executions/computations Leaf functions = elementary units of execution Independent from each other, in full parallelism With their own thread of execution Behavior described as composition of computation and communication sequences Mixed control and data flow 11/28/2007 Copyright CoFluent Design ESCUGM16 6

7 Inter-Function Communications Event F1 Evt F2 Blocking wait/reset Non-blocking signal/set Shared Variable F1 Data F2 Critical section: concurrency Non-blocking write Non-blocking read Message Queue F1 MsgQ F2 Critical section: concurrency Message capacity Channel policy Blocking send on FIFO full Blocking receive on FIFO empty F1 F2 11/28/2007 Copyright CoFluent Design ESCUGM16 7

8 Graphical Front-End Modeling Refined function Operation (with algorithm as pure sequential C/C++ code) Elementary (leaf) function Communication FIFO channel (or message queue) Unconditional loop Event wait Shared variable Event generation Branch joint Concurrent wait on two inputs 11/28/2007 Copyright CoFluent Design ESCUGM16 8

9 Platform Modeling Platform = network of resource elements Computation units called processors Storage units called shared memories Communication links called nodes Independent from each other, in full parallelism Including performance information Hardware units Can run all allocated functions in parallel Software units Run one allocated function at a time Involves time sharing of the resource Abstract RTOS model, multicore Shared memories Store variables shared between multiple processors Physical links For transporting all functional relations Different types of links: point-to-point, bus, routing network 11/28/2007 Copyright CoFluent Design ESCUGM16 9

10 Generic HW Performance Models Shared-Memory Shared-Memory Mem Hardware Processor Proc2 Proc3 Processor P2 Bus Processor P3 Node Link1 Link1 ProcessorType = Hardware RelativeSpeed = AsicSpeed Software Processor MCU RTK Local Mem Local Dev Processor P1 SchedulingPolicy = PSP OverHead = 10 us ProcessorType = Software Concurrency = 1 RelativeSpeed = SwSpeed 11/28/2007 Copyright CoFluent Design ESCUGM16 10

11 HW/SW Partitioning and Mapping Functional architecture (Application) Workload definition Physical architecture (Platform) F1 Mapping (allocation) Board N1 V1 MsgQ2 P1 P2 F31 V3 Ev F2 F3 F32 Processor interfaces Communications Prospective performances 11/28/2007 Copyright CoFluent Design ESCUGM16 11

12 Y Design Flow Functional Architecture (Application) F0 MsQ1 F1 MsQ2 V1 Virtual System (SystemC) F2 Ev V3 F31 F32 F3 Performance Analysis Time & Performance Attributes Mapping Physical Architecture (Platform) Design Space Exploration P0 (HW) P1 (HW) N0 Communications network N1 M P2 (SW) Memory P0 F0 MsQ1 Interfaces and communications network N0 IntP0 IntP01 MsQ1 P1 F1 MsQ2 V1 IntP1 N1 IntP2 MsQ2 V1 P2 F2 Ev V3 F31 F32 F3 V1 M RTOS 11/28/2007 Copyright CoFluent Design ESCUGM16 12

13 Simulation & Analysis Tools Architecture profiling Performance charts Bus transactions Task scheduling Inter-function communications 11/28/2007 Copyright CoFluent Design ESCUGM16 13

14 The Message-Level Protocol The message data type includes The value of the data to transmit to the destination The source of the message, able to route the message to its destination The priority of the message The length of the message The abstract bus model fully implements The communication protocol with timing And both the arbiter and the router functions 11/28/2007 Copyright CoFluent Design ESCUGM16 14

15 Abstract Bus Model Example RequestToSend(s i ) RequestToReceive(r i ) Sender s i ReceiverIsReady s i Data DataIsReady Bus DataIsReady r i Data Receiver r i TransferIsDone TransferIsDone Transfer duration 11/28/2007 Copyright CoFluent Design ESCUGM16 15

16 MLM On Top Of TLM Sender s i port_initiator port_initiator Receiver r i port_target send(data) { Message.Data = Data; Message.m_access = ACCESS_SEND; transport(&message); } receive(pdata) { Message.ptrData = pdata; Message.m_access = ACCESS_RECEIVE; transport(&message); } Bus transport(&message) { if (Message->m_access == ACCESS_SEND) { // send protocol // implementation } else if (Message->m_acces == ACCESS_RECEIVE) { // receive protocol // implementation } } 11/28/2007 Copyright CoFluent Design ESCUGM16 16

17 IP-Based Micro-Architecture (C.A.) CPU + HW devices Environment Link model Full embedded software + IDE for crosscompilation F1 F2 Fx Real RTOS ISS CPU model HW IPs & SW drivers Memory IP Bus models LONG ITERATIONS I/F IPs HW accelerator I/F IPs Test bench IP F5 IP F6 IP HIGH HIGH EFFORT EFFORT & HIGH HIGH COST COST Memory IP + Simulation environment HW IPs 11/28/2007 Copyright CoFluent Design ESCUGM16 17

18 MLM Macro-Architecture Timedbehavioral graphical models + C code F1 F2 Fx RTOS model CPU model HW/SW interface models Data & ins. SHORT ITERATIONS Interfaces HW interfaces Test bench F5 F6 INCREMENTAL INCREMENTAL EFFORT EFFORT & LOW LOW COST COST Memory Interface Model Instructions Data MsgQ Customizable generic models of HW components 11/28/2007 Copyright CoFluent Design ESCUGM16 18

19 For More Information Articles Product data sheets Company information Market information Upon request Downloadable free books on MCSE methodology Online demos Technology white papers Workshop data sheet Training data sheets General inquiry 11/28/2007 Copyright CoFluent Design ESCUGM16 19