Processor Design Flow 1

Transcription

1 Processor Design Processor Design Flow Professor Jari Nurmi Institute of Digital and Computer Systems Tampere University of Technology, Finland ÿ Capturing requirements Functional requirements ÿ of the application(s)/workload ÿ of the operating environment Processor Design Flow 1 Non-functional requirements ÿ Functional requirements of the applications Identification of (typical, representative, all?) algorithms to be executed Finding instruction primitives to support these algorithms Profiling of algorithms ÿ full algorithms (e.g. GSM half-rate speech codec, MPEG-4, Viterbi) ÿ algorithm kernels, inner loops (e.g. codebook search, motion estimation) ÿ forehead-profiling of the application ÿ pitfall: profiling with an existing processor may be misleading! 1 1

2 Misleading Profiling? ÿ E.g. ADPCM encoder - decoder Profiling with old Sun workstation with no support for ÿ exponent extraction ÿ multibit shifting based on register value indicated a huge number of cycles for scaling of results On the other hand, profiling with Analog Devices 2151 DSP with ÿ hardware resources for exponent extraction ÿ barrel shifter yielded completely different results and indicated better the requirements of the algorithm when implemented efficiently ÿ Profiling a real source code with an existing processor Function of the instruction set of the old processor Function of the compiler ability to optimize for the target Processor Design Flow 2 ÿ Functional requirements of the operating environment Requirements of the (real-time) operating system Requirements of the memory subsystem Requirements of I/O to be attached to the processor Requirements of the software tools Clock cycle, throughput, latency requirements by the environment ÿ Non-functional issues Cost, power consumption Design tool compatibility SW tool compatibility, backwards compatibility EMC restrictions Manufacturability, testability, maintainability Acceptable failure rate, etc. 2 2

3 Preparing for the Future? ÿ Maintaining a certain degree of general-purposity Elementary support for rare operations (not judging them impossible) Elementary support for rare addressing modes ÿ The old Patterson Hennessy truth! Make the common case fast Make the rare case correct ÿ Future requirements There will be more applications than we can think of We should be wizards to foresee all of them! Or leave some room for extensions or configurability in the core Processor Design Flow 3 ÿ We know the required operations addressing modes data types ÿ Now we need to design the actual instruction set and its coding Iterative task Restricted by the cost/performance requirements Has a major effect on the organizational architecture as well ÿ This is so important that we will devote a complete lecture on this later on! ÿ Needs hands-on experience exercises 3 3

4 Processor Design Flow 4 ÿ Implications of the instruction set to the resources needed Arithmetic and address calculations Data registers Data transfers, buses Control structures and registers ÿ Exploration of organizational architectures Pen-and-paper methods Spread-sheet calculations of cycle counts etc. Using specification languages WITH automatic performance estimator or simulator generation (strongly recommended) ÿ Estimation of the foreseen implementation(s) Fitting to the non-functional specification (e.g. cost, power)? Achieving the target cycle time? critical paths? severe bottlenecks? Processor Design Flow 5 ÿ Development of the HW ASIC design flow for the HW Accompanying HW models for developing application systems ÿ Software tools and libraries Essential for the adoption of the processor Egg chicken problem (which first, HW or SW?) Ungrateful co-development and co-debugging of ÿ program ÿ SW tools ÿ HW platform Assembler, linker, disassembler, ISS/debugger High-level language compiler (e.g. C/C++) RTOS application examples and libraries 4 4

5 Processor Design Flow APPLICATION REQUIREMENT CAPTURE DESIGN & CODING INITIAL ABSTRACT FINAL & INITIAL ARCHITECTURE ASIC HW FLOW SW TOOLS FLOW ENVIRONMENT REQUIREMENT CAPTURE EXPLORATION OF ARCHITECTURES NON- ESTIMATION AUGMENTED ABSTRACT ARCHITECTURE FINAL & FINAL ARCHITECTURE PROCESSOR TOOLS & HW IMPLEMENTATION End of processor design flow next we will look at instruction coding issues 5 5