Managing Dynamic Partial Reconfiguration on Embedded SDR Platforms

Transcription

1 ' ( %& ( ) &*++, Authors: Jean-Philippe Delahaye Christophe Moy Pierre Leray Jacques Palicot Managing Dynamic Partial Reconfiguration on Embedded SDR Platforms Christophe MOY Associate Professor at Supélec!"#"$ %& % UMR

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4 %0 &%& SDR multi-standard terminal architecture Classical approach: Multiple architecture for multiple standards Software-Defined Radio approach : Single architecture for multiple standards Mode 1 Mode 2 Mode n Terminal with duplicated HW for each standard Terminal with a common configurable computing architecture for all standards SDRF Technical Conference 05 - November Anaheim 4

5 %& INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES Our view of configuration management PHY Goals adapt signal processing functionality to the radio application needs perform reconfiguration over heterogeneous computing resources control the reconfiguration process Constraint run-time reconfiguration requirements SDRF Technical Conference 05 - November Anaheim 5

6 '&%& Configuration management units (CMU): distributed over processing blocks INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES Configuration Path Config. Manager Unit 1 Config. Manager Unit 2 Config. Manager Unit N Processing Block Unit 1 Processing DataPath Processing Block Unit 2 Processing Block Unit N Different kinds of CMU processing nature underlying hardware depth of reconfiguration Config. Manag. Unit Configuration Path Unit Function Config. Info Time to Config. Current Function State of Config. Configuration Config. Info Data Validity Manager Config. link {Config Control} Data Configurable IN Data OUT Processing Resources Processing DataPath Unit SDRF Technical Conference 05 - November Anaheim 6

7 ! & &%& Expected scenarios standard changing mode changing service changing performance enhancement bug fixing higher granularity Data IN Processing Block 1 Processing Block 2 f 1,1 f n,1 f i,i f 1,n f n,n Processing Block N Data OUT SDRF Technical Conference 05 - November Anaheim 7

8 1& &( %& Identified constraints for SDR distributed management multi-granularity issue in function of the HW support INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES L1_CM : Global manager Standard parameter control Dispatches orders to lower layers Config. Management Level 1 Config. Manager L1_CM Standard Set! "! L2_CMUs : Function Level Independent of the HW Manages several elementary PBprocessing blocks of lower granul. Config. Management Level 2 L2_CMU Function Set L2_CMU Function Set L2_CMU Function Set L2_CMU Function Set L3_CMUs : Processing blocks configuration Embedded very closely to the PB Dedicated to the nature of reconfigurable resources L3_CMU Block Set Config. Management Level 3 L3_CMU Block Set L3_CMU Block Set SDRF Technical Conference 05 - November Anaheim 8

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10 & % & Baseband transmitter chain GSM (Voice, mono carrier) UMTS (Data, High Mobility, CDMA ) g OFDM Mode (High Data rate, multi-carrier) # Coding functions Data structuring functions Modulation functions Code 1 (Block) Code 2 (convoluti onal) Reordering and Partitioning Interleaving Cryptological unit Burst Bulding Burst Multiplexing Differential encoding Filtering $%$%&'(( Code Code 1 1 (CRC) (CRC) Block concat/segmen Code 2 (conv. ou turbo) Frame Frame equalisation equalisation Interleaving Interleaving (1 (1 st st ) ) Frame segment. Rate matching TrChannel Multiplex PhyCha segmentation Interleaving Interleaving (2 (2 nd nd ) ) Mapping Spreading Scrambling Filtering )*!+,( Scrambling Code 2 Puncturing (convoluti onnel) Interleaving Mapping OFDM Modulation Filtering SDRF Technical Conference 05 - November Anaheim 10

11 % & Classification of processing functions in 3 classes depending on processing nature INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES Data Structuring Class Memory Intensive Coding Class Flexibility Intensive Modulation Class Computation Intensive deduction of the mapping on 3 clusters HW resources Array of MemBlocks µp DSP CoP CoP CoP FPGA DSP HAcc. HAcc. SDRF Technical Conference 05 - November Anaheim 11

12 ! & Distributed processing Heterogeneous processing devices depending on processing nature INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES 3 clusters of HW resources Different architecture granularities have to considered depending on processor and processing nature Very close to configuration management considerations Both can easily be merged in the global SDR system design SDRF Technical Conference 05 - November Anaheim 12

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14 1& &( % &(& Combine both reconfiguration management - hierarchical data processing - distributed INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES " #! Config. Manager L1_CM Standard Set Coding PC Data Structuring PC Modulation PC L2_CMU Function Set L3_CMU Block Set L2_CMU Function Set L3_CMU Block Set L2_CMU Function Set L3_CMU Block Set PF 3 PF 1 PF 2 PF 5 PB 1 PB 2 PB 3 PF 4 PB 5 PB 4 Processing cluster level Processing Function level (independent of the HW) Processing Blocks level (deployed on the HW) SDRF Technical Conference 05 - November Anaheim 14

15 &(& INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES && )0 Hierarchical approach for SDR system Design L1_CM + µp L2_CMUs Fct µp Program Mem. L2_CMUs Fct µp Program Mem. L2_CMUs Fct µp Program Mem. L3_CMUs L3_ CMUs L3_ CMUs Core µp Cop1 DSP Core µp Array of BlockRAM µp Core µp HW Acc1 DSP DMA Data Mem. Data Mem. Data Mem. Coding Cluster Data Structuring Cluster Modulation Cluster SDRF Technical Conference 05 - November Anaheim 15

16 ! %( INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES % &(& HW platform composed of 3 processing units L1_CM + µp Extern. Storage Mem Standards Parameters GPP Standards Parameters T 1_L1_CM L2_CMUs Fct µp Program Mem. Fct Core Fct Lib. Core Fct Lib. Core T 1_DS T 2_DS T 4 T 3_DS L3_ CMUs Core µp Modulation Cluster HW Acc1 DSP FPGA Soft µp Core T 1_L3 DSP Fct T 1_L2 T 1_L3 Data Mem. HW Acc HW Acc Cop Cop Cop Configurable Array of BlockRAM T 2 _Md T3 _Md T1_Md SDRF Technical Conference 05 - November Anaheim 16 T 4_Cd

17 Heterogeneous processing units & %& GPP+Memory : host PC FPGA : Xilinx Virtex II DSP : TI C64 Extern. Storage Mem Fct Core Standards Parameters Fct Lib. Core Fct Lib. Core GPP T 1_DS Standards Parameters T 2_DS T 1_L1_CM T 4 T 3_DS FPGA Soft µp Core T 1_L3 DSP Fct T 1_L2 T 1_L3 HW Acc HW Acc Cop Cop Cop Configurable Array of BlockRAM T 2 _Md T3 _Md T1_Md T 4_Cd SDRF Technical Conference 05 - November Anaheim 17

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19 & &%& %/ Partial reconfiguration save reconfiguration time save bandwidth for OTAR by downloading FPGA context dissuasive time of total reconfiguration for large FPGA (~100 ms per million gates - Virtex) memory limitations to store total bitstreams control resource savings a plurality of successive designs instead of heavy control state machines permits to modify the structure of a design SDRF Technical Conference 05 - November Anaheim 19

20 /( % &(& Common operator approach parameters change the operator functionality managed at the L3_CMU level FPGA fixed area for management contents Processor CORE (µblaze/ppc for Xilinx) operators dedicated state machines FGPA dynamically reconfigurable area operators parameters (managed by L3_CMU) intra-operator routing (managed by L3_CMU) inter-operator data flow changes (m.b. L2_CMU) INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES SDRF Technical Conference 05 - November Anaheim 20

21 / INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES & &%& Module-based design flow on Virtex II devices Object 1!!$% Object 2! FPGA " & '( Multi-objects in large FPGAs FPGA Obj. 1 Obj. 2!!$% Obj. 3 Obj. 2! FPGA " & FPGA SDRF Technical Conference 05 - November Anaheim 21

22 DSP device downloads bitstreams through SelectMap interface SRAM bitstream storage 2& &%& Reconfigurable Reconfigurable Logic Parts Logic Columns FPGA Configuration management external L2_CMU on DSP R ToT F B U S Fixed Logic Parts SRAM Bitstream Storage DSP µp Config. controller Interface Controller SelectMap/JTAG link Configuration transfert (bitsream) L3_CMU wired in the FPGA within or close to operators SDRF Technical Conference 05 - November Anaheim 22

23 µblaze Read/write bitstreams into ICAP Boot loader if no DSP initial config. instanciates ICAP, µblaze & &%& Reconfigurable Logic Parts FPGA Configuration management R ToT F B U S RTF R2F Interface P PC/µBlaze Config. controller ICAP Controller CoreConnect ICAP PLB/OPB ICAP internal L2_CMU: µblaze embedded in the FPGA flexible L3_CMU: µblaze embedded in the FPGA ComPort or/and L3_CMU wired in the FPGA within operators SRAM Bitstream Storage Boot Loader SDRF Technical Conference 05 - November Anaheim 23

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25 Multi-level granularity needs for reconfiguration of SDR have been identified Hierarchical configuration management to optimize reconfiguration is proposed Multi-standard functional architecture model Deduction of an SDR architecture applicable to any hardware platform Support any partial reconfiguration of the SDR processing chain Illustrated by a FPGA partial reconfiguration implementation SDRF Technical Conference 05 - November Anaheim 25

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